JPH104353A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the A/D conversion time of a voltage to be measured. SOLUTION: The A/D converter is provided with an integration device consisting of an operational amplifier 11, of a capacitor 12, and of resistors 13a, 13b and a comparator 14 that compares a center voltage Vref between a ground level and a power supply voltage VDD with an output voltage Vo of the integration device (operational amplifier 11), and the integration device integrates a voltage averaging a measured voltage Vin and the power supply voltage VDD to decrease its output voltage Vo for a prescribed time ta after an output of the comparator 14 is inverted and then the integration device integrates the ground level to increase the output voltage Vo, a time Tb from the start of integration of the ground level till the output of the comparator 14 is again inverted is measured and then the measured voltage Vin is converted into a digital voltage based on a ratio of the times as above (Tb/Ta). A coding circuit TAD 22 capable of binary-coding a time with a minimum resolution of an inverting operating time of an inverter measures the times Ta, Tb as above.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog voltage to a digital value, and more particularly to an integral A / D converter.

[0002]

2. Description of the Related Art Conventionally, when an actuator or the like is controlled in accordance with an analog signal from a sensor, an A / D converter is required. As a device capable of high-precision A / D (analog / digital) conversion, for example, “AD
/ DA conversion circuit introduction: written by Iwao Sagara, Nikkan Kogyo Shimbunsha.

Here, a conventional basic integrating A / D converter has a predetermined reference voltage Vre, as shown in FIG.
f (in this example, ground potential = 0 V) is applied to the non-inverting input terminal, the integrating capacitor 2 connected between the output terminal of the operational amplifier 1 and the inverting input terminal, and the operational amplifier 1 An integrator (more specifically, a Miller integrator) composed of an integrating resistor 3 having one terminal connected to the inverting input terminal; and an output voltage Vo of the integrator (operational amplifier 1) and a predetermined comparison voltage VC. The comparator 4 to be compared and a terminal 5 (hereinafter referred to as an input terminal) on the opposite side of the inverting input terminal of the integrating resistor 3 have a voltage under measurement Vin and a voltage under measurement Vin which are relative to the reference voltage Vref. A changeover switch 6 for switching and applying a predetermined set voltage -VR of the opposite polarity, a control circuit 7, and a clock generator 8. Then, the control circuit 7 controls the changeover switch 6 according to the output signal of the comparator 4 so that the voltage applied to the input terminal 5 is changed to the measured voltage Vin and the set voltage −VR.
And the digital amount of the measured voltage Vin is obtained.

That is, as shown in FIG. 14 (B), the control circuit 7 sets a predetermined time T at the input terminal 5 from the time when the output voltage Vo of the integrator matches the comparison voltage VC.
By applying the measured voltage Vin by 1 and during this time T1,
An integrator integrates the measured voltage Vin and outputs the voltage Vo.
Then, the voltage applied to the input terminal 5 is switched to the set voltage -VR, and the integrator integrates the set voltage -VR to increase the output voltage Vo of the integrator.
Then, after the set voltage -VR is applied to the input terminal 5 (that is, after the integration of the set voltage -VR is started), the output voltage Vo of the integrator reaches the comparison voltage VC, and the output signal of the comparator 4 becomes The time T2 until inversion is measured.

Then, if there is no offset voltage of the comparator 4, the following equation 1 is established, and the following equation 2 is established from the equation 1. Note that in Equation 1, “式 _ (0) ^ (t1) [Vi
n−Vref] dt ”is the measured voltage Vin and the reference voltage Vref.
[Vin−Vref] from time “0” to time “t1”
The values 0 to t1 correspond to the time T1 in FIG. Similarly, “∫_ (0) ^ (t2) [−
[VR-Vref] dt "is the set voltage -VR and the reference voltage Vref.
The difference [−VR−Vref] from time “0” to time “t”
2 ", and 0 to t2 correspond to time T2 in FIG. 14B. “C” is the capacitance of the integrating capacitor 2, “R” is the resistance value of the integrating resistor 3, and Vref = 0 in this example.

[0006]

１ (0) ^ (t1) [Vin−Vref] dt / CR = Vin × T1 / CR = −∫_ (0) ^ (t2) [− VR−Vref] dt / CR = VR × T2 / CR… (1)

[0007]

(2) Vin / VR = T2 / T1 (2) As can be seen from the above equation (2), the ratio (Vin / VR) between the measured voltage Vin and the known VR is determined by the measured time T2. It matches the ratio (T2 / T1) to the known time T1.

Therefore, in the conventional integrating A / D converter, the control circuit 7 measures the time T1 by counting the clock from the clock generator 8 by a predetermined count value N1. Set voltage -V to input terminal 5
The clock output from the clock generator 8 is counted between the time when R is applied and the time when the output signal of the comparator 4 is inverted, and the count value N2 is measured as the time T2. Then, the count values N2, N
1 (N2 / N1) is the ratio (T2) of the times T2 and T1.
2 / T1), the control circuit 7 converts the digital signal indicating the ratio (N2 / N1) of the count values N2 and N1 to the ratio (Vin / V1) between the measured voltage Vin and the known voltage VR.
R) is output as a digital signal, thereby performing A / D conversion of the measured voltage Vin.

As described above, in the basic integrating A / D converter, the output voltage Vo of the integrator is compared with the comparison voltage VC of the comparator 4 by integrating the voltage to be measured Vin only during the fixed time T1.
The voltage Vin to be measured is converted into a digital value by integrating the known set voltage -VR and measuring the time T2 until the output voltage Vo of the integrator returns to the comparison voltage VC. Then, as can be seen from the fact that the parameters of “C” and “R” are not included in Equation 2, the A / D conversion can be performed without being affected by the variation of the elements.

However, the basic integral type A /
In the D converter, the measured voltage Vin is compared with the reference voltage Vref.
There is a problem that a set voltage -VR of the opposite polarity is required, and both positive and negative power supplies must be provided. In addition, when configured to operate with a single power supply, there is a problem that the voltage range of the measured voltage Vin capable of A / D conversion is narrowed.

That is, in order to operate the above-mentioned integrating A / D converter with a single power supply VDD (a power supply whose voltage value is VDD with respect to the ground potential), for example, in FIG. , The reference voltage Vref applied to the operational amplifier 1
A predetermined voltage (for example, VDD) between the ground potential and the power supply voltage VDD.
/ 2), and a ground potential (0 V) is input to one of the changeover switches 6 instead of the above-mentioned set voltage -VR.

However, if such a configuration of a single power supply is adopted, the measured voltage Vin becomes the reference voltage Vref (= VDD / 2).
If the voltage to be measured Vin is lower than the reference voltage Vref,
The output voltage Vo of the integrator at the time T1 shown in FIG.
Does not decrease, the output voltage Vo changes in the same direction when the measured voltage Vin is integrated and when the ground potential as the set voltage is integrated, and A / D conversion cannot be performed. That is, if the measured voltage Vin and the set voltage to be integrated have the same polarity with respect to the reference voltage Vref of the integrator, the output voltage Vo of the integrator when integrating both voltages changes in the same direction. Therefore, A / D conversion cannot be performed, and as a result, the measured voltage Vin capable of A / D conversion is limited to a range from the reference voltage Vref to the power supply voltage VDD.

Further, in the above-mentioned basic integrating A / D converter, there is a problem that a measurement error occurs due to the offset voltage of the comparator 4. Therefore, as an integral type A / D converter capable of expanding the range of the measured voltage Vin capable of A / D conversion and eliminating the influence of the offset voltage of the comparator 4, for example, "Toshiba CMOS AD"
Converter Data Book: 1990 Edition "and JP-A-53-101966.
A five-phase integration system has been proposed.

The five-phase integral type A / D converter is shown in FIG.
It is configured as shown in FIG. That is, in the case of the five-phase integration type, the input terminal 5 supplies the measured voltage Vin, the predetermined voltage VR having the same polarity as the measured voltage Vin, and the ground potential VG to the A / D converter shown in FIG. (= 0 V) is selectively inputted by three changeover switches S1, S2, and S3, respectively, and the reference voltage Vref applied to the non-inverting input terminal of the operational amplifier 1 is equal to the predetermined voltage VR and the ground. Potential V
The difference is that an intermediate voltage (= VR / 2) with G is set. The measured voltage Vin and the predetermined voltage VR
And the ground potential VG is such that VR>Vin> VG.

The operation of the five-phase integral type A / D converter will be described below with reference to the time chart of FIG. In the following description, the changeover switches S1 to S3
(ON / OFF) is performed by the control circuit 7. Further, a time T3, which will be described later, executed by the control circuit 7,
The measurement of T4 is performed by counting the clock from the clock generator 8, just like the case of the A / D converter shown in FIG.

"State 1 and state 2" First, in state 1,
The changeover switch S2 is turned on (short-circuited) for a predetermined time T3, and during this time T3, the integrator integrates the predetermined voltage VR to lower its output voltage Vo. Then, in the next state 2, the changeover switch S3 is turned on, the integrator integrates the ground potential VG to increase the output voltage Vo, and this state is maintained until the output signal of the comparator 4 is inverted (that is, the output voltage (Until Vo reaches the comparison voltage VC of the comparator 4).

Here, since the end of the state 2 is determined by inverting the output signal of the comparator 4, the output voltage Vo of the integrator at the end of the state 2 is set to the comparison voltage VC by the comparison voltage VC. The voltage (VC + V) to which the offset voltage VOF is added
OF). Then, in state 3 to be described later, integration is started with this voltage (VC + VOF) as a starting point. When state 5 to be described later ends, the output voltage Vo of the integrator is equal to the voltage (VC
(+ VOF) again, so that the offset voltage VOF of the comparator 4 is not affected. still,
In the following description, the above voltage (VC + VOF) is referred to as the comparison voltage VC again.

"State 3" Next, in state 3, the changeover switch S2 is turned on for a time T3, and during this time T3, the integrator integrates the predetermined voltage VR to lower the output voltage Vo. Then, the output signal of the comparator 4 is inverted in a direction opposite to the inversion direction at the end of the state 2. The output voltage Vo (3) at the end of the state 3 is calculated by the following equation (3).
become that way.

[0019]

Vo (3) = VC− (VR−Vref) × T3 / CR (3) “State 4” In the next state 4, the changeover switch S1 is set to the time T
3 and the integrator integrates the measured voltage Vin during this time T3. Therefore, the output voltage Vo of the integrator at this time follows various paths according to the magnitude of the measured voltage Vin, as shown by the dotted line in FIG. In this figure, a dotted line a indicates a case where the measured voltage Vin is equal to the ground potential VG, a dotted line b indicates a case where the measured voltage Vin is equal to the reference voltage Vref, and a dotted line c indicates
This shows a case where the measured voltage Vin is equal to the predetermined voltage VR. Then, the output voltage Vo (4) at the time when the state 4 ends.
Is as shown in Expression 4 below.

[0020]

Vo (4) = Vo (3) − (Vin−Vref) × T3 / CR (4) “State 5” In the last state 5, the changeover switch S
3 is turned on, the integrator integrates the ground potential VG to increase the output voltage Vo, and this state is continued until the output signal of the comparator 4 is again inverted in the inversion direction at the end of the state 2. Therefore, if the time from when the changeover switch S3 is turned on (that is, when the state 5 starts) to when the output signal of the comparator 4 is inverted is T4, the output voltage Vo (5) at the time when the state 5 ends is Equation 5 below.

[0021]

Vo (5) = Vo (4) − (VG−Vref) × T4 / CR = VC (5) Here, the ground potential VG is 0 V, and is applied to the non-inverting input terminal of the operational amplifier 1. Since the reference voltage Vref is one half (= VR / 2) of the predetermined voltage VR, the measured voltage Vin is given by the following equation 6 from the above equations 3 to 5.

[0022]

## EQU6 ## Vin / VR = (T4 / T3) / 2 (6) As can be seen from Expression 6, the time T3 and the set voltage V
Since R is known, the measured voltage Vin is converted into a digital value by the value of the measured time T4.

That is, in the five-phase integration method, in the state 3 in which the A / D conversion is substantially started, the output voltage Vo of the integrator is integrated by integrating the predetermined voltage VR set higher than the reference voltage Vref. Is lowered from the comparison voltage VC, and the voltage under test Vin is integrated for the first time in the next state 4, so that the value of the voltage under test Vin becomes the reference voltage Vref (= VR /
2) Even if the output voltage Vo of the integrator does not decrease as indicated by the dotted lines a and b in FIG. 15B, the A / D conversion of the measured voltage Vin is possible even if the value is smaller than 2). I am trying to be.

Further, in the A / D converter of the five-phase integration method, in state 1 and state 2, the integration of the predetermined voltage VR and the integration of the ground potential VG are sequentially performed, so that the output signal of the comparator 4 is obtained. The signal is inverted in a predetermined direction, and from the time when the output signal of the comparator 4 is inverted in this manner, the substantial A
The state 5 is terminated when the / D conversion operation is started and the output signal of the comparator 4 is again inverted in the predetermined direction, so that the state 5 is not affected by the offset voltage of the comparator 4 and is not affected. A / D conversion of the measurement voltage Vin becomes possible.

[0025]

As described above, the integral type A
In the / D converter, conceptually, the ratio of the integration time when the unknown measured voltage and the preset known setting voltage are integrated so that the output change amount of the integrator becomes equal is obtained. The measured voltage is converted into a digital value based on the above. As described above, the conventional A / D converter measures the integration time by counting the clock from the clock generator. Therefore, there is a problem that the time required for A / D conversion cannot be shortened.

In other words, in order to increase the accuracy of the A / D conversion, the number of clocks to be counted when measuring the integration time is set to be large to increase the measurement resolution of the integration time. , Use a high frequency clock,
Alternatively, it is necessary to lengthen the integration time by increasing the time constants of the integrating capacitor and the resistor constituting the integrator. However, an ordinary fixed oscillator used as a clock generator can generate only a clock of about several tens of MHz, so in order to further improve the measurement resolution of the integration time, the time constant of the integrator must be set large. As a result, the integration time becomes longer, and the time required for A / D conversion of the measured voltage becomes longer.

On the other hand, the A / D of the five-phase integral equation shown in FIG.
According to the converter, the range of the voltage Vin under which the A / D conversion can be performed can be expanded.
As shown in "State 3", a period for integrating the predetermined voltage VR must be provided before integrating the measured voltage Vin, and the time required for the A / D conversion becomes longer.

Further, according to the five-phase integral type A / D converter, the influence of the offset voltage of the comparator can be removed, but for this purpose, the "state 1" shown in FIG. As in "State 2", a period must be provided for sequentially integrating the predetermined voltage VR and the ground potential VG before starting the substantial A / D conversion operation, which is required for A / D conversion. Time will be long.

The present invention has been made in view of such a problem, and has as its object to provide an A / D converter that can reduce the A / D conversion time of a measured voltage.

[0030]

Means for Solving the Problems and Effects of the Invention The A / D converter according to the first aspect of the present invention is provided with an integrator for integrating an input voltage and outputting the integrated voltage. The integration control means integrates one of the voltage according to the voltage to be measured and the preset voltage into the integrator until a predetermined condition is satisfied. A first control operation for measuring an integration time as a first integration time; and a voltage corresponding to a voltage to be measured and the other of the set voltages, which are different from those integrated by the first control operation, are supplied to the integrator. A second control operation is performed in which integration is performed, and a time until the output change amount of the integrator coincides with the output change amount of the integrator by the first control operation is measured as a second integration time. Then, the A / D converter is connected to the first integration time measured by the integration control means and the second integration time.
The measured voltage is converted into a digital value based on the ratio with the integration time.

That is, in the A / D converter, a voltage corresponding to the unknown voltage to be measured and a known voltage set in advance are integrated so that the output change of the integrator is equalized. , Both integration times (first integration time and second integration time)
The measured voltage is converted into a digital value based on the ratio.

The voltage according to the voltage to be measured may be the voltage to be measured itself, for example, a voltage obtained by amplifying the voltage to be measured at a predetermined ratio or a voltage between the voltage to be measured and a known voltage. A voltage obtained by averaging may be used. Here, in particular, in the A / D converter according to the first aspect, the integration control means includes the first control section.
As timing means for measuring the integration time and the second integration time, a plurality of inverting circuits for inverting and outputting an input signal are connected, and a delay circuit for sequentially inverting and transmitting a pulse signal by each inverting circuit is provided, An encoding unit capable of binary encoding the time using the phase difference time of the pulse signal sequentially output from a plurality of predetermined inversion circuits among the inversion circuits constituting the delay circuit as a resolution. The integration control means uses the encoding means to calculate the first integration time and the second integration time.
Measure the integration time.

According to the A / D converter according to the first aspect, the inversion operation time of each inversion circuit constituting the delay circuit is very short, about several hundred psec. The first integration time and the second integration time can be measured using the doubled time as the measurement resolution. Therefore, the conventional A / D
The A / D conversion accuracy can be increased by increasing the integration time measurement resolution without setting the integration time longer as in a converter. As a result, the A / D conversion of the measured voltage can be performed with high accuracy. It can be performed in a short time.

Furthermore, since it is not necessary to set the integration time long, the capacitance of the integrating capacitor constituting the integrator and the resistance value of the integrating resistor can be reduced, and the A / D converter can be reduced. Can be reduced when integrated on a single semiconductor chip.

Next, in the A / D converter according to the second aspect, in the A / D converter according to the first aspect, the delay circuit of the encoding means includes an inverting circuit connected in a ring shape and a delay circuit. A specific inverting circuit of the inverting circuits is configured as a starting inverting circuit capable of controlling an input signal inverting operation by a first external signal, and the starting inverting circuit starts the inverting operation. A pulse circulating circuit for sequentially inverting and circulating the pulse signal by each inverting circuit is also provided.

Further, in addition to the pulse circulating circuit, the encoding means counts the number of times the pulse signal circulates in the pulse circulating circuit, and outputs a binary digital signal representing the counted number; A latch circuit that latches and outputs a binary digital signal from the counter when a second signal is input from the outside, and outputs signals of a plurality of predetermined inverting circuits among inverting circuits constituting a pulse recirculation circuit When the second signal is input, a pulse signal generated by the start of the inversion operation of the start-up inversion circuit detects which of the inversion circuits in the pulse recirculation circuit has reached the start-up inversion circuit. A pulse detection circuit that outputs a binary digital signal according to the number of inversion circuits from the inversion circuit to the inversion circuit that has detected that the pulse signal has arrived. The encoding means uses the binary digital signal from the latch circuit as the upper bit and the binary digital signal from the pulse detection circuit as the lower bit to indicate the phase difference between the first signal and the second signal. It is configured to output a binary digital signal.

The encoding means having such a pulse circulating circuit is disclosed in Japanese Unexamined Patent Application Publication No.
JP-A-220814, JP-A-6-216721, JP-A-7-183800, and JP-A-7-2
No. 83722 discloses a pulse phase difference encoding circuit in detail.

That is, in this encoding means, the first signal is input to the inverting circuit for starting the pulse circulating circuit to start the pulse circulating operation of the pulse circulating circuit, and then the second signal is supplied to the latch circuit and the pulse detecting circuit. When input to the circuit, the counter and the latch circuit detect how many times the pulse signal has circulated on the pulse circulating circuit between the input of the first signal and the input of the second signal. The pulse detection circuit detects which of the inversion circuits in the pulse circulation circuit has reached the pulse signal when the signal is input. Then, the binary digital signal (that is, the count value of the counter) from the latch circuit is set as the upper bit, and the binary digital signal with the binary digital signal from the pulse detection circuit as the lower bit is input after the first signal is input. The pulse signal represents a value corresponding to the total number of inverting circuits in which the pulse signal has propagated (that is, has performed an inverting operation) until the second signal is input, and further, a phase difference between the first signal and the second signal. (That is, the input time difference) is output as a binary digital signal obtained by encoding the inversion operation time of each inversion circuit or a time several times the inversion operation time.

In this case, in particular, in the A / D converter according to the second aspect, when the integration control means starts the first control operation and causes the integrator to start integration of the one voltage, the starting is performed. A first signal is output to the inverting circuit for use to start a pulse circulating operation of the pulse circulating circuit. Thereafter, when a predetermined bit of the counter changes, the first control operation is terminated assuming that the predetermined condition is satisfied, and The second control operation is started to cause the integrator to start integrating the other voltage. After that, when the output change amount of the integrator matches the output change amount of the integrator by the first control operation, the latch circuit and the The second signal is output to the pulse detection circuit.

That is, in the A / D converter according to the second aspect, the integration control means starts the pulse circulating operation of the pulse circulating circuit in the first control operation and then changes the predetermined bit of the counter. During this period, the one voltage is integrated by the integrator, and the integration time (that is, the first integration time) is measured by the pulse circulation circuit and the counter of the encoding means. Therefore, it is assumed that the second signal is output to the latch circuit and the pulse detection circuit at the time when the integration of the one voltage is completed (that is, when the predetermined bit of the counter is changed and the first integration time is completed). The binary digital signal output from the encoding means at that time is a binary digital signal (hereinafter referred to as a binary digital signal) in which a bit corresponding to a predetermined bit of the counter is “1” and all lower bits are “0”. , Switching binary digital signal).

When the predetermined bit of the counter changes and the first control operation is completed, the integration control means shifts to the second control operation and causes the integrator to integrate the other voltage.
Thereafter, when the output change amount of the integrator matches the output change amount during the first integration time (that is, the output change amount of the integrator due to the first control operation), the second signal is sent to the latch circuit and the pulse detection circuit of the encoding means. Is output. Therefore, the binary digital signal output from the encoding means at this time is a binary digital signal obtained by adding the binary digital signal representing the second integration time to the above-described binary digital signal at the time of switching, that is,
2 representing a time obtained by adding the first integration time and the second integration time
Therefore, a binary digital signal representing the second integration time can be obtained simply by subtracting the switching binary digital signal from the binary digital signal.

Further, if it is previously determined that the second integration time is shorter than the first integration time for integrating the one voltage, the sign is output after the integration control means outputs the second signal. In the binary digital signal output from the converting means,
The bit group lower than the bit corresponding to the predetermined bit of the counter directly indicates the ratio between the first integration time and the second integration time. In this case, the integration control means outputs the second signal. In the binary digital signal output from the encoding unit later, a group of bits lower than the bit corresponding to the predetermined bit of the counter can be directly used as a signal obtained by converting the voltage to be measured into a digital value.

As described above, according to the A / D converter of the second aspect, the integration time can be measured with the inversion operation time of the inversion circuit or a time several times as long as the measurement resolution. A / D conversion of the measured voltage can be performed with high accuracy and in a short time, and this effect can be obtained with a simple configuration.

In the A / D converter according to the first aspect, the predetermined condition for determining the time for integrating the one voltage (first integration time) is as follows. As in the case of a converter, it may be until the predetermined time elapses, or as in claim 3, it may be until the output voltage of the integrator changes by the predetermined voltage. .

That is, as a first control operation, the integration control means integrates the one voltage into the integrator until the output voltage of the integrator changes by a predetermined voltage. At the same time, even if the time required for the change is measured as the first integration time, the voltage corresponding to the unknown voltage to be measured and the previously set known voltage are used as the output change amount of the integrator. When integrated to be equal,
The measured voltage is converted into a digital value based on the ratio of the two integration times. In this case as well, the A / D conversion is performed with high accuracy by measuring the integration time by the encoding means according to claim 1. It can be performed in a short time. On the other hand, an A / D converter according to a fourth aspect of the present invention provides an operational amplifier in which a predetermined reference voltage Vref is applied to a non-inverting input terminal, and an integration circuit connected between the output terminal and the inverting input terminal of the operational amplifier. And an integrating resistor having one terminal connected to the inverting input terminal of the operational amplifier, and integrates a voltage input to a terminal of the integrating resistor opposite to the inverting input terminal. Then, an integrator that outputs from the output terminal of the operational amplifier, an output voltage Vo of the integrator and a predetermined comparison voltage V
And a comparator for comparing C with the size.

Then, the initial setting means causes the output signal of the comparator to be inverted in a predetermined direction from the high level to the low level or from the low level to the high level.
When the output voltage Vo of the integrator is changed and the output signal of the comparator is inverted by the operation of the initial setting means, the integration control means sets the integration voltage for a first integration time set from that time onward.
The integrator integrates a voltage corresponding to the voltage to be measured, and changes the output voltage Vo of the integrator so that the output signal of the comparator is inverted in the direction opposite to the predetermined direction. Further, after the first integration time has elapsed, the integration control means integrates the preset voltage in the integrator, and the output signal of the integrator inverts the output signal of the comparator again in the predetermined direction. The time from the start of the integration of the set voltage to the inversion of the output signal of the comparator is measured as a second integration time. Then, the A / D converter converts the measured voltage into a digital value based on a ratio between the first integration time and the second integration time.

That is, in the A / D converter according to the present invention, when the output voltage Vo of the integrator is changed by the initial setting means and the output signal of the comparator is inverted in a predetermined direction. As in the conventional A / D converter shown in FIG. 14, the integrator integrates a voltage corresponding to the voltage to be measured for a first integration time from that point, and the output voltage Vo of the integrator is calculated as follows. After the first integration time has elapsed, the output signal of the comparator is separated from the comparison voltage VC of the comparator so that the output signal is inverted in the direction opposite to the predetermined direction. The time from when the output voltage Vo of the integrator is returned to the comparison voltage VC of the comparator and the integration of the set voltage is started until the output signal of the comparator is again inverted in the predetermined direction is defined as a second integration time. I measure it.

Then, from the time when the output signal of the comparator is inverted in the predetermined direction, the integration of the voltage corresponding to the voltage to be measured is started, and when the output signal of the comparator is inverted again in the predetermined direction. , To end the measurement of the second integration time,
The output change amount of the integrator when the voltage according to the voltage to be measured is integrated for the first integration time and the output change amount of the integrator when the set voltage is integrated for the second integration time are represented by an offset of the comparator. The voltage can be matched without being affected by the voltage. As a result, the measured voltage can be accurately A / D converted.

Here, in order to invert the output signal of the comparator in a predetermined direction before starting the integration of the voltage according to the voltage to be measured, the five-phase integration method shown in FIG. As in “State 1” and “State 2”, first, a voltage having a polarity opposite to the set voltage to be integrated at the time of measuring the second integration time with reference to the reference voltage Vref is integrated, and the output voltage Vo of the integrator is integrated. Is separated from the comparison voltage VC of the comparator, and then the set voltage is integrated, and the output voltage Vo of the integrator is returned to the comparison voltage VC. A / D
The time required for the conversion becomes longer.

Therefore, in particular, in the A / D converter according to the fourth aspect, the initial setting means includes a resistor and a switch element connected in series, and is connected in parallel with an integrating capacitor forming an integrator. Provided voltage setting circuit.
Then, the initial setting means applies the predetermined voltage to the integrating resistor of the integrator in a state where the switch element of the voltage setting circuit is short-circuited, thereby changing the output voltage Vo of the integrator to the output signal of the comparator. Is held at a voltage near the voltage that is inverted in the predetermined direction, and then, while opening the switch element, applying the set voltage to an integrating resistor, and integrating the set voltage to an integrator. , The output voltage Vo of the integrator is changed so that the output signal of the comparator is inverted in the predetermined direction.

In other words, in the A / D converter according to the fourth aspect, the output voltage Vo of the integrator is held at a voltage before the output signal of the comparator is inverted in the predetermined direction, and the output voltage Vo is output to the integrator. By integrating the set voltage and changing the output voltage Vo from the held voltage, the output signal of the comparator is inverted.

Therefore, according to the A / D converter of the fourth aspect, unlike the conventional five-phase integration method, there is no need to provide a period for sequentially integrating two types of voltages, and the A / D converter of the voltage to be measured is not required.
After the start of the / D conversion operation, the output signal of the comparator can be inverted in a predetermined direction earlier, and as a result, the time required for A / D conversion of the measured voltage can be reduced.

On the other hand, the A / D converter according to the fifth aspect is based on the same configuration as that of the A / D converter according to the fourth aspect, but forms an integrator. Reference voltage Vref applied to the non-inverting input terminal of the operational amplifier
Is set to a voltage between a preset set voltage (that is, a voltage to be integrated at the time of measuring the second integration time) Vα and a second set voltage Vβ different from the set voltage Vα.

In the A / D converter according to the fifth aspect, the output signal of the comparator is inverted in a predetermined direction by the operation of the initial setting means, as in the A / D converter according to the fourth aspect. Then, during the first integration time from that point, the integrator integrates the voltage corresponding to the voltage to be measured, and the output voltage V
When the first integration time elapses, the integrator integrates the set voltage Vα, returns the output voltage Vo to the comparator comparison voltage VC, and integrates the set voltage Vα. Is measured from the start to the time when the output signal of the comparator is inverted again in the predetermined direction as a second integration time.

Here, as a voltage corresponding to the voltage to be measured,
When the configuration is such that the measured voltage itself is integrated, as described in the section of “Prior Art”, the measured voltage is equal to the reference voltage V.
When the voltage is on the set voltage Vα side of ref, that is,
When the measured voltage to be integrated and the set voltage Vα have the same polarity when viewed from the reference voltage Vref of the integrator, the integrators are integrated when the measured voltage is integrated and when the set voltage Vα is integrated. Change direction of the output voltage Vo becomes the same, and A / D conversion cannot be performed.

In particular, in the A / D converter according to the fifth aspect, the reference voltage Vref of the integrator is set to the center voltage ((Vα + Vβ) / (Vα + Vβ) / Vd) between the set voltage Vα and the second set voltage Vβ.
2) Alternatively, the voltage is set to a voltage between the center voltage and the set voltage Vα, and the integration control means sets the voltage during the first integration time.
A voltage obtained by averaging the measured voltage and the second set voltage Vβ is integrated by an integrator as a voltage corresponding to the measured voltage.

According to the A / D converter of the fifth aspect, even if the voltage to be measured is a voltage on the set voltage Vα side with respect to the reference voltage Vref, the voltage is determined as a voltage corresponding to the voltage to be measured. The voltage integrated during one integration time, that is, the voltage obtained by averaging the measured voltage and the second set voltage Vβ is not the set voltage Vα side when viewed from the reference voltage Vref, but the second set voltage Vβ Is the value of Therefore, regardless of whether the measured voltage is any voltage between the set voltage Vα and the second set voltage Vβ, the case where the voltage corresponding to the measured voltage is integrated and the case where the set voltage Vα is integrated are as follows. The output voltage Vo of the integrator can be changed in the opposite direction. As a result, the voltage range of the voltage to be measured in which A / D conversion can be performed is not restricted.

According to the A / D converter according to the fifth aspect, it is not necessary to provide an additional integration period as in “state 3” of the five-phase integration method shown in FIG. Without lengthening the A / D conversion time of the measured voltage,
Thus, the voltage range of the voltage to be measured in which the A / D conversion can be performed can be expanded.

Next, in the A / D converter according to the sixth aspect, in the A / D converter according to the fifth aspect, the integrator has one terminal connected to an inverting input terminal of the operational amplifier. It has two integrating resistors, and the integrating control means includes:
During the first integration time, the measured voltage and the second set voltage Vβ are added to the integrator by applying the measured voltage and the second set voltage Vβ to each of the two integrating resistors. The averaged voltage is integrated, and when the first integration time elapses,
By applying the set voltage Vα to each of the two integration resistors, the integrator integrates the set voltage Vα.

According to the A / D converter of the sixth aspect, there is no need to provide a special buffer or the like for averaging the measured voltage and the second set voltage Vβ. The effect of the A / D converter described in (1) can be obtained. Next, in the A / D converter according to the seventh aspect, in the A / D converter according to the fifth aspect, the voltage according to the voltage to be measured (that is, the voltage to be measured and the second set voltage Vβ, The initial setting means for inverting the output signal of the comparator in a predetermined direction before starting the integration of (the voltage obtained by adding and averaging) comprises the same initial setting means as the A / D converter according to the fourth aspect.

Therefore, according to the A / D converter of the seventh aspect, the effects of the A / D converter of the fifth aspect are as follows:
The effect of the A / D converter according to claim 4 can be obtained in combination, and the time required for A / D conversion of the measured voltage can be further reduced.

Next, in the A / D converter according to the eighth aspect, in the A / D converter according to the sixth aspect, the initial setting means is the same as the A / D converter according to the fourth aspect. A voltage setting circuit formed by connecting a resistor and a switch element in series and connected in parallel with an integrating capacitor forming an integrator. Then, the initial setting means, in a state where the switch element of the voltage setting circuit is short-circuited,
By applying the second set voltage Vβ to one of the two integrating resistors, the output voltage Vo of the integrator is changed to a voltage at which the output signal of the comparator is inverted in the predetermined direction. , And thereafter, the switch element is opened, and the set voltage Vα is applied to each of the two integrating resistors to integrate the set voltage Vα into the integrator. The output voltage Vo of the integrator is changed so that the output signal of the comparator is inverted in the predetermined direction.

That is, in the A / D converter according to the present invention, the integrating resistor is used to hold the output voltage Vo of the integrator at a voltage before the output signal of the comparator is inverted in the predetermined direction. As the predetermined voltage applied to the second set voltage V
β is used. According to the A / D converter of the eighth aspect, the effect of the A / D converter of the sixth aspect and the effect of the A / D converter of the fourth aspect are obtained. , Can be obtained without additionally providing a special voltage.

On the other hand, in the A / D converter according to the ninth aspect, in the A / D converter according to any one of the fourth to eighth aspects, the integration control means includes the first integration time and the second integration time. 2. As the time measuring means for measuring the integration time, an encoding means exactly the same as the encoding means provided in the A / D converter according to claim 1 is provided.

Therefore, according to the A / D converter of the ninth aspect, in each of the A / D converters of the fourth to eighth aspects, the A / D converter of the first aspect is provided. Similar to the device, the measurement resolution of the integration time can be increased and the accuracy of the A / D conversion can be increased without setting a long integration time.
As a result, the time required for A / D conversion of the measured voltage can be further reduced.

Next, in the A / D converter according to the tenth aspect, in the A / D converter according to the ninth aspect, the encoding means is provided with the A / D converter according to the second aspect. And a coding circuit provided with a pulse circulating circuit, a counter, a latch circuit, and a pulse detection circuit, just like the coding means.

When the integrator starts integration of the voltage corresponding to the voltage to be measured, the integration control means outputs the first signal to the inverting circuit for starting to start the pulse circulating operation of the pulse circulating circuit. Thereafter, when a predetermined bit of the counter changes, the first integration time is passed and the integrator starts to integrate the set voltage. After that, when the output signal of the comparator is inverted in the predetermined direction, the latch circuit and It is configured to output the second signal to the pulse detection circuit.

That is, in the A / D converter according to the tenth aspect, the integration control means receives the signal from the integrator during a period from the start of the pulse circulating operation of the pulse circulating circuit until the predetermined bit of the counter changes. A voltage corresponding to the measured voltage is integrated, and the integration time (ie, the first integration time)
Is measured by a pulse circulation circuit and a counter of the encoding means. When the predetermined bit of the counter changes, the integration control means causes the integrator to integrate the set voltage, and then, when the output signal of the comparator is inverted, outputs the second signal to the latch circuit and the pulse detection circuit. The encoding means outputs a binary digital signal representing a time obtained by adding the first integration time and the second integration time.

The A according to claim 10
According to the A / D converter, in each of the A / D converters according to the fourth to eighth aspects, the same effect as the A / D converter according to the second aspect, that is, with a simple configuration. A of measured voltage
The effect that the / D conversion can be performed with high accuracy in a short time can be obtained.

[0070]

Embodiments of the present invention will be described below with reference to the drawings. It is needless to say that the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.

[First Embodiment] FIG. 1 shows the configuration of an integrating A / D converter according to a first embodiment for outputting a binary digital signal corresponding to a voltage Vin to be externally input. It is a block diagram. The A / D converter according to the present embodiment measures the voltage to be measured within the range from the ground potential VG (= 0 V) as the set voltage to the power supply voltage VDD (5 V in the present embodiment) as the second set voltage. It is configured on the assumption that the voltage Vin changes.

As shown in FIG. 1, the A / D converter of the first embodiment includes an operational amplifier (op-amp) 11 and an operational amplifier 1.
1 and two integrating resistors 13 having one terminal connected to the inverting input terminal of the operational amplifier 11 respectively.
a and 13b, a comparator 14 in which the output voltage of the integrator (ie, the output voltage of the operational amplifier 11) Vo is input to the non-inverting input terminal, and an operational amplifier 11 of the integrating resistor 13a. A switching element 1 for switching and applying a ground potential VG and a power supply voltage VDD to the opposite terminal.
6a, a switch element 16b for switching and applying a measured voltage Vin and a ground potential VG to a terminal of the integrating resistor 13b opposite to the operational amplifier 11, and a resistor 17b.
And a switch element 18 connected in series, and a voltage setting circuit connected in parallel with the integrating capacitor 12 forming the integrator.

The center voltage (= VDD / 2) between the ground potential VG and the power supply voltage VDD is applied to the non-inverting input terminal of the operational amplifier 11 as the reference voltage Vref. Is also applied to the inverting input terminal of the comparator 14 as a comparison voltage for the comparator 14 to compare the magnitude with the output voltage Vo of the integrator.

Further, the A / D converter according to the first embodiment includes a control circuit 20 for controlling the switch elements 16a, 16b and 18 by switching signals φ1 to φ4, and a first signal PA from the control circuit 20. Is output and the second signal P
A pulse phase difference encoding circuit (hereinafter referred to as TAD) 22 for binary encoding the time until B is output and outputting a binary digital signal representing the time, and the switching signal φ1
When φ2 out of φ4 rises from the low level to the high level, the output from the TAD 22 at that time is 2
And a register 24 for latching and outputting the binary digital signal.

Here, when the switching signal φ1 or φ3 from the control circuit 20 is at a high level, the switch element 16a switches its contact to the power supply voltage VDD side and applies the power supply voltage VDD to the integrating resistor 13a. When the switching signal φ2 or φ4 from the control circuit 20 is at a high level,
The contact is switched to the ground potential VG and the integrating resistor 13
a is applied with the ground potential VG. The switch element 16
b, when the switching signal φ3 from the control circuit 20 is at a high level, the contact switches to the measured voltage Vin side to apply the measured voltage Vin to the integrating resistor 13b,
When the switching signal .phi.2 or .phi.4 is at a high level, the contact is switched to the ground potential VG side to apply the ground potential VG to the integrating resistor 13b. Further, the switch element 18 is short-circuited when the switching signal φ1 from the control circuit 20 is at a high level, and connects the resistor 17 in parallel with the integrating capacitor 12.

Therefore, when the control circuit 20 outputs the switching signal φ1 at a high level as described later, the switch element 18 is short-circuited, the contact of the switch element 16a is switched to the power supply voltage VDD side, and the integrator The reference voltage V applied to the non-inverting input terminal
ref (= VDD / 2) so that the output voltage Vo
To change the output voltage Vo of the integrator at this time.
Is a voltage VS determined by the resistance value R of the integrating resistor 13a and the resistance value r of the resistor 17, as shown in the following Expression 7. Hereinafter, this voltage is referred to as an initial voltage VS.

[0077]

VS = (VDD / 2) × (1−r / R) (7) As can be seen from Equation 7, the initial voltage VS is
Although it is lower than the reference voltage Vref (= VDD / 2) (in other words, it is closer to the ground potential VG), in the first embodiment, the initial voltage VS is set to be slightly lower than the reference voltage Vref. , The resistance value r of the resistor 17 to the integrating resistor 1
It is set to a value sufficiently smaller than the resistance value R of 3a.
In the first embodiment, two integrating resistors 13 are used.
The resistance values of a and 13b are set to the same value.

Next, TAD (pulse phase difference encoding circuit)
22 will be described. The configuration and operation of this type of pulse phase difference encoding circuit are described in Japanese Patent Laid-Open Publication No.
Since it is described in detail in Japanese Patent Application Laid-Open No. 220814, Japanese Patent Application Laid-Open No. 6-216721, and the like, it will be briefly described here with reference to FIG.

As shown in FIG. 2, the TAD 22 is formed by sequentially connecting a two-input NAND gate NAND as a start-up inverting circuit and a plurality of inverters IV in a ring shape, and the input which is not connected to the inverter IV of the NAND gate NAND. A pulse circulation circuit 23 to which a first signal PA from the control circuit 20 is input is provided at a terminal. When the first signal PA from the control circuit 20 is at a low level, the pulse circulating circuit 23 makes the output of the NAND gate NAND a high level and outputs the output from the inverter IV connected immediately before the NAND gate NAND to the NAND gate NAND. Is also at a high level, and is configured to be stable in this state. When the first signal PA changes from the low level to the high level, the NAND gate NAND starts the inversion operation of the input signal, and thereafter, the pulse signal is sequentially inverted by each of the inversion circuits (that is, the NAND gate NAND and the inverter IV) to circulate. .

Further, the TAD 22 counts the rising edge (or the falling edge) of the pulse signal output from any of the inverting circuits constituting the pulse circulating circuit 23, and thereby the pulse signal in the pulse circulating circuit 23 is counted. Counts how many times the orbit has circulated, and represents the count number.
26 that outputs a binary digital signal (10-bit data in this embodiment), and a second signal P from the control circuit 20.
When B changes from a low level to a high level (rising timing of the second signal PB), 10
A latch circuit 28 for latching and outputting bit data;
Upon receiving output signals of a plurality of predetermined inverting circuits among the inverting circuits constituting the pulse circulating circuit 23, when the second signal PB changes from a low level to a high level, the pulse signal is A pulse selector 30 for detecting whether or not the pulse has reached the inverting circuit, and counting from the NAND gate NAND of the pulse circulating circuit 23 based on the signal from the pulse selector 30,
(2) corresponding to the number of inverting circuits from the NAND gate NAND to the inverting circuit in which the pulse signal is detected to indicate in which stage the inverting circuit detected is located. And an encoder 32 that outputs a binary digital signal (in this embodiment, 5-bit data).

In the TAD 22, the pulse circulating circuit 23
The first signal PA input to the NAND gate NAND is changed from low level to high level to start the pulse circulating operation of the pulse circulating circuit 23, and then the second signal PB input to the latch circuit 28 and the pulse selector 30 is set to low level. From the first signal PA to the high level until the second signal PB rises, the counter 26 and the latch determine how many times the pulse signal has circulated on the pulse circulating circuit 23. When the pulse signal reaches the inverting circuit in the pulse circulating circuit 23 when the second signal PB rises, the pulse selector 30 and the encoder 32 detect the pulse signal. . And the latch circuit 2
The 15-bit data with the 10-bit data from 8 (that is, the count value of the counter 26) as the upper bit and the 5-bit data from the encoder 32 with the lower bit becomes the second signal after the first signal PA becomes high level. The pulse signal represents a value corresponding to the total number of inverting circuits in which the pulse signal has propagated (that is, has performed an inverting operation) before PB rises,
Further, the phase difference (that is, the input time difference) between the first signal PA and the second signal PB is output as a binary digital signal obtained by encoding the inversion operation time of each inversion circuit or a time several times as long as the inversion operation time. You.

Next, as shown in FIG. 3, the control circuit 20
Three D-type flip-flops (hereinafter, simply referred to as flip-flops) F forming a three-stage shift register
1, F2, and F3, and a clock (C) terminal commonly connected to the clock terminals of the flip-flops F1 to F3, and a data (D) terminal connected to a third-stage flip-flop F3 forming the shift register. Q bar output (Q
B) a flip-flop F4 connected to the data terminal of the first-stage flip-flop F1 forming the shift register, and an external clock CLK and a Q-bar of the flip-flop F4. The AND gate 34 to which the output is input, the AND gate 36 to which the output signal CMP of the comparator 14 and the Q output of the flip-flop F1 are input, the most significant bit MSB of the counter 26 constituting the TAD 22 and the flip-flop F2
And the gate 38 to which the Q output of the comparator 1 is input and the comparator 1
And an AND gate 40 to which the output signal CMP and the Q output of the flip-flop F3 are input, and outputs the logical sum signal of the outputs of the four AND gates 34 to 40 to the clock terminals of the flip-flops F1 to F4. A 4-input OR gate 42 and an external reset signal RST are inverted to reset the flip-flops F1 to F4 (R
B) an inverter 44 for outputting to a terminal.

Further, the control circuit 20 controls the flip-flop F5 in which the output of the AND gate 36 is input to the clock terminal and the power supply voltage VDD is applied to the data terminal, the output of the AND gate 40, and an external reset signal RST. NOR gate 46, which outputs a NOR signal to the reset terminal of flip-flop F5,
An OR gate 48 for outputting a logical sum signal of the Q output of 5 and the most significant bit MSB of the counter 26 is provided.

Then, the control circuit 2 thus configured
0, the Q bar output of the flip-flop F4 is output as the switching signal φ1 to the switch elements 16a and 18;
The Q output of the flip-flop F1 is connected to the switch element 16a
And 16b, and outputs the Q output of flip-flop F2 to switch elements 16a and 16b.
To the flip-flop F3
Is output as a switching signal φ4 to the switching elements 16a and 16b. Further, the output of the OR gate 48 is supplied to the pulse circuit 23 constituting the TAD 22 by the first circuit.
The signal Q is output as the signal PA, and the Q bar output of the flip-flop F5 is output as the second signal PB to the latch circuit 28 and the pulse selector 30 constituting the TAD 22.

Next, the operation of the A / D converter according to the first embodiment configured as described above will be described with reference to a time chart shown in FIG. First, in the initial state where the external reset signal RST is at a high level, the control circuit 20
Are reset, and only the switching signal φ1 of the switching signals φ1 to φ4 attains a high level. Therefore, as described above, the switching element 18
Is short-circuited, and the contact point of the switch element 16a switches to the power supply voltage VDD side, so that the output voltage Vo of the integrator becomes
It is kept at the initial voltage VS slightly lower than the reference voltage Vref (= VDD / 2) (see equation 7).

Then, the reset signal RST changes from the high level to the low level, and the flip-flops F1 to F
5 is released, and thereafter, as shown at time t1 in FIG. 4, when the external clock CLK rises, the control circuit 20 causes the clock terminals of the flip-flops F1 to F4 via the AND gate 34 and the OR gate 42 in the control circuit 20. , The switching signals φ1 to φ1
Of φ4, only the switching signal φ2 is at the high level.

Then, the switch element 18 is opened, the contact of the switch element 16a and the contact of the switch element 16b are both switched to the ground potential VG, and the integrator starts to integrate the ground potential VG. Then, the output voltage Vo of the integrator rises from the initial voltage VS with the integration of the ground potential VG. At the timing when the switching signal φ2 changes to the high level, the register 24 latches and outputs the binary digital signal (15-bit data) output from the TAD 22 at that time.

Thereafter, when the output voltage Vo of the integrator rises and exceeds the comparison voltage of the comparator 14 (that is, the reference voltage Vref), as shown at time t2, the output signal CMP of the comparator 14 changes from the low level to the high level. (Reverse). At time t2, the output voltage Vo of the integrator is actually
At the time when the voltage reaches the sum of the reference voltage Vref and the offset voltage of the comparator 14.

Then, in the control circuit 20, a rising edge is input to the clock terminals of the flip-flops F1 to F4 from the AND gate 36 via the OR gate 42, and only the switching signal φ3 of the switching signals φ1 to φ4 is output. High level. At the same time, a rising edge is input from the AND gate 36 to the clock terminal of the flip-flop F5, and the output of the OR gate 48 is the first signal.
The signal PA changes from the low level to the high level, and the second signal PB, which is the Q-bar output of the flip-flop F5, changes from the high level to the low level.

When the switching signal φ3 goes high as described above, the contact of the switch element 16a switches to the power supply voltage VDD side, and the contact of the switch element 16b switches to the measured voltage Vin side. The integrator starts to integrate a voltage ((Vin + VDD) / 2) obtained by averaging the measured voltage Vin and the power supply voltage VDD. When the first signal PA changes to the high level as described above, the pulse circulating circuit 23 of the TAD 22 starts the circulating operation of the pulse signal. In the following description,
The voltage obtained by averaging the measured voltage Vin and the power supply voltage VDD is simply referred to as an averaging voltage VH.

Here, the above average voltage VH (= (Vin
+ VDD) / 2) is always equal to the reference voltage V if the measured voltage Vin is within the range between the ground potential VG and the power supply voltage VDD.
The voltage ranges from ref (= VDD / 2) to the power supply voltage VDD. Therefore, when the switching signal φ3 becomes high level and the integrator starts to integrate the above average voltage VH, the output voltage Vo of the integrator always drops. When the output voltage Vo of the integrator starts to fall in this way, the output signal CMP of the comparator 14 is inverted from the above-described direction at the time t2, that is, from the high level to the low level.

[0092] Then, after changing the first signal PA is at the high level at time t2, the pulse signal on the pulse circulating circuit 23 circulates only 2 ⁹ times, as shown at time t3, T
At AD22, the most significant bit MSB of the counter 26 changes from "0" (= low level) to "1" (= high level).

Then, in the control circuit 20, a rising edge is input to the clock terminals of the flip-flops F1 to F4 from the AND gate 38 via the OR gate 42, and only the switching signal φ4 among the switching signals φ1 to φ4 is output. High level. Then, when the switching signal φ4 becomes high level, the switching element 1 is switched in the same manner as at the time t2.
6a and the contact of the switch element 16b are both switched to the ground potential VG side, and the integrator starts to integrate the ground potential VG, whereby the output voltage Vo of the integrator becomes
It will rise from time t3.

Then, when the output voltage Vo of the integrator exceeds the comparison voltage of the comparator 14 (that is, the reference voltage Vref), as shown at time t4, the output signal CM of the comparator 14 is output.
P is again inverted from low level to high level. At time t4, the output voltage Vo of the integrator is the same as at time t2.
At the time when the voltage reaches the sum of the reference voltage Vref and the offset voltage of the comparator 14.

Then, in the control circuit 20, a rising edge is input to the clock terminals of the flip-flops F1 to F4 from the AND gate 40 via the OR gate 42, and only the switching signal φ1 of the switching signals φ1 to φ4 is high. Return to level state. At the same time, since a low-level signal is input from the AND gate 40 to the reset terminal of the flip-flop F5 via the NOR gate 46, the flip-flop F5 is reset and the second signal PB which is the Q-bar output thereof is output. Changes from a low level to a high level.

When the second signal PB rises in this manner, the TAD 22 becomes a 15-bit signal representing the time from when the first signal PA goes high at time t2 to when the second signal PB rises at time t4. Will be output. Thereafter, the pulse number of times of circulation of a pulse circulating circuit 23 reaches 2 ¹⁰ times, as shown at time t5, when the most significant bit MSB of the counter 26 becomes "0" (i.e.,
When the counter 26 overflows and all its bits become "0"), the first
The signal PA returns from the high level to the low level, and the pulse circulating operation of the pulse circulating circuit 23 stops.

Then, when the clock CLK from the outside rises again, only the switching signal φ2 goes high, as described above, and the integration of the ground potential VG by the integrator is started. Time t4 described above
, The 15-bit data newly output from the TAD 22 is latched in the register 24. In the first embodiment, immediately after the data of the TAD 22 is latched by the register 24, the stored contents of the counter 26, the latch circuit 28, and the pulse selector 30 are cleared.

Thereafter, the same operation as that after time t1 described above is repeated. In the A / D converter of the present embodiment, the 15-bit data from the TAD 22 latched by the register 24 when the switching signal φ2 changes from the low level to the high level corresponds to the most significant bit MSB of the counter 26. A group of bits lower than the bits, that is, 14-bit data excluding the most significant bit of the 15-bit data latched by the register 24 is output to the outside as a binary digital signal representing the value of the voltage under measurement Vin. .

As described above, in the A / D converter of the first embodiment, first, with the switch element 18 short-circuited,
By applying the power supply voltage VDD to one of the integrating resistors 13a via the switch element 16a, the output voltage Vo of the integrator is changed to the initial voltage near the point where the output signal CMP of the comparator 14 is inverted from low level to high level. VS (i.e., a voltage slightly lower than the reference voltage Vref) (before time t1). Thereafter, the switch element 18 is opened and the two integrating resistors 13a and 13b are connected via the switch elements 16a and 16b. By applying the ground potentials VG, respectively,
By integrating the ground potential VG with the integrator, the output voltage Vo of the integrator is increased so that the output signal CMP of the comparator 14 is inverted from the low level to the high level (from time t1 to time t2).

When the output signal CMP of the comparator 14 is inverted from the low level to the high level (time t2), the first signal PA is set to the high level to start the pulse circulating operation of the pulse circulating circuit 23, and the counter 26 Until the upper bit MSB changes to “1”, the integrator averages the average voltage V obtained by averaging the measured voltage Vin and the power supply voltage VDD.
H is integrated, and the output voltage Vo of the integrator is calculated by the comparator 14.
Is lowered so that the output signal CMP of the counter 26 is inverted from the high level to the low level, and then the most significant bit MSB of the counter 26 changes to “1” (time t3).
The integrator integrates the ground potential VG to increase the output voltage Vo of the integrator so that the output signal CMP of the comparator 14 is inverted again from the low level to the high level. When the CMP is inverted (time t4), the second signal PB to the TAD 22 rises and T
The AD 22 outputs a binary digital signal representing the time from time t2 to time t4.

Here, after the output signal CMP of the comparator 14 is inverted at time t2, the most significant bit M
Until time t3 when SB changes to "1", the output change voltage V of the integrator due to integration of the averaged voltage VH.
a is given by the following equation 8. Further, from time t3 to time t4 when the output signal CMP of the comparator 14 is again inverted, the output change voltage Vb of the integrator due to integration of the ground potential VG is: Equation 9 below is obtained.

In equation 8, "「 _ (0) ^ (Ta) [(V
in + VDD) / 2−VDD / 2] dt ”is the average voltage V
H and the difference between the reference voltage Vref [(Vin + VDD) / 2−VDD
/ 2] by the time Ta, and the time Ta is
As shown in FIG. 4, it corresponds to the time from time t2 to time t3. Similarly, in equation 9, “「 _ (0) ^ (Tb)
[0−VDD / 2] dt ”is the ground potential VG and the reference voltage V
This is a value obtained by integrating the difference [0−VDD / 2] with respect to ref by the time Tb, and the time Tb corresponds to the time from time t3 to time t4 as shown in FIG. In Equations 8 and 9, “C” is the capacitance of the integrating capacitor 12, and “R” is the combined resistance value of the integrating resistors 13 a and 13 b.

[0103]

Va = −∫_ (0) ^ (Ta) [(Vin + VDD) / 2−VDD / 2] dt / CR = −Vin × Ta / (2 × CR) (8)

[0104]

Vb = −∫_ (0) ^ (Tb) [0−VDD / 2] dt / CR = VDD × Tb / (2 × CR) (9) Then, the output signal CMP of the comparator 14 is The integration of the averaged voltage VH is started at the time when the level changes from the low level to the high level. Similarly, when the output signal CMP of the comparator 14 changes from the low level to the high level, the integration of the ground potential VG is terminated. Therefore, the absolute value of the output change voltage Va (that is, the output change amount of the integrator when the averaging voltage VH is integrated by the time Ta) and the absolute value of the output change voltage Vb (that is, ground) (The amount of change in the output of the integrator when the potential VG is integrated for the time Tb), and Va + Vb = 0.
Equation 10 below is established from

[0105]

Vin / VDD = Tb / Ta (10) Accordingly, the value of the measured voltage Vin is calculated as the ratio (Tb / Ta) of the time Tb obtained by integrating the ground potential VG and the time Ta obtained by integrating the average voltage VH. ) Is converted into a numerical value.

Therefore, in the A / D converter according to the first embodiment, since the second signal PB rises at time t4 in FIG. 4, the most significant bit is removed from the 15-bit data output from the TAD 22. The 14-bit data is converted into a binary digital signal (that is, A / D
(A converted binary digital signal).

That is, first, in the A / D converter of this embodiment, the integration is performed from the start of the pulse circulating operation of the pulse circulating circuit 23 until the most significant bit MSB of the counter 26 changes to "1". When the integration of the averaged voltage VH is completed (when the most significant bit MSB of the counter 26 changes to "1"), the latch circuit 2 of the TAD 22 is activated.
Assuming that the second signal PB has been output to the pulse selector 30 and the pulse selector 30, the 15-bit data output from the TAD 22 at that time has the most significant bit “1” and the lower 14 bits.
This is a binary digital signal whose bits are all "0". That is, the binary digital signal representing the integration time Ta of the average voltage VH is 15-bit data in which only the most significant bit is "1".

As described above, the 15-bit data output from the TAD 22 when the second signal PB rises at time t4 in FIG. 4 is obtained by integrating the integration time Ta of the average voltage VH and the integration of the ground potential VG. In this first embodiment, the reference voltage Vref is set to the center voltage (VDD / 2) between the ground potential VG and the power supply voltage VDD. The integration time Tb of the ground potential VG is always shorter than the integration time Ta of the averaging voltage VH.

Therefore, of the 15-bit data representing the time obtained by adding the two integration times Ta and Tb, the data of the lower 14 bits excluding the most significant bit is the integration of the ground potential VG with respect to the integration time Ta of the addition average voltage VH. The ratio of the time Tb, that is, the ratio of the two integration times Tb and Ta (Tb / T
a) will be expressed as it is. Therefore, in the A / D converter of this embodiment, the lower 14 bits of data are output to the outside as a binary digital signal representing the value of the measured voltage Vin. In the first embodiment, the voltage setting circuit including the resistor 17 and the switch element 18, the switch element 16a, and the portion including the AND gate 34 and the flip-flops F1 and F4 in the control circuit 20 are initialized. Parts other than the part corresponding to the initial setting means in the control circuit 20 and the switch elements 16a and 16b correspond to the integration control means. The TAD 22 corresponds to an encoding unit (time measuring unit).

As described in detail above, A /
In the D converter, an averaging voltage VH corresponding to the unknown voltage under measurement Vin and a known ground potential VG set in advance are calculated by:
Based on the ratio of the integration times Ta and Tb when the output change amount of the integrator is integrated to be equal, the measured voltage V
I am trying to convert in to a digital value,
In particular, the integration time (first integration time) T of the averaged voltage VH
a and the integration time (second integration time) Tb of the ground potential VG are measured by the TAD 22 capable of binary encoding the time with the inversion operation time of the inversion circuit or a time several times as long as the inversion operation time. .

Therefore, according to the A / D converter of the first embodiment, the integration time can be measured with a very small time resolution, and the integration time is set long as in the conventional A / D converter. Without this, the accuracy of the A / D conversion can be increased, and as a result, the A / D conversion of the measured voltage Vin can be performed with high accuracy and in a short time. Further, since it is not necessary to set the integration time longer, the capacitance of the integrating capacitor 12 constituting the integrator and the resistance of the integrating resistors 13a and 13b can be reduced, and the A / D conversion can be performed. When the device is integrated on one semiconductor chip, the chip size can be reduced.

In the A / D converter according to the first embodiment,
After starting the pulse circulating operation of the pulse circulating circuit 23 in the TAD 22, the most significant bit MSB of the counter 26 is
Until the voltage changes to “1”, the measured voltage Vin is applied to the integrator.
And the power supply voltage VDD are integrated, and at the timing when the most significant bit MSB of the counter 26 changes to "1", the voltage to be integrated by the integrator is switched to the ground potential VG. In the binary digital data output from the TAD 22 at the time when the integration of the ground potential VG is completed, a bit group lower than the bit corresponding to the most significant bit MSB of the counter 26 is converted into a binary group representing the value of the measured voltage Vin. They are output to the outside as digital signals. Therefore, the effect that the A / D conversion of the measured voltage Vin can be performed with high accuracy and in a short time can be obtained with a simple configuration.

Further, in the A / D converter of the first embodiment, during the period from time t2 to time t3 in FIG.
Since the measured voltage Vin is not integrated as it is, but the integrated average voltage VH obtained by averaging the measured voltage Vin and the power supply voltage VDD is integrated, the measured voltage Vin is more ground potential than the reference voltage Vref. VG side voltage (that is,
Even if the voltage is lower than the reference voltage Vref), the output voltage Vo of the integrator can be reduced during the period from time t2 to time t3 in FIG.

Therefore, according to the A / D converter of the first embodiment, even if the measured voltage Vin is any voltage between the ground potential VG and the power supply voltage VDD, the time t2 in FIG. The output voltage Vo of the integrator can be changed in the opposite direction between the period until time t3 and the period from time t3 to time t4 in FIG. As a result, it is not necessary to provide an additional integration period such as “state 3” of the five-phase integration method shown in FIG. A / D conversion time of the measured voltage Vin can be shortened.

Further, in the A / D converter according to the first embodiment, a voltage setting circuit in which a resistor 17 and a switch element 18 are connected in series is provided in parallel with the integrating capacitor 12.
With the switch element 18 short-circuited, the power supply voltage VDD is connected to one of the integrating resistors 13a via the switch element 16a.
Is applied, the output voltage Vo of the integrator is held at the initial voltage VS near the point where the output signal CMP of the comparator 14 is inverted from the low level to the high level, and then the switch element 18 is opened, Two integrating resistors 13a, 1 are connected via switch elements 16a, 16b.
3b, the ground signal VG is applied, and the integrator integrates the ground voltage VG.
The output voltage Vo of the integrator is increased so that MP is inverted from low level to high level.

Therefore, according to the A / D converter of the first embodiment, the “state 1” of the five-phase integration method shown in FIG.
In addition, there is no need to provide a period for sequentially integrating two types of voltages as in “state 2”, and the output signal CMP of the comparator 14 is inverted earlier to perform a substantial A / D conversion operation (time t2 in FIG. 4). The subsequent operation) can be started, and as a result, the time required for A / D conversion of the measured voltage Vin can be reduced.

In the first embodiment, when the most significant bit MSB of the counter 26 changes to "1",
Although the voltage to be integrated by the integrator is switched from the average voltage VH to the ground potential VG, the integration of the ground potential VG is performed at a timing when a predetermined bit lower than the most significant bit MSB of the counter 26 changes to "1". In this case, the measurement resolution of the integration time and the total time required for A / D conversion can be changed.

In this case, when the second signal PB rises at time t4 in FIG. 4, the binary digital signal output from the TAD 22 has a lower order than the bit corresponding to the predetermined bit of the counter 26. May be output to the outside as a binary digital signal representing the value of the measured voltage Vin.

On the other hand, in the TAD 22 of the above embodiment, the counter 26 outputs 10-bit data, and the encoder 32 outputs 5-bit data. However, the number of such bits may be changed as necessary. can do. [Second Embodiment] By the way, the A / D of the first embodiment described above.
In the converter, the integrator includes two integrating resistors 13a and 13
b, the power supply voltage VDD is applied to one of the integrating resistors 13a via the switch element 16a, and the voltage to be measured Vin is applied to the other integrating resistor 13b via the switch element 16b. As a result, the measured voltage Vin
Average voltage VH (=
(Vin + VDD) / 2) is equivalently integrated, but may be configured like the A / D converter of the second embodiment shown in FIG. In FIG. 5, the same members as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 5, in the A / D converter according to the second embodiment, the non-inverting input terminal is different from the A / D converter according to the first embodiment in that the switching elements of the resistors 13a and 13b are used. 1
An operational amplifier 50 connected to a terminal on the opposite side of 6a and 16b and having an output terminal and an inverting input terminal connected to each other;
A resistor 5 connected between the output terminal of the operational amplifier 50 and the inverting input terminal of the operational amplifier 11 forming an integrator
2 is additionally provided. Other configurations and operations are exactly the same as those in the first embodiment.

That is, in the A / D converter according to the second embodiment, the integrator includes the operational amplifier 11, the integrating capacitor 12, and the additional resistor 52. When the switching signal φ3 from the control circuit 20 goes high, the integrating resistors 13a and 13
b, the switch elements 16a and 16b, and the additional operational amplifier 50, the voltage under test Vin and the power supply voltage VDD.
Are added and averaged to generate an averaged voltage VH, and the generated averaged voltage VH is applied to the resistor 52 of the integrator to be integrated.

Although the A / D converter of the second embodiment is disadvantageous in that an operational amplifier 50 and a resistor 52 must be added, the A / D converter of the first embodiment is disadvantageous. It is possible to obtain exactly the same effect as the container. Third Embodiment On the other hand, in the A / D converter of the first embodiment, the ground potential VG is used as a known set voltage to be integrated during a period from time t3 to time t4 in FIG. Therefore, during the period from time t2 to time t3 in FIG. 4, the average voltage VH of the measured voltage Vin and the power supply voltage VDD is integrated to lower the output voltage Vo of the integrator.

On the other hand, A of the third embodiment shown in FIG.
Like a / D converter, the power supply voltage VDD may be integrated as a known set voltage. That is, the third
The A / D converter of the embodiment is different from the A / D converter of the first embodiment in the following three points (a) to (c). Other configurations and operations are exactly the same as those in the first embodiment.

(A) The switch element 16a is connected to the control circuit 2
When the switching signal φ1 or φ3 from 0 is at the high level, the contact is switched to the ground potential VG side to apply the ground potential VG to the integrating resistor 13a, and the switching signal φ2 or φ4 from the control circuit 20 is output. When the level is high, the contact switches to the power supply voltage VDD side and the integrating resistor 13a
To the power supply voltage VDD.

(B) The switch element 16b is connected to the control circuit 2
When the switching signal φ2 or φ4 from 0 is at a high level, the contact switches to the power supply voltage VDD side to apply the power supply voltage VDD to the integrating resistor 13b. (C) The input terminal of the comparator 14 is reversed, the output voltage Vo of the integrator is input to the inverting input terminal, and the reference voltage Vref as the comparison voltage is input to the non-inverting input terminal.
Is applied.

The A / D of the third embodiment configured as described above
In the converter, as shown before time t1 in FIG. 7, when the control circuit 20 outputs the switching signal φ1 at a high level, the switch element 18 is short-circuited and the contact of the switch element 16a is switched to the ground potential VG. Therefore, the output voltage Vo of the integrator is held at the initial voltage VS 'determined by the resistance value R of the integrating resistor 13a and the resistance value r of the resistor 17, as shown in the following Expression 11. As described in the first embodiment, the resistance value r of the resistor 17 is set to a value sufficiently smaller than the resistance value R of the integrating resistor 13a.
As can be seen from Equation 11, the initial voltage VS 'is equal to the reference voltage Vs.
The value is slightly higher than ref (= VDD / 2).

[0127]

VS '= (VDD / 2) × (1 + r / R) (11) Then, after the reset signal RST changes from the high level to the low level, as shown at time t1 in FIG. When CLK rises and only the switching signal φ2 among the switching signals φ1 to φ4 from the control circuit 20 becomes high level, the switch element 18 is opened and both the contact of the switch element 16a and the contact of the switch element 16b are both connected. Switching to the power supply voltage VDD side, the integrator starts to integrate the power supply voltage VDD, and accordingly, the output voltage Vo of the integrator falls from the initial voltage VS '.

Thereafter, the output voltage Vo of the integrator is changed to the value of the comparator 1
When the voltage falls below the comparison voltage (that is, the reference voltage Vref) of FIG. 4, the output signal CMP of the comparator 14 is output as shown at time t2 in FIG.
Is inverted from a low level to a high level, only the switching signal .phi.3 of the switching signals .phi.1 to .phi.4 from the control circuit 20 becomes a high level, the contact of the switch element 16a switches to the ground potential VG side, and the switch element 16b Switches to the measured voltage Vin side. As a result, the integrator starts to integrate a voltage ((Vin + 0) / 2 = Vin / 2) obtained by adding and averaging the measured voltage Vin and the ground potential VG. Voltage V
o rises. From the time t2, the TAD22
Starts the circulating operation of the pulse signal.

Here, the voltage (Vin / 2) obtained by adding and averaging the measured voltage Vin and the ground potential VG is as follows if the measured voltage Vin is within the range between the ground potential VG and the power supply voltage VDD.
Always from ground potential VG to reference voltage Vref (= VDD / 2)
Voltage. Therefore, if the switching signal φ3 becomes high level and the integrator starts to integrate the voltage (Vin / 2), the output voltage Vo of the integrator always rises. When the output voltage Vo of the integrator starts to rise in this manner, the output signal CMP of the comparator 14 is inverted from the above-described direction at the time t2, that is, from the high level to the low level.

Thereafter, as shown at time t3 in FIG. 7, when the most significant bit MSB of the counter 26 changes to "1" (= high level), the switching signals .phi.
Only the switching signal φ4 of φ4 becomes high level, the contacts of the switch element 16a and the switch element 16b are both switched to the power supply voltage VDD side, and the integrator starts to integrate the power supply voltage VDD. As a result, the output voltage Vo of the integrator drops from the time t3.

Then, when the output voltage Vo of the integrator falls below the comparison voltage of the comparator 14 (that is, the reference voltage Vref), the output signal CMP of the comparator 14 changes from the low level again as shown at time t4 in FIG. Inverts to the high level, and switches among the switching signals φ1 to φ4 from the control circuit 20.
Only 1 returns to the high level state. At the same time, the second signal PB from the control circuit 20 changes from the low level to the high level, and the TAD 22 outputs 15-bit data representing the time from the time t2 to the time t4.

Thereafter, when the external clock CLK rises, only the switching signal φ2 goes high again, and the integration of the power supply voltage VDD by the integrator is started. Are latched in the register 24.

Thereafter, the same operation as that after time t1 is repeated, and the A / D converter of the third embodiment is also latched by the register 24 when the switching signal φ2 changes from low level to high level. In the 15-bit data from the TAD 22, a bit group lower than the bit corresponding to the most significant bit MSB of the counter 26 is output to the outside as a binary digital signal representing the value of the measured voltage Vin.

As described above, in the A / D converter according to the third embodiment, the power supply voltage VDD is used instead of the ground potential VG and the power supply voltage is different from the A / D converter according to the first embodiment. The ground potential VG is used instead of VDD. That is, the power supply voltage VDD is used as the known set voltage for measuring the integration time Tb in FIG.
The ground potential VG is used as the second set voltage to be added and averaged and integrated.

According to the A / D converter of the third embodiment, as shown in FIG. 7, the output voltage Vo of the integrator is in the reverse direction as compared with the case of the first embodiment. And the same effect as the A / D converter of the first embodiment can be obtained.

[Fourth Embodiment] Next, the A / D of the fourth embodiment will be described.
The converter will be described with reference to FIGS. First, FIG. 8 is a configuration diagram illustrating a configuration of the A / D converter according to the fourth embodiment. As shown in FIG. 8, the A / D converter of the fourth embodiment is different from the A / D converter of the first embodiment in that a control circuit 54 for controlling the switch elements 16a, 16b, 18 and the TAD 22 is different from the A / D converter of the first embodiment. 9 is different from the configuration shown in FIG. 9 in that two registers 56 and 58 and a calculator 60 are provided instead of the register 24.

Here, when the second signal PB from the control circuit 54 to the TAD 22 changes from a low level to a high level (rises), the register 56 latches the binary digital signal newly output from the TAD 22 at that timing. I do. Further, the register 58 stores the T
When the second signal PB to AD22 rises, the register 56 latches the binary digital signal already latched at that time. When the switching signal φ2 from the control circuit 54 rises, the computing unit 60 subtracts the value of the binary digital signal latched by the register 58 from the value of the binary digital signal latched by the register 56, Further, the value of the binary digital signal after the subtraction is divided by the value of the binary digital signal latched by the register 58, and the binary digital signal after the division is divided into a binary digital signal representing the measured voltage Vin. Output as a signal.

On the other hand, the control circuit 54 of the fourth embodiment is different from the control circuit of FIG.
As shown in (1), the following four points (d) to (g) are different from the control circuit 20 of the first embodiment. (D) It comprises a flip-flop F6, an exclusive OR gate 62, and a buffer 64 which are reset together with the other flip-flops F1 to F5 when the output of the inverter 44 is at a low level. A pulse output circuit 66 for outputting a one-shot pulse having a time width corresponding to the signal propagation delay time in the buffer 64 from the exclusive OR gate 62 is additionally provided.

(E) A one-shot pulse (the output of the exclusive OR gate 62) from the pulse output circuit 66 is input to one input terminal of the AND gate 38 instead of the most significant bit MSB of the counter 26. ing. (F) The Q output of the flip-flop F5 is
The first signal P to the pulse circuit 23 constituting the AD 22
Output as A.

(G) The Q bar output of the flip-flop F5 and the output of the AND gate 38 are input to the OR gate 48, and the output of the OR gate 48 is supplied to the latch circuit 28 and the pulse selector 30 constituting the TAD 22. 2
Output as signal PB. Next, the operation of the A / D converter of the fourth embodiment configured as described above will be described with reference to FIG.
This will be described with reference to the time chart shown in FIG. In FIG. 10, "FP" indicates the Q output of the flip-flop F6.

As shown in FIG. 10, the A /
Also in the D converter, the control circuit 5 operates until the external reset signal RST changes from the high level to the low level and the external clock CLK first rises.
Out of the switching signals .phi.1 to .phi.4, only the switching signal .phi.1 attains a high level, and the output voltage Vo of the integrator becomes the initial voltage VS of Equation 7 slightly lower than the reference voltage Vref (= VDD / 2). Held, and as shown at time t1, the clock C
When LK rises, of the switching signals φ1 to φ4, only the switching signal φ2 becomes high level, and the integrator starts to integrate the ground potential VG.

When the output voltage Vo of the integrator rises from the initial voltage VS and exceeds the comparison voltage of the comparator 14 (that is, the reference voltage Vref), as shown at time t2, the output signal CMP of the comparator 14 is output. Is inverted from the low level to the high level, and accordingly, in the control circuit 54, only the switching signal φ3 of the switching signals φ1 to φ4 becomes the high level. At the same time, a rising edge is input from the AND gate 36 to the clock terminal of the flip-flop F5, and the first signal PA, which is the Q output of the flip-flop F5, changes from low level to high level. The Q bar output changes from the high level to the low level, and the second signal PB output from the OR gate 48 changes from the high level to the low level.

When the switching signal φ3 goes high as described above, the switching of the switch elements 16a and 16b causes the integrator to operate the voltage under test Vin and the power supply voltage VDD.
Is started, and when the first signal PA changes to the high level as described above, TAD2
The second pulse circulating circuit 23 starts the circulating operation of the pulse signal.

That is, the operation from the initial state to the time t2 when the switching signal φ3 becomes high level is the same as that of the first embodiment.
It is the same as the D converter. At time t2, the integrator starts to integrate the averaged voltage VH and the pulse circulating circuit 23
Starts the circulating operation of the pulse signal, and as shown at time t3, when the external clock CLK rises again,
In the control circuit 54, a one-shot pulse is output from the pulse output circuit 66. The one-shot pulse is input from the AND gate 38 to the clock terminal of the flip-flops F1 to F4 via the OR gate 42.
Only the high level. In addition, the one-shot pulse is transmitted from the AND gate 38 through the OR gate 48.
Latch circuit 28 and pulse selector 30 of TAD 22
Is output as a high-level second signal PB.

Then, as in the case of the time t1, the integrator starts to integrate the ground potential VG, and the output voltage Vo of the integrator rises from the time t3. As described above, when the one-shot pulse from the pulse output circuit 66 is output as the second signal PB, TAD
Reference numeral 22 denotes 15-bit data representing the time from when the first signal PA goes high at time t2 to when the second signal PB rises at time t3, that is, 15-bit data representing the integration time Ta of the averaging voltage VH. Then, the register 56 latches the 15-bit data. At this time, the register 58 latches the 15-bit data output from the register 56 until then.

Thereafter, when the output voltage Vo of the integrator exceeds the comparison voltage of the comparator 14 (that is, the reference voltage Vref), as shown at time t4, the output signal CM of the comparator 14 is output.
P is again inverted from low level to high level. Then, in the control circuit 54, a rising edge is input from the AND gate 40 to the clock terminals of the flip-flops F1 to F4 via the OR gate 42, and the switching signals φ1 to
Only the switching signal φ1 of φ4 returns to the high level. At the same time, since a low-level signal is input from the AND gate 40 to the reset terminal of the flip-flop F5 via the NOR gate 46, the flip-flop F5 is reset, and the first signal PA as its Q output is output. From the high level to the low level, the pulse circulating operation in the pulse circulating circuit 23 stops, and the Q bar output of the flip-flop F5 changes from the low level to the high level, and the second signal PB changes from the low level to the high level. I do.

As described above, when the second signal PB rises at the time t4, the TAD 22 becomes a 15-bit signal representing the time from when the first signal PA goes high at the time t2 until the second signal PB rises at the time t4. The data, ie, the integration time Ta of the averaging voltage VH and the integration time T of the ground potential VG
Then, 15-bit data representing the time Tc (= Ta + Tb) obtained by adding b is output, and the register 56 latches the 15-bit data. Further, at this time, the register 58 determines that the register 56 has latched at the time t3.
The bit data, that is, 15-bit data representing the integration time Ta of the averaging voltage VH is latched.

After that, when the external clock CLK rises again, the switching signal φ2 out of the switching signals φ1 to φ4
Is at a high level, and the integration of the ground potential VG by the integrator is started. When the switching signal φ2 rises to the high level, the computing unit 60 determines that the time Tc (= Tc) that the register 56 has latched at the time t4.
a + Tb) from the register 58
Is the integration time T of the averaged voltage VH latched at time t4.
a is subtracted, and the 15-bit data after the subtraction (that is, the integration time T of the ground potential VG) is subtracted.
b) is divided by the 15-bit data representing the integration time Ta latched by the register 58,
The binary digital signal after the division is converted into a binary digital signal representing the ratio (Tb / Ta) of the integration time Tb of the ground potential VG and the integration time Ta of the averaged voltage VH, that is, the binary digital signal representing the measured voltage Vin. Output as a binary digital signal.

In the fourth embodiment, when the arithmetic unit 60 performs the above operation and outputs a binary digital signal representing the measured voltage Vin, immediately after that, the counter 26 and the latch circuit 2
8, and the stored contents of the pulse selector 30 are cleared. Then, thereafter, the above-described time t1
The same operation as above is repeated.

As described above, in the A / D converter according to the fourth embodiment, as in the first embodiment, at the timing when the most significant bit MSB of the counter 26 in the TAD 22 changes to "1", the integrator is changed. To the average voltage VH
Instead of switching to the ground potential VG, the voltage to be integrated by the integrator is switched in synchronization with an external clock CLK (time t3 in FIG. 10).

In the A / D converter of the fourth embodiment, the averaging voltage V corresponding to the unknown voltage to be measured Vin is also obtained.
The measured voltage Vin is converted into a digital value on the basis of the ratio between the integration times Ta and Tb when H and a predetermined known ground potential VG are integrated so that the output change amount of the integrator becomes equal. Although the conversion is performed, the integration time Ta of the addition average voltage VH and the integration time Tb of the ground potential VG are determined.
Are measured by the TAD 22.

Therefore, according to the A / D converter of the fourth embodiment, the accuracy of A / D conversion can be improved without setting a long integration time unlike the conventional A / D converter. A / D conversion of the measured voltage Vin can be performed with high accuracy and in a short time. Further, since it is not necessary to set the integration time longer, the capacitance of the integration capacitor 12 and the resistance values of the integration resistors 13a and 13b can be reduced, and the A / D converter can be used as one semiconductor. The chip size when integrated on a chip can be reduced.

Also in the A / D converter of the fourth embodiment, during the period from time t2 to time t3 in FIG. 10, the average voltage VH obtained by averaging the measured voltage Vin and the power supply voltage VDD is integrated. Therefore, even if the measured voltage Vin is a voltage closer to the ground potential VG than the reference voltage Vref, the output voltage Vo of the integrator is maintained during that period.
As a result, there is no need to provide an additional integration period as in “State 3” of the five-phase integration method shown in FIG. The voltage range can be expanded.

Further, in the A / D converter of the fourth embodiment, a voltage setting circuit in which a resistor 17 and a switch element 18 are connected in series is provided in parallel with the integrating capacitor 12.
With the switch element 18 short-circuited, the power supply voltage VDD is connected to one of the integrating resistors 13a via the switch element 16a.
, The output voltage Vo of the integrator is maintained at the initial voltage VS slightly lower than the reference voltage Vref, and then the integrator integrates the ground potential VG to invert the output signal CMP of the comparator 14. Like that.

Therefore, the A / D converter according to the fourth embodiment also sequentially applies two types of voltages as in “state 1” and “state 2” of the five-phase integration method shown in FIG. There is no need to provide a period for integration, and the A / D conversion time of the measured voltage Vin can be reduced. Fifth Embodiment Next, an A / D converter according to a fifth embodiment will be described with reference to FIGS.

FIG. 11 is a configuration diagram showing the configuration of the A / D converter according to the fifth embodiment. As shown in FIG. 11, the A / D converter of the fifth embodiment differs from the A / D converter of the fourth embodiment in that two comparators 14a, 14a are used instead of the comparator 14.
4b, and the output signal CM of one comparator 14a
P1 is output as the first signal PA to the pulse circulating circuit 23 forming the TAD 22, and the output signal CMP2 of the other comparator 14b is output from the latch circuit 2 forming the TAD 22.
8 and the second signal PB to the pulse selector 30 and the point of being output as a latch signal to the registers 56 and 58;
A control circuit 68 for controlling the switch elements 16a, 16b, 18 is configured as shown in FIG. 12 and includes an arithmetic unit 70 that performs an operation slightly different from the arithmetic unit 60 instead of the arithmetic unit 60. Is different.

Here, the first comparison voltage V1 slightly higher than the initial voltage VS shown in Equation 7 is applied to the inverting input terminal of the comparator 14a, and the inverting input terminal of the comparator 14b is A second comparison voltage V2 higher than the first comparison voltage V1 and lower than the power supply voltage VDD (= 5V) is applied.

When the switching signal φ2 from the control circuit 68 rises, the arithmetic unit 70 calculates the value of the binary digital signal latched by the register 58 from the value of the binary digital signal latched by the register 56. Further, the value of the binary digital signal after the subtraction is divided by the value of the binary digital signal latched by the register 56, and the binary digital signal after the division represents the measured voltage Vin. Output as a binary digital signal.

Further, in the A / D converter of the fifth embodiment, when the switching signal φ1 from the control circuit 68 is at a high level, the contact of the switch element 16a switches to the power supply voltage VDD side. When the power supply voltage VDD is applied to the integrating resistor 13a and the switching signal φ2 or φ3 from the control circuit 68 is at a high level, the contact is switched to the ground potential VG side and the integrating resistor 13a is connected to the ground potential VG. Is applied. When the switching signal φ3 from the control circuit 68 is at a high level, the switch element 16b switches the contact to the measured voltage Vin side and applies the measured voltage Vin to the integrating resistor 13b. Is high, the contact switches to the ground potential VG side to apply the ground potential VG to the integrating resistor 13b.

On the other hand, the control circuit 68 of the fifth embodiment is different from that of FIG.
As shown in FIG. 2, with respect to the control circuit 54 of the fourth embodiment,
The following five points (h) to (l) are different. (H) One-shot pulse (exclusive OR gate 62) from pulse output circuit 66 is applied to one input terminal of AND gate 34 in place of external clock CLK.
Output) is input.

(I) The comparator 14b is connected to one input terminal of the AND gate 36 and one terminal of the AND gate 40.
(The second signal PB) is input. (J) The logical sum signal of the Q output of the flip-flop F4 and the Q output of the flip-flop F2 is changed to the switching signal φ1
An OR gate 72 is additionally provided, which outputs an OR gate.

(K) The Q output of the flip-flop F3 is
It is output as switching signal φ3, and switching signal φ4 is not output from control circuit 68. (L) The output signal CMP1 of the comparator 14a is the first signal PA
Since the output signal CMP2 of the comparator 14b is used as the second signal PB, the control circuit 68
Does not include the flip-flop F5, the NOR gate 46, and the OR gate 48.

Except for the matters described above, the configuration is the same as that of the A / D converter of the fourth embodiment. Next, the operation of the A / D converter of the fifth embodiment configured as described above will be described.
This will be described with reference to the time chart shown in FIG. First,
In the initial state where the external reset signal RST is at a high level, all the flip-flops F1 to F
4, F6 are reset, and only the switching signal φ1 of the switching signals φ1 to φ3 becomes high level. Therefore, the switch element 18 is short-circuited and the switch element 16a
Is switched to the power supply voltage VDD side, and the output voltage Vo of the integrator becomes the initial voltage V slightly lower than the first comparison voltage V1.
Held in S.

Then, the reset signal RST changes from the high level to the low level, and the flip-flops F1 to F
4 and F6 are released, and thereafter, as shown at time t1 in FIG. 13, when the external clock CLK rises, a one-shot pulse is output from the pulse output circuit 66, and the one-shot pulse is output to the AND gate 34.
From the flip-flops F1 to F1
The switching signals φ1 to φ4 are input to the clock terminal of F4.
Of φ3, only the switching signal φ2 is at the high level.

Then, the switch element 18 is opened, the contact of the switch element 16a and the contact of the switch element 16b are both switched to the ground potential VG, and the integrator starts to integrate the ground potential VG. Then, the output voltage Vo of the integrator rises from the initial voltage VS with the integration of the ground potential VG. At the timing when the switching signal φ2 changes to the high level, the computing unit 70 performs the above-described computation based on the binary digital signals from the registers 56 and 58, and outputs a binary digital signal representing the voltage Vin to be measured. However, at the time t1, the register 5
Since the 6,58 latch data is immediately after the reset, the binary digital signal output from the arithmetic unit 70 at the time t1 may be ignored.

Thereafter, when the output voltage Vo of the integrator rises and exceeds the first comparison voltage V1 of the comparator 14a, as shown at time t2, the output signal CMP1 of the comparator 14a (that is, the first signal to the TAD 22) is output. Signal PA) changes from the low level to the high level, and the pulse circulating circuit 23 of the TAD 22
Starts the circulation operation of the pulse signal.

Thereafter, when the output voltage Vo of the integrator further rises and exceeds the second comparison voltage V2 of the comparator 14b, as shown at time t3, the output signal CMP2 of the comparator 14b
(That is, the second signal PB to the TAD 22) changes from a low level to a high level. Then, when the second signal PB rises in this way, the TAD 22 causes the first signal PB at time t2.
15-bit data representing the time Td from when the signal PA goes high to when the second signal PB rises at time t3 is output, and the register 56 latches the 15-bit data. At this time, the register 58 latches the 15-bit data output from the register 56 until then.

Therefore, the output signal CMP2 of the comparator 14b
At the time t3 when the signal changes to the high level, the 15-bit data latched by the register 56 is supplied to the integrator by the ground potential V.
When G is integrated, the time required for the output voltage Vo to change by a predetermined voltage corresponding to the first comparison voltage V1 to the second comparison voltage V2 (hereinafter referred to as the integration time of the ground potential VG) Td Will be expressed.

When the second signal PB rises at time t3, the control circuit 68 causes the flip-flops F1 to F4 from the AND gate 36 through the OR gate 42.
, A rising edge is input to the clock terminal and the Q output of the flip-flop F2 goes high, so that only the switching signal φ1 of the switching signals φ1 to φ3 goes high. When the switching signal φ1 becomes high level, the switch element 18 is short-circuited again, and the contact of the switch element 16a is switched to the power supply voltage VDD, so that the output voltage Vo of the integrator is changed to the first comparison voltage. The voltage is returned to the initial voltage VS which is slightly lower than the voltage V1. Therefore, the comparator 14
The output signal CMP2 of b is inverted from the high level to the low level, and immediately thereafter, the output signal CMP1 of the comparator 14a is also inverted from the high level to the low level, and the pulse circulating operation in the pulse circulating circuit 23 stops.

In the fifth embodiment, when the output signal CMP1 (first signal PA) of the comparator 14a is at a low level, the contents stored in the counter 26, the latch circuit 28, and the pulse selector 30 of the TAD 22 are cleared. It has become so. Next, as shown at time t4, when the external clock CLK rises again, the control circuit 68
, A one-shot pulse is output from the pulse output circuit 66, and the one-shot pulse is output from the AND gate 38 via the OR gate 42 to the flip-flop F
1 to F4, the switching signal φ
Only the switching signal φ3 among 1 to φ3 becomes high level.

Then, the contact of the switch element 16a is switched to the ground potential VG side, and the contact of the switch element 16b is switched to the measured voltage Vin side, so that the integrator is now connected to the measured voltage Vin. The integration of a voltage ((Vin + 0) / 2 = Vin / 2) obtained by adding and averaging the ground potential VG is started. Then, the output voltage Vo of the integrator rises again from the initial voltage VS with the integration of the voltage (Vin / 2). In the following description, a voltage obtained by averaging the measured voltage Vin and the ground potential VG is simply referred to as an averaging voltage VH.

Thereafter, when the output voltage Vo of the integrator rises and exceeds the first comparison voltage V1 of the comparator 14a, as shown at time t5, the output signal CMP1 of the comparator 14a (that is, the first signal to the TAD 22) is output. The signal PA) changes from the low level to the high level, and the pulse circulating circuit 2 of the TAD 22
3 starts the pulse signal circulating operation again.

Further, when the output voltage Vo of the integrator rises and exceeds the second comparison voltage V2 of the comparator 14b, as shown at time t6, the output signal CMP2 of the comparator 14b
(That is, the second signal PB to the TAD 22) changes from the low level to the high level again.

As described above, when the second signal PB rises,
The TAD 22 outputs 15-bit data representing the time Te from when the first signal PA goes high at time t5 to when the second signal PB rises at time t6, and the register 56 latches the 15-bit data. . At this time, the register 58 latches the 15-bit data latched by the register 56 at the time t3.

Therefore, the output signal CMP2 of the comparator 14b
At the time t6 when the output voltage Vo changes to the high level, the output voltage Vo of the 15-bit data latched by the register 56 is compared with the output voltage Vo when the integrator integrates the average voltage VH (= Vin / 2). It represents a time Te required to change by a predetermined voltage corresponding to the voltage V1 to the second comparison voltage V2 (hereinafter, referred to as an integration time of the averaging voltage VH) Te. Further, at time t6, the 15-bit data latched in the register 58 represents the integration time Td of the ground potential VG corresponding to the time from time t2 to time t3 in FIG.

When the second signal PB rises at time t6, the control circuit 68 causes the flip-flops F1 to F4 from the AND gate 40 via the OR gate 42.
, A rising edge is input to the clock terminal and the Q-bar output of the flip-flop F4 goes high, so that only the switching signal φ1 of the switching signals φ1 to φ3 returns to the high level. When the switching signal .phi.1 goes high, the output voltage Vo of the integrator is returned to the initial voltage VS again, the output signal CMP2 of the comparator 14b is inverted from high to low, and the output signal of the comparator 14a is output. CMP1 is also inverted from the high level to the low level, and the pulse circulating operation of the pulse circulating circuit 23 stops. afterwards,
Although not shown in FIG. 13, an external clock C
When LK rises again, as in the case of the above-mentioned time t1, only the switching signal φ2 among the switching signals φ1 to φ3 becomes high level, and the integration of the ground potential VG by the integrator is started.

When the switching signal φ2 rises to a high level in this manner, the arithmetic unit 70 sets the register 58 to the time based on the 15-bit data representing the integration time Te of the average voltage VH latched by the register 56 at the time t6. The 15-bit data representing the integration time Td of the ground potential VG latched at t6 is subtracted, and the 15-bit data after the subtraction is divided by the 15-bit data representing the integration time Te latched by the register 56 at time t6. , 2 after the division
Binary digital signal (that is, “(Te−Td) / Te = 1”
−Td / Te ”is output as a binary digital signal representing the measured voltage Vin.

Thereafter, the same operation as that after time t1 described above is repeated. As described above, in the A / D converter of the fifth embodiment, the ground potential is maintained until the output voltage Vo of the integrator changes by the predetermined voltage corresponding to the first comparison voltage V1 to the second comparison voltage V2. VG is integrated and the integration time required for its change (integration time of ground potential VG) Td
Similarly, until the output voltage Vo of the integrator changes by the same amount as the predetermined voltage, the average voltage VH of the measured voltage Vin and the ground potential VG is integrated, and the integration required for the change is calculated. Time (integration time of average voltage VH) Te
Is measured.

Here, during the integration time Td (ie, after the output signal CMP1 of the comparator 14a goes high at time t2 in FIG. 13, the comparator 14a at time t3 in FIG. 13).
The output change voltage Vd of the integrator due to the integration of the ground potential VG only until the output signal CMP2 of “b” becomes high level is expressed by the following equation 12, and during the integration time Te (ie, Only during the period from when the output signal CMP1 of the comparator 14a goes high at time t5 in FIG. 13 until the output signal CMP2 of the comparator 14b goes high at time t6 in FIG. The output change voltage Ve of the integrator due to the integration is represented by the following equation (13).
Becomes

In the equation (12), “∫_ (0) ^ (Td) [0
−Vref] dt ”is a value obtained by integrating the difference [0−Vref] between the ground potential VG (= 0) and the reference voltage Vref by the time Td. Similarly, in equation 13, “∫_ (0) ^ (Te)
[Vin / 2−Vref] dt ”is the average voltage VH (=
Vin / 2) and the reference voltage Vref [Vin / 2−Vref
] Is integrated by the time Te. And Equation 1
In FIGS. 2 and 13, “C” is the capacitance of the integrating capacitor 12 and “R” is the combined resistance value of the integrating resistors 13a and 13b.

[0181]

Vd = −∫_ (0) ^ (Td) [0−Vref] dt / CR = Vref × Td / CR (12)

[0182]

Ve = −∫_ (0) ^ (Te) [Vin−2−Vref] dt / CR = (Vref−Vin / 2) × Te / CR (13) And both output change voltages Vd , Ve are equal to each other, and the following Expression 14 is established from Expressions 12 and 13.

[0183]

[Expression 14] Vin = 2Vref × ((Te−Td) / Te) (14) Therefore, as can be seen from Expression 14, since the reference voltage Vref is known, the value of the measured voltage Vin is equal to the ground potential VG. Can be quantified by the value "(Te-Td) / Te = 1-Td / Te" according to the integration time Td and the integration time Te of the averaged voltage VH.

Therefore, in the A / D converter according to the fifth embodiment, as described above, the integration time T
From the 15-bit data representing e, 1 representing the integration time Td
The 5-bit data is subtracted, the 15-bit data after the subtraction is divided by the 15-bit data representing the integration time Te, and the binary digital signal after the division (that is, “(Te
−Td) / Te = 1−Td / Te ”is output as a binary digital signal representing the measured voltage Vin.

The arithmetic unit 70 calculates the value “(Te−Td) / Te” after the division by “2Vref
, And a binary digital signal representing the value after the multiplication may be output as a binary digital signal representing the measured voltage Vin. Then, in this way, the value of the voltage Vin to be measured can be known without performing any operation in the device that has received the binary digital signal from the A / D converter.

The arithmetic unit 70 stores the 15-bit data representing the integration time Td latched at time t6 by the register 58 and the integration time Te latched by the register 56 at time t6.
, And the binary digital signal after the division (that is, a binary digital signal representing “Td / Te”) is output as a binary digital signal representing the measured voltage Vin. Good.

As described in detail above, A / A
Also in the D converter, an averaged voltage VH corresponding to the unknown voltage under measurement Vin and a known ground potential VG set in advance.
Is converted into a digital value based on the ratio of the integration times Te and Tb when the output change amount of the integrator is integrated so as to be equal. The integration times Td and Te are measured by the TAD 22.

Therefore, according to the A / D converter of the fifth embodiment, the accuracy of A / D conversion can be improved without setting a long integration time unlike the conventional A / D converter. A / D conversion of the measured voltage Vin can be performed with high accuracy and in a short time. Further, since it is not necessary to set the integration time longer, the capacitance of the integration capacitor 12 and the resistance values of the integration resistors 13a and 13b can be reduced, and the A / D converter can be used as one semiconductor. The chip size when integrated on a chip can be reduced.

In the fifth embodiment, the reference voltage Vref of the integrator is set to the center voltage between the ground potential VG and the power supply voltage VDD (= VDD / 2). If it is equal to the power supply voltage VDD, the average voltage VH of the measured voltage Vin and the ground potential VG becomes equal to the reference voltage Vref, and the output voltage Vo of the integrator when integrating the average voltage VH does not change. Would.

Therefore, if the value of the reference voltage Vref is set to a voltage (for example, VDD × 3/4) between the center voltage (= VDD / 2) and the power supply voltage VDD, the measured voltage Vin becomes the power supply voltage. Even if it is equal to VDD, the output voltage Vo of the integrator can be increased in the period from time t4 to time t6 in FIG. 13, and the above problem can be solved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of an A / D converter according to a first embodiment.

FIG. 2 is a configuration diagram illustrating a pulse phase difference encoding circuit (TAD) of FIG. 1;

FIG. 3 is a circuit diagram illustrating a control circuit of FIG.

FIG. 4 is a time chart illustrating an operation of the A / D converter according to the first embodiment.

FIG. 5 is a configuration diagram illustrating a configuration of an A / D converter according to a second embodiment.

FIG. 6 is a configuration diagram illustrating a configuration of an A / D converter according to a third embodiment.

FIG. 7 is a time chart illustrating an operation of the A / D converter according to the third embodiment.

FIG. 8 is a configuration diagram illustrating a configuration of an A / D converter according to a fourth embodiment.

FIG. 9 is a circuit diagram illustrating the control circuit of FIG.

FIG. 10 is a time chart illustrating an operation of the A / D converter according to the fourth embodiment.

FIG. 11 is a configuration diagram illustrating a configuration of an A / D converter according to a fifth embodiment.

FIG. 12 is a circuit diagram illustrating a control circuit of FIG.

FIG. 13 is a time chart illustrating an operation of the A / D converter according to the fifth embodiment.

FIG. 14 is an explanatory diagram illustrating a conventional basic integral A / D converter.

FIG. 15 is an explanatory diagram illustrating a conventional five-phase integral type A / D converter.

[Explanation of symbols]

11, 50: operational amplifier 12: integrating capacitor 13a, 13b: integrating resistor 14, 14a, 14
b ... Comparator 16a, 16b, 18 ... Switching element 17,52 ...
Resistors 20, 54, 68 Control circuit 22 Pulse phase difference encoding circuit (TAD) 23 Pulse circulating circuit 24, 56, 58 Register 26 Counter 28 Latch circuit 30 Pulse selector 32
Encoders 60, 70 ... Calculators 34, 36, 38, 40 ... AND gates 42, 48, 72 ... OR gate 46 ... NOR gate IV, 44 ... Inverter NAND ... NAND gate 62 ... Exclusive OR gate 64 ... Buffer 66 ... Pulse output circuit F1 to F6: flip-flop

Claims (10)

[Claims] An integrator for integrating and outputting an input voltage; and an integrator for outputting one of a voltage corresponding to a voltage to be measured and a preset voltage until a predetermined condition is satisfied. In the meantime, the first integrator integrates, and the first control operation of measuring the integration time as the first integration time, and the first control operation of the voltage according to the measured voltage and the set voltage. The other voltage different from the integrator is integrated by the integrator, and the time until the output change amount of the integrator matches the output change amount of the integrator by the first control operation is referred to as a second integration time. And A / D converting the measured voltage into a digital value based on a ratio of the first integration time and the second integration time.
A converter, wherein a plurality of inverting circuits for inverting and outputting an input signal are connected as time measuring means for the integration control means to measure the first integration time and the second integration time;
A delay circuit that sequentially inverts and propagates the pulse signal by each of the inversion circuits, and calculates a phase difference time of a pulse signal sequentially output from a plurality of predetermined inversion circuits among the inversion circuits that constitute the delay circuit; An A / D converter comprising encoding means capable of binary encoding time as a resolution. 2. The A / D converter according to claim 1, wherein the delay circuit is configured such that the inverting circuit is connected in a ring shape, and a specific inverting circuit of the inverting circuit is configured to receive an input signal. A pulse circulating circuit that is configured as a start-up inverting circuit that can control the inverting operation by a first signal from the outside, and in which each of the inverting circuits sequentially inverts and circulates a pulse signal as the starting inverting circuit starts the inverting operation. A counter that counts the number of times the pulse signal circulates in the pulse circulating circuit and outputs a binary digital signal representing the counted number, in addition to the pulse circulating circuit; A latch circuit that latches and outputs a binary digital signal from the counter when a second signal is input from the outside; It receives the output signals of the plurality of inverting circuits which are, the second
When a signal is input, a pulse signal generated by the start of the inverting operation of the starting inverting circuit is detected to reach which inverting circuit in the pulse circulating circuit, and the pulse is output from the inverting circuit for starting. A pulse detection circuit that outputs a binary digital signal according to the number of inverting circuits up to the inverting circuit that has detected that the signal has arrived, and the binary digital signal from the latch circuit is used as upper bits, and The binary digital signal from the pulse detection circuit is configured to output a binary digital signal representing a phase difference between the first signal and the second signal, using the lower bit as a lower bit. When the first control operation is started to cause the integrator to start integrating the one voltage, the first signal is outputted to the inverting circuit for starting, and the pulse of the pulse recirculation circuit is output. When a predetermined bit of the counter changes after that, the first control operation is terminated assuming that the predetermined condition has been satisfied, and the second control operation is started to cause the integrator to start the other operation. Integrating the voltage is started, and thereafter, when the output change amount of the integrator matches the output change amount of the integrator by the first control operation, the second signal is output to the latch circuit and the pulse detection circuit. An A / D converter, characterized in that: 3. The A / D converter according to claim 1, wherein the integration control means performs the integration until the output voltage of the integrator changes by a predetermined voltage as the first control operation. An integrated circuit for integrating the one voltage, and measuring a time required for the change as the first integration time. 4. An operational amplifier having a predetermined reference voltage applied to a non-inverting input terminal, an integrating capacitor connected between an output terminal and an inverting input terminal of the operational amplifier, and an inverting input terminal of the operational amplifier. And an integrating resistor having one terminal connected thereto, and integrates a voltage input to a terminal of the integrating resistor opposite to the inverting input terminal, and outputs the result from an output terminal of the operational amplifier. An integrator that performs a magnitude comparison between an output voltage of the integrator and a predetermined comparison voltage; and an output signal of the comparator in a predetermined direction from a high level to a low level or from a low level to a high level. Initial setting means for changing the output voltage of the integrator so that the output voltage of the integrator is inverted; and when the output signal of the comparator is inverted by the operation of the initial setting means, a first integration time set in advance from that time. The integrator integrates a voltage corresponding to the voltage to be measured, and changes the output voltage of the integrator so that the output signal of the comparator is inverted in a direction opposite to the predetermined direction. When the integration time elapses, the integrator integrates a preset set voltage, and changes the output voltage of the integrator so that the output signal of the comparator is again inverted in the predetermined direction. Integrating control means for measuring a time from the start of integration of the comparator to the inversion of the output signal of the comparator as a second integration time, wherein a ratio of the first integration time to the second integration time is provided. A / D converting the measured voltage to a digital value based on
In the converter, the initial setting means includes a resistor and a switch element connected in series, and further includes a voltage setting circuit connected in parallel with an integrating capacitor forming the integrator. By applying a predetermined voltage to the integrating resistor in the short-circuited state, the output voltage of the integrator is held at a voltage near the voltage at which the output signal of the comparator is inverted in the predetermined direction, and thereafter By opening the switch element, applying the set voltage to the integrating resistor, and integrating the set voltage in the integrator, the output signal of the comparator is inverted in the predetermined direction. A / D converter, wherein the output voltage of the integrator is changed. 5. An operational amplifier in which a predetermined reference voltage set between a preset set voltage and a second set voltage different from the set voltage is applied to a non-inverting input terminal. An integrating capacitor connected between an output terminal and an inverting input terminal; and an integrating resistor having one terminal connected to the inverting input terminal of the operational amplifier, wherein the inverting input of the integrating resistor is provided. An integrator that integrates a voltage input to a terminal opposite to the terminal and outputs the integrated voltage from an output terminal of the operational amplifier; a comparator that compares the output voltage of the integrator with a predetermined comparison voltage; Initial setting means for changing an output voltage of the integrator so that an output signal of the comparator is inverted in a predetermined direction from a high level to a low level or from a low level to a high level; and operation of the initial setting means By When the output signal of the comparator is inverted, the integrator integrates a voltage corresponding to the voltage to be measured for a first integration time set in advance from that time, and outputs the output voltage of the integrator to the comparator. Is changed so that the output signal is inverted in a direction opposite to the predetermined direction. After the first integration time has elapsed, the integrator integrates the set voltage, and the output voltage of the integrator is compared with the output voltage of the integrator. Change so that the output signal of the device is again inverted in the predetermined direction,
Integration control means for measuring the time from the start of integration of the set voltage to the inversion of the output signal of the comparator as a second integration time, wherein the first integration time and the second integration time A / D that converts the measured voltage into a digital value based on the ratio
In the converter, the reference voltage is set to a center voltage between the set voltage and the second set voltage or a voltage between the center voltage and the set voltage. During the first integration time, a voltage obtained by averaging the measured voltage and the second set voltage is integrated by the integrator as a voltage corresponding to the measured voltage. An A / D converter, characterized by: 6. The A / D converter according to claim 5, wherein said integrator has two integrating resistors each having one terminal connected to an inverting input terminal of said operational amplifier. The control means applies the measured voltage and the second set voltage to the two integrating resistors during the first integration time, respectively, so that the measured voltage and the A voltage obtained by averaging the second set voltage and the second set voltage is integrated, and after the first integration time elapses, the set voltage is applied to each of the two integrating resistors, whereby the set voltage is applied to the integrator. A / D converter, wherein: 7. The A / D converter according to claim 5, wherein said initial setting means comprises a resistor and a switch element connected in series, and in parallel with an integrating capacitor forming said integrator. A voltage setting circuit connected thereto, wherein a predetermined voltage is applied to the integrating resistor in a state where the switch element is short-circuited, so that an output voltage of the integrator and an output signal of the comparator correspond to the predetermined voltage. By holding the voltage near the voltage inverting in the direction, and then opening the switch element, applying the set voltage to the integrating resistor, and integrating the set voltage to the integrator, An output voltage of the integrator is changed so that an output signal of the comparator is inverted in the predetermined direction. 8. The A / D converter according to claim 6, wherein said initial setting means comprises a resistor and a switch element connected in series, and in parallel with an integrating capacitor forming said integrator. A voltage setting circuit connected thereto, by applying the second setting voltage to one of the two integrating resistors in a state where the switch element is short-circuited, The output voltage of the integrator is held at a voltage near the voltage at which the output signal of the comparator is inverted in the predetermined direction, and then the switch element is opened, and the two integrating resistors are connected to the two integrating resistors. By applying a set voltage, respectively, the output voltage of the integrator is changed such that the output signal of the comparator is inverted in the predetermined direction by integrating the set voltage in the integrator. You A / D converter. 9. The A / D converter according to claim 4, wherein said integration control means is a time measurement means for measuring said first integration time and said second integration time, A plurality of inverting circuits for inverting and outputting an input signal are connected,
A delay circuit that sequentially inverts and propagates the pulse signal by each of the inversion circuits, and calculates a phase difference time of a pulse signal sequentially output from a plurality of predetermined inversion circuits among the inversion circuits that constitute the delay circuit; An A / D converter comprising encoding means capable of binary encoding time as a resolution. 10. The A / D converter according to claim 9, wherein the delay circuit is configured such that the inverting circuits are connected in a ring shape, and a specific inverting circuit of the inverting circuits is configured to receive an input signal. A pulse circulating circuit that is configured as a start-up inverting circuit that can control the inverting operation by a first signal from the outside, and in which each of the inverting circuits sequentially inverts and circulates a pulse signal as the starting inverting circuit starts the inverting operation. A counter that counts the number of times the pulse signal circulates in the pulse circulating circuit and outputs a binary digital signal representing the counted number, in addition to the pulse circulating circuit; A latch circuit that latches and outputs a binary digital signal from the counter when a second signal is input from the outside; Receives the output signals of the plurality of inverting circuits because obtained, the second
When a signal is input, a pulse signal generated by the start of the inverting operation of the starting inverting circuit is detected to reach which inverting circuit in the pulse circulating circuit, and the pulse is output from the inverting circuit for starting. A pulse detection circuit that outputs a binary digital signal according to the number of inverting circuits up to the inverting circuit that has detected that the signal has arrived, and the binary digital signal from the latch circuit is used as upper bits, and The binary digital signal from the pulse detection circuit is configured to output a binary digital signal representing a phase difference between the first signal and the second signal, using the lower bit as a lower bit. When the integrator starts integration of a voltage corresponding to the voltage to be measured, the first signal is output to the inverting circuit for starting to open the pulse circulating operation of the pulse circulating circuit. Then,
Thereafter, when a predetermined bit of the counter changes, the first integration time is passed and the integrator starts to integrate the set voltage. Thereafter, when the output signal of the comparator is inverted in the predetermined direction, An A / D converter configured to output the second signal to the latch circuit and the pulse detection circuit.