JPH03158020A - Integration type a/d conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an oscillator mounted externally by counting an integration pulse coming from an oscillator source being an internal ring oscillator. CONSTITUTION:A control circuit 8 allows a 2nd selector 14 in a timing signal generating circuit 7 to other timing pulse width 33. Then the output 34 of an integration device reaches a positive calibration voltage in the same time, but the increment of a counted value 42 takes a different inclination because of the different timing pulse width. In order to select the timing pulse width closest to the correct inclination, the control circuit 8 changes its control code for an analog switch array to select a timing pulse width offering the closest inclination to the correct inclination. After the coarse adjustment, the control circuit 8 varies the control code controlling the connection of the current source of a charge pump section 3, to apply fine adjustment to one charge quantity, thereby allowing the output 35 of the integration device to reach the positive calibration voltage in a different time. Thus, an expensive externally mounted oscillator is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion circuit, and particularly to an integral type A/D conversion circuit having an internal clock signal source.

[Conventional technology]

Conventionally, in an integral type A/D conversion circuit, as shown in FIG. 2, a sample hold 21 of an input analog signal, a comparator 22 connected to the output thereof, and a comparator output are used to count up and stop the count up. , a counter 23 that outputs the count value, and a charge pump unit 24 that receives an external high-frequency clock as input.
and a buffer amplifier 25 having an output that returns the output of the charge pump section to the other end of the comparator 22, and the charge pump section 24 includes a current source 26 whose one end is connected to a reference voltage source, and a current source 26 whose one end is connected to GND. capacitor 27
and an analog switch 28 for switching the connection between the current source 26 and the capacitor 27.

In this circuit, an integrator consisting of a charge pump section 24 and a buffer amplifier 25 generates a ramp voltage using an external high frequency clock.

The high frequency clock input to the charge bomb 1 section 24 was counted until the voltage became equal to the input voltage, and the counted value was used as the A/D conversion value.

[Problem to be solved by the invention]

The above-described conventional integral type A/D conversion circuit requires an external high-frequency clock to control the charge and count up the counter, and has the drawback that it requires an externally expensive oscillator.

An object of the present invention is to provide an integral type A/D conversion circuit that solves the above problems.

[Means for Solving the Problem] In order to achieve the above object, 1. the integral form A/ in the present invention.
The D conversion circuit includes a first selector that receives an input analog signal and a positive calibration voltage and switches between them using a reset signal at power-on, and a sample hold that holds the output from the first selector. A comparator connected to the sample hold, a counter that counts up and stops counting up based on the output of the comparator, and uses that value as an output signal, a ring oscillator that generates a timing signal, and each bit output of the ring oscillator. a second selector that is connected to the output terminal and selects and outputs the timing signal, and a current source array and a switch array that are connected to a positive power source and a negative calibration voltage source. It has a charge pump section that performs switching, and a buffer amplifier that connects the output from the charge pump section to the curved end of the comparator, outputs a control code according to the output signal from the counter, and outputs a control code at the second selector. This selects the signal and selects the current source in the charge pump section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, the present invention includes a first selector that receives an input analog signal and a positive calibration voltage and switches them by a reset signal at power-on;
A sample hold 2 that holds the output from the circuit, a charge pump section 3 connected to a current source and outputs charge by switching, a buffer amplifier 4 connected to the charge pump section 3, and a sample hold output and a buffer amplifier output. A comparator 5 for comparison, and a counter 6 for counting up and stopping counting up based on the comparator output and outputting the count value as an A/D converted value.
and a timing signal generation circuit 7 that generates a timing signal for switching the counter and the charge bong.
The control circuit 8 includes a control circuit 8 that generates a control signal that controls the timing signal width of the timing signal generation circuit 7 and the charge amount of the charge pump section 3. The charge pump section 3 is connected to a current source array 9 consisting of n independent current sources, one end of which is connected to a positive power supply VDD, and the control circuit 8.
an analog switch row 10 having n analog switches whose switching is controlled by control signals from;
An analog switch 11 controlled by the timing signal from the timing signal generation circuit 7, and a capacitor whose one end is connected to a negative calibration voltage source and the other end is connected to the analog switch 11, and which stores the output of the charge pump section 3. It consists of 12.

The timing signal generation port #17 includes a ring oscillator 13 that outputs n different timing signals, and a second selector 14 that is connected to each output of the ring oscillator 13, selects the output, and outputs it as a timing signal. Become. The operation of this circuit uses the timing signal generation circuit 7 instead of an external high-frequency clock, and since the pulse width of the timing pulse is not determined, the input signal is set to a positive calibration voltage when the power is turned on for calibration. The voltage range of the A/D conversion is controlled by the first selector 1 for switching, and the control circuit 8 that determines the timing pulse width of the timing signal generation circuit 7 and the amount of charge at one time of the charge pump section 3. This is the same as the prior art except that it has a means for achieving the MAX value of .

Calibration means for adjusting the voltage range of A/D conversion to the MAX value of A/D conversion will be explained with reference to FIGS. 3 and 4. At power-on, when a positive calibration voltage source is selected by the first selector 1 instead of the input signal by the reset signal, the output 31 of the integrator consisting of the charge pump section 3 and the buffer amplifier 4 becomes a positive voltage source. The voltage increases until it becomes equal to the calibration voltage. Here, the value 41 obtained by counting the timing pulses 32 that drove the charge pump section 3 should be the MAX value of A/D conversion for the voltage range consisting of the difference between the positive calibration voltage and the negative calibration voltage. However, depending on the timing pulse width, it may not be the correct value. Therefore, the control circuit 8 controls the timing signal generation port 1R17.
Another timing pulse width 3 is input to the second selector 14 in the middle.
Let them choose 3. Then, the output 34 of the integrator reaches the positive calibration voltage in the same time, but since the timing pulse width is different, the counter Wi 42 has an increased slope. Here, the control circuit 8 changes the control code to select the timing pulse width closest to the correct slope.
After the adjustment, the control circuit 8 changes the control code that controls the connection of the current source of the charge pump section 3, performs the charge amount n times, and becomes correct at the time when the output 35 of the integrator rises. to reach the calibration voltage. Then, the count 43 of the timing pulse changes slightly, so this is brought closer to the MAXI of A/D conversion, and finally, the timing pulse width and charge amount are fixed at a combination that is close to the ideal, and the A/D conversion The voltage range of A/
Calibrate to correspond to the MAX value of D conversion.

〔Effect of the invention〕

As explained above, in an integral type A/D conversion circuit, the present invention counts integral pulses from an internal ring oscillator oscillation source without using an external high-frequency clock, so an expensive external oscillator is required. Furthermore, by determining the ring oscillator pulse width and A/D conversion quantization width at power-on reset, it is possible to correct the fact that the ring oscillator pulse width is not completely arbitrary. be.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an integral type A/D conversion circuit of the present invention,
Figure 2 is a configuration diagram showing a conventional integral type A/D conversion circuit, Figure 3 is a diagram showing the relationship between voltage value and time of A/D conversion during calibration, and Figure 4 is a diagram showing the A/D conversion circuit during calibration. FIG. 3 is a diagram showing a relationship between a conversion voltage value and a count value. 1...-first selector 2...sample hold 3...charge pump section 4...buffer amplifier 5
...Comparator 6...Counter 7...Timing signal generation circuit 8...Control circuit 9...Current source array 10...
・Analog switch row 11...Analog switch 12...Capacitor 1
3... Ring oscillator 14... Second selector Figure 1 Figure 3

Claims (1)

[Claims] (1) A first selector that receives an input analog signal and a positive calibration voltage and switches between them using a reset signal at power-on, a sample hold that holds the output from the first selector, and the sample hold. A comparator connected to the oscillator, a counter that counts up and stops counting based on the output of the comparator and uses that value as an output signal, a ring oscillator that generates a timing signal, and a ring oscillator that is connected to each bit output of the ring oscillator. , a second selector that selects and outputs the timing signal, and a current source array and a switch array connected to a positive power source and a negative calibration voltage source, and switching is performed by the timing signal from the second selector. comprising a charge pump section and a buffer amplifier that connects the output from the charge pump section to the other end of the comparator,
An integral type A/D conversion circuit, characterized in that a control code is output based on an output signal from the counter, and the second selector selects a signal and the charge pump section selects a current source.