JPH057161A - D/a converter - Google Patents

Abstract

PURPOSE:To use an inexpensive ring oscillator as an integration timing pulse of an integration type D/A converter. CONSTITUTION:A ring oscillator 1 whose stage number N is variable is employed and a full scale digital value is inputted at power-on reset, the stage number N and the integration gain are adjusted to calibrate the ring oscillator 1. The integration gain is controlled by controlling a charge M of a current source of an integration charge pump section 7. The values N,M are adjusted while an output of a comparator 9 is detected so that a full scale digital value is converted into a full scale analog value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to an adjustment method for a power-on reset of an integral D / A converter.

[0002]

2. Description of the Related Art A conventional integrating D / A converter has a structure shown in FIG. The input digital signal is one input of the magnitude comparator 5, and the output of the counter 3 is supplied to the other inputs.

The counter 3 counts a high frequency clock from the outside, and the count value and the value of the digital input signal are compared by a magnitude comparator 5,
A match signal is generated when the two match.

The control circuit 6 supplies the clock signal to the switch 14 of the charge pump section 7 from the input timing of the digital input signal to the generation timing of the coincidence signal,
In synchronism with this clock signal, the current of the current source 28 is passed through the capacitor 15 to be charged up and integrated.

This integrated output is sampled and held by a sample hold circuit 10 via a buffer 8. This hold output is LPF (low pass filter)
It becomes an analog output signal via 11.

In this circuit, the charge pump unit 7
The ramp voltage is generated by the timing signal obtained from the clock signal from the outside by the integrator composed of the buffer up 8. When the magnitude comparator 5 detects that the number of times the timing signal has been input matches the value of the digital input signal, the sample-and-hold circuit 10 holds the output voltage of the integrator at that time to obtain an analog value.

In the above-mentioned conventional integral type D / A converter, a high-frequency clock signal from the outside is used to operate the charge pump unit 7 and to count up the counter 3, so that the externally mounted external D / A converter is used. Has the disadvantage of requiring an expensive oscillator.

[0008]

An object of the present invention is to use an internal clock oscillator without using an external high-frequency clock oscillator, and to automatically adjust the clock frequency and the integral gain of the integrator to obtain an optimum clock. An object of the present invention is to provide a D / A converter with adjustable frequency and integral gain.

[0009]

According to the present invention, a counter for counting clock signals, a magnitude comparator for generating a coincidence signal when the value of the counter coincides with the value of the input digital signal, and the input timing of the digital signal. To a generation timing of the coincidence signal, the D / A converter includes an integrating means for performing integration while performing charge-up with a constant current, and a means for deriving an integrated output of the integrating means as an analog signal, A ring oscillator whose number of stages is variable as a signal generation source, a selector which selects a full-scale digital signal and the input digital signal and supplies them to the magnitude comparator, and a variable control of a constant current value for charge-up of the integrating means. And a ratio of the output of the integrating means to the analog full scale value. When the full scale digital signal is selected by the comparing means and the selector, the number of stages of the ring oscillator is set to a predetermined initial value, and the constant current value is set to a predetermined initial value. A D / A converter including: a control unit that controls the number of stages and the constant current value according to the output result of the comparator to adjust the number of stages and the constant current value.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and the same parts as those in FIG. 5 are designated by the same reference numerals. The selection output of the selector 4 is applied to the digital input section of the magnitude comparator 5, and this selector selectively derives the input digital signal and the digital full scale value.

The output of the ring oscillator 1 having a variable number of stages is applied to the count input of the counter 3, and the control circuit 6 receives the output of the ring oscillator 1 as an input.

A control circuit 2 for controlling the number of stages of the ring oscillator 1 is provided, and the control circuit 2 also controls the integral gain of the integrator. That is, it controls the jersey-up constant current value of the capacitor 15 of the charge pump section 7, and selectively turns on the analog switch row 13 corresponding to the row 12 of the plurality of current sources.

Then, the integrated output of the buffer amplifier 8 becomes one input of the comparator 9, and in this comparator 9, the integrated value at the time of digital full scale is converted into the analog full scale which is the difference between the positive power supply voltage and the negative power supply voltage. It is designed to be compared with the voltage. The comparison output is input to the control circuit 2, and the count value of the counter 3 is input to the control circuit 2. The control circuit 2 adjusts the number of stages of the ring oscillator 1 and the integral gain according to these inputs.

That is, a ring oscillator 1 having a variable number of stages for generating a timing signal is used instead of the high frequency clock from the outside in FIG. 5, and the pulse width of the timing signal is not fixed. At power-on, the full-scale digital value and the full-scale analog value are compared, and the number of stages and the integral gain described above are adjusted so that they match.

FIG. 2 is a flow chart showing the operation of the circuit of FIG. 1 at the time of power-on calibration, and FIGS. 3 and 4 are diagrams showing an example of an operation timing chart at that time. The operation of the embodiment of the present invention will be described below with reference to these drawings.

Now, the number of stages of the ring oscillator 1 is represented by N, and the output from the control circuit 2 to the ring oscillator 1 is a decode signal for selecting the number of stages N.
Further, the total number of charges in the current source array 12 is M, and the current sources in the current source array 12 are “1”, “2”, “4”,
It is designed to have a charge amount such as "8", so that M can take a desired integer value of 0 or more by selecting one or more current reductions. The control circuit 2 also generates a decode signal for selectively turning on the analog switch row 13 to control the charge amount M of the current source row 12.

At power-on, the selector 4 selects the digital full-scale value and inputs it to the magnitude comparator 5. First, the control circuit 2 has N = 1 and M = 1.
Then, each decode signal is output to control the ring oscillator 1 and the analog switch array 13.

As a result, the output of the integrator consisting of the charge pump unit 7 and the buffer up 8 increases until the number of times the tamping pulse a is generated reaches the digital full scale value 2 ⁿ , as shown by A in FIG. 3, for example. To do.

However, when the timing pulse width of the ring oscillator 1 deviates from the ideal value, the integrator output slope (A in FIG. 4) with respect to the number of timing pulses is not normal. Therefore, the output A of the integrator does not reach the analog full scale voltage when the number of timing pulses reaches the digital full scale value. Since this can be discriminated by the output of the comparator 9, the control circuit 2 switches the number N of stages of the ring oscillator 1 to, for example, N = N + 2.
(Note that N is set every two steps, but logically it may be changed every other step).

Then, the width of the timing pulse is b in FIG.
The pulse width shown in FIG. 4 is obtained, so that the output of the integrator with respect to the number of timing pulses becomes as shown in B of FIG. 3, and the inclination thereof changes as shown in B of FIG.

In this way, the control circuit 2 makes the output of the integrator approach the correct one as shown in C of FIG. 3 and C of FIG.
N is controlled sequentially.

In this way, when the output of the comparator 9 changes, the rough adjustment is completed, and then the fine adjustment is performed. The control circuit 2 reduces the number N of stages of the ring oscillator 1 to N-2 and repeats the same operation as above, but if the integrated output does not reach the full-scale analog voltage by the comparator 9 at this time, M is changed to M + 1. Control to increase the integral gain.

As a result, when the integrated output reaches the analog full-scale voltage, the fine adjustment is completed, and the timing pulse width at that time (the number N of stages of the ring oscillator 1 and the one-to-one correspondence)
2) and the charge amount M of the charge pump unit (corresponding to the integral gain) are fixed, and thereafter N and M are used as N and M of the D / A converter.

In this way, the full scale adjustment of the D / A converter is completed, and the selector 4 operates to select the input digital signal.

[0026]

As described above, according to the present invention, an inexpensive internal ring oscillator is used irrespective of the clock signal from the outside, and the point that the pulse width of this ring oscillator is not perfect at the time of power-on reset. Since the number N of ring oscillator stages and the charge pump current source M are adjusted and corrected, there is an effect that an inexpensive and accurate D / A converter can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is an operation flow chart at the time of calibration of the embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between an integrated voltage value and a timing pulse at the time of calibration.

FIG. 4 is a diagram showing a relationship between an integrated voltage value at the time of calibration and the number of timing pulses generated by a ring oscillator.

FIG. 5 is a block diagram of a conventional D / A converter.

[Explanation of symbols]

 1 Ring Oscillator 2, 6 Control Circuit 3 Counter 4 Selector 5 Magnitude Comparator 7 Charge Pump 8 Buffer Amplifier 9 Comparator 10 Sample Hold Circuit 11 LPF 12 Current Source Sequence 13 Analog Switch Sequence 14 Analog Switch 15 Capacitor

Claims (1)

Claim: What is claimed is: 1. A counter for counting a clock signal, a magnitude comparator for generating a coincidence signal when a value of the counter coincides with a value of an input digital signal, and an input timing of the digital signal. To D-A including an integrating means for performing integration while performing charge-up with a constant current from the coincidence signal to the generation timing of the coincidence signal, and a means for deriving an integrated output of the integrating means as an analog signal.
A converter, which is a ring oscillator having a variable number of stages as a generation source of the clock signal, a selector for selecting a full-scale digital signal and the input digital signal and supplying them to the magnitude comparator, and a charge-up of the integrating means. Means for variably controlling the constant current value for use, a comparing means for comparing the output of the integrating means with an analog full scale value, and a full scale digital signal selected by the selector, the number of stages of the ring oscillator is changed. Adjusting the number of stages and the constant current value by setting a predetermined initial value and setting the constant current value to a predetermined initial value, and controlling the number of stages and the constant current value according to the output result of the comparator at this time. A D / A converter including: