JPH04207521A - Time constant adjustment circuit - Google Patents

Abstract

PURPOSE:To reduce the dispersion in the characteristic of the set by digitizing control information of a time constant adjustment circuit so as to form a time constant adjustment loop able to be digitally controlled. CONSTITUTION:A comparator 7 outputs an H level when a sample-and-hold output is higher than a comparison voltage V2, and a comparator 8 outputs an H level when a sample-and-hold output is lower than a comparison voltage V1. Then outputs of the comparators 7, 8 are inputted to AND gates 9, 10 and a clock signal CK5 is fed to the other input terminal. An output of the gate 9 connects to an up-count terminal of an up-down counter 11, an output of the gate 10 connects to a down-count terminal and an output in nBIT of the counter 11 is fed back to a capacitor C5 of a programmable capacitor array(PCA) 12. Thus, an output data of the time constant adjustment circuit is directly controlled and the dispersion in the characteristic due to the dispersion in the time constant of an IC is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention particularly relates to a time constant adjustment circuit that automatically reduces variations in time constants.

(Conventional technology) FIG. 8 shows a conventional specific number automatic adjustment circuit.

A clock CKI is input as a reference signal from an external reference signal generator (not shown). Based on this tarlock signal CKI, the charge/discharge circuit 1 connects the capacitor CI to the charge/discharge current source 1.
Charge and discharge the eont current. The peak voltage of the waveform created by charging and discharging is detected by the peak hold circuit 2 and stored in the hold capacitor C2. Comparison circuit 3 compares the peak voltage and reference voltage V ref and outputs the comparison result as I
It is accumulated in the external integral capacitor C3. The charging/discharging current source 1 cont is controlled by the output of the comparison circuit 3, and a negative feedback loop is formed as a whole so that the peak hold voltage is equal to V ref'.

FIG. 8 will be explained in more detail using the waveform diagram of FIG. 9. It is assumed that the clock signal CKl is a signal as shown in FIG. 9(a), and that the clamp circuit operates when the voltage of the capacitor C1 becomes low.

The charging/discharging circuit 1 charges the capacitor C1 with the charging/discharging current source I cont during the period when the clock signal CKI is "H", and the charging/discharging current source 1 can charges the capacitor C1 during the period when the clock signal CKI is "L".
Discharge with a current greater than t. As a result, a charging/discharging waveform as shown in (b) is obtained. Since the discharging current is larger than the charging current, the falling slope is steeper than the rising slope. The reason why the O voltage remains constant at the bottom during the discharge period is because the clamp circuit is turned on, and this bottom voltage becomes the start voltage for the next charging operation. The peak hold circuit 2 holds the peak voltage of this waveform (b). This results in a waveform as shown by the dashed line in FIG. 9(b). The normal peak hold circuit 2 has a leakage current to release the hold voltage.
After holding the chevron-shaped waveform peak of waveform (b), discharge is performed from above until the next peak occurs. The operation of charging C2 again at the next peak is repeated. The comparison circuit 3 compares the two peak bold voltages with V ref and controls the current source so that the peak voltage is equal to V ref.

If the amplitude of the charging waveform is Vcl and the half cycle time of the tarlock signal CKJ is T, then Vcl-I C0nt-T, /Cl
=-(1), and the charge/discharge waveform bottom clamp voltage is v
b, the peak voltage Vpl is as follows.

Vpl=Vcl+Vb=12
) Since the loop is closed so that Vpl and Vref are equal, if Vb is constant, Vcl can be kept constant. Furthermore, if the reference time T of the clock signal CKI is created from a highly stable signal source such as a crystal oscillator, T can be kept constant, and I cont/C1 can be kept constant.

A resistor is usually used to generate the charging/discharging current source 1 cont. For example, if we create this current by converting the power supply voltage Vcc with a resistor, I cont = 'v' cc/ R-(3), and I cont/C1-Vcc/ (R-C1) = 1
4). As can be seen from equation (4), the loop operates so that the left side is constant, so if the power supply voltage Vcc is constant, control is applied so that the product of the resistor R and the capacitor CI is equal.

Therefore, the time constant is always constant, and by outputting the current of I cont to another block using a current mirror circuit or the like, it can be used for adjusting a circuit that can control the current (for example, free-run frequency adjustment of a VCO).

(Problem to be solved by the invention) Since the circuit shown in Figure 2 basically contains control information or analog current, even if it is to be used for other blocks, it is necessary to have a circuit configuration that can control the current. The fatal drawback is that it cannot be used and the time constant cannot be adjusted. For example, in the video signal processing of a television receiver, this adjustment current information is only used to adjust the cutoff frequency of a filter, and cannot be used in the circuit portion that accounts for more than 90% of the other circuits. The above-mentioned filters are chroma band-pass filters and tick-off filters, which have a biquad filter configuration and have recently been increasingly incorporated into ICs. Even this filter circuit has a number of disadvantages, so careful consideration is required when adopting it, and there is a tendency for it to be avoided.

Therefore, there may be no need for a filter circuit for adjustment, and many TV ICs do not include a time constant adjustment circuit. Therefore, variations in the time characteristics of each TV set due to the IC time constant are completely eliminated by I
This results in an extremely unreasonable situation where the customer becomes dependent on process variations, and the cents purchased by the customer may be hit or miss.

In addition, as a fundamental operation, adjustments are made again every time the power is turned on, so it takes time to converge, and there is also the disadvantage that high-speed convergence is lacking.

An object of the present invention is to provide a time constant adjustment circuit that has general versatility in time constant adjustment information, can automatically adjust the time constant of the entire IC, and further minimizes variations in set characteristics.

[Structure of the Invention] (Means for Solving the Problems) The present invention digitizes control information of a time constant adjustment circuit to create a digitally controllable time constant adjustment loop. In particular, the charging/discharging waveform of the charging/discharging circuit was made into a trapezoidal wave, and a dentally controllable /A circuit or a programmable =2 capacitor array was used to control the peak value.

(Function) Since the adjustment control information is digitized by the above-described means, the operations of other blocks can be easily realized without being limited to the current control type. For example, if all the capacitances of each block are made into a programmable capacitor array, it can be directly controlled by the output data of the time constant adjustment circuit, and it is possible to extremely reduce the variation in characteristics caused by the variation in the time constant of the IC.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The charging/discharging circuit 5 inputs the two zeros CK2 and CK3, and charges the capacitor C5 of the programmable capacitor array (hereinafter referred to as PCA) 12 using the charging/discharging current source 1 cont. It is assumed that the clamp circuit operates when the voltage of the capacitor C5 becomes lower than a certain voltage.

The charging/discharging circuit 5 is set not to perform charging/discharging for a certain period after charging is completed. The sample and hold circuit 6 and the capacitor C4 hold the peak of the charging waveform.

The sample and hold outputs are input to comparators 7 and 8. It is assumed that the comparator 7 outputs "H" when the sample and hold output is higher than the comparison voltage v2.

It is assumed that the comparator 8 outputs "H" when the sample and hold output is lower than the comparison voltage 1. The outputs of the respective comparators 7 and 8 are input to AND gates 9 and 10. A clock signal CK5 is applied to the other input terminal of each ant gate 9,10. The output of gate 9 is
Connect to the up count terminal of the up/down counter 11, and output the output of the gate 10 to the up/down counter 11.
Connect to the down count terminal.

PCAI output of nBIT of up/down counter 11
It is fed back to the capacitor C5 of No. 2, and the whole constitutes a feedback loop.

The operation of this circuit will be explained in more detail using FIG. If the waveform of the clock signal CK2 for charging that is active during the ``H'' period is as shown in (a), and the waveform of the clock signal CK3 for discharging is as shown in (b), the output of the charging/discharging circuit 5 is The waveform is as shown in (C).The charging/discharging circuit 5 is set in advance to have a period in which neither charging nor discharging is performed, so the waveform is trapezoidal.During discharging, the charging/discharging current source 1 cont. Since it also discharges with a large current, the slope of discharging is steeper than that of charging.

When the battery discharges to a certain voltage, the clamp circuit turns on and prevents the voltage from dropping below that level. This clamp voltage is the starting voltage for the next charge.

During the charging/discharging stop period, the charging/discharging current does not completely become zero due to leakage current, etc., so it is necessary to quickly sample and hold the voltage at which charging is completed. Therefore, the sampling pulse CK4 of the sample and hold circuit 6 was set at the position of waveform (d). Ideally, the sampling pulse should be short and close to the starting point of the top and bottom of the trapezoidal wave, as shown by the dotted line in waveform (d). If the influence of leakage current etc. can be ignored, the sample and hold circuit 6 may be deleted.

If the charging end voltage (voltage at the top part) of the trapezoidal wave just sampled is higher than the comparison voltage V2, the output of comparator 7 will be H.
°, and the output of the comparator 8 becomes "L". When this signal and the clock signal CK5 are ANDed, only the clock CK5 is output to the gate 9 output. Kate 1
The output of 0 remains "L'. Therefore, the up/down counter 1 performs up-counting by 1, and the output data increases by 1, and the capacitance value of capacitor C5, which is PCA, becomes 1.
The count increases.

In the next charging cycle, the end-of-charge voltage will be lower than the previous one because the capacity has increased. If it is still higher than the comparison voltage V2, one more count is made, and the capacitance value also increases by one count. This operation continues until the voltage becomes lower than the comparison voltage V2, and finally the charging end voltage comes to be between the comparison voltage V2 and the comparison voltage V1.

Here, the configuration of the PCA 12 will be explained using FIG. 3. One example shown here is a switch SWI consisting of a bipolar transistor or N10S transistor.
~swg and 124816: 8 composed of capacitors CP1 to CP8 weighted to 32: 64: 128
This is BIT's PCA12. Switch S field input “H”
It is assumed that the switch SW closes when . switch SW
】 ~ PCA total capacity H based on SW8 manual data
(5 can take on 256 values from 0 to 255XCPl, and its increasing tendency can be changed by changing the weighting distribution.

FIG. 4 shows an example of the configuration of another PCA.

In this case, the CPC does not have a SW, and the capacitor C
Switches SW+ to SW4 are provided for P1 to CP4, and capacitors CPI to CP4 are each 0.5 pF,
Assume that the values are 1 pF, 2 pF, and 4 pF.

In this way, by switching the switches SW1 to SW4, the total capacitance value becomes 1. From OpF to 17.5 pF, 16 gradations can be obtained in 0.5 pF steps.

Since the approximate range of variations in the IC built-in capacitance is known and the capacitance can be varied to cover this range, the configuration shown in FIG. 4 is more useful.

In this case, it is possible to correct manufacturing variations in the time constant of ±25% with respect to 149F, which is the center of the design.

Next, using FIG. 5, the initial setting of the circuit shown in FIG. 1 at power-on, etc. will be explained.

Before that, with conventional time constant adjustment circuits, users had to start the adjustment from O every time they turned on a television receiver, and wait until it converged in order to obtain a good setting. By doing so, this time can be significantly shortened.

In FIG. 5, in addition to the up/down counter 11 of FIG. 1, a power-on detection circuit 13 and a BUS1/F (interface) circuit 14 are provided. BUS I/F
The circuit 14 is built into the IC and is connected to the external B via the bottle.
Connect to US line.

BUS is now! If it is 2CBUS, two lines, a data line and a clock line, are required, and the IC bin may also have two pins.

For example, suppose that in the manufacturing process of a television receiver, the television set is turned on and the time constant adjustment circuit shown in FIG. 5 is operated. The converged digital data at this time is written into the nonvolatile memory of the BUS controller via the BUS I/F circuit 14. If this data is loaded from the BUS memory and given as the initial value of the counter every time the power is turned on thereafter, the convergence point can be reached in a few cycles of counting operation depending on the operating environment.

For this purpose, a power-on detection circuit 13 is provided to detect that the power of the IC is turned on, and the BUS 1/F circuit 14
The input information is output to the BUS control microcomputer via the . On the microcontroller side, this signal causes the BUS
By transmitting the initial value to the IC via the IC, the convergence time of the time constant adjustment circuit can be shortened each time the power is turned on.

FIG. 6 shows the Sahlen and Key LPF as an example of data diversion to other blocks according to the second invention. Such LPF is used for chroma signal processing of television receivers,
It is widely used for video signal processing and is the most common format. Conventional time constant adjustment circuits have not been able to correct this variation in the time constants (R and C) of the LPF, but the time constant adjustment circuit of the present invention can easily correct this variation without adding a complicated circuit. It can be adjusted.

For example, the main band-limiting capacitor C7 and the feedback capacitor C6 are
The PCA shown in the figure is configured, and the nBIT data output of the up/down counter 11 in FIG.
Enter. In this way, depending on the variation of R, C
The time constant is constant, that is, the cutoff frequency is constant.

In this case, if only the cutoff frequency is desired to be constant, only the band limiting capacitor C7 may be set as PCA. return capacity f
If f1c8 is made into a PCA, it may be necessary to use a MOS switch, but if only the band-limiting capacitor C7 is made into a PCA, it can be realized with a bipolar element. However, if the in-band group delay characteristic is to be made constant, the feedback capacitance C6 should also be changed to PCA.
There is a need to do so.

In addition, the adjustment accuracy of the time constant adjustment circuit depends on the number of bits of the up/down counter 11, or in a circuit that diverts data as shown in FIG. 6, it is necessary to use all the bits of the up/down counter 11. There is no. There is no problem in using only the upper 4 bits of the n bits of the up/down counter 11 in a circuit where the adjustment accuracy can be lowered. In addition, the capacitance accuracy of the PCA of the circuit that fully diverts data from n bits is poor, and even if an inversion phenomenon occurs in which the capacitance value decreases even though the capacitance value data increases, the original The number of bits of the diversion circuit can be determined easily as necessary, since the data will not be corrupted, but will simply result in an adjustment error in the circuit.

FIG. 7 shows an example in which the present invention is applied to another integrating circuit. The integrating circuit shown in FIG. 7 is used as a CO for reproducing color subcarriers and a vertical synchronization separation circuit. Transistor Q2. Q3 and resistors R3 and R4 transmit the signal current after battery replacement to transistor Q4. It is made single-ended by the current mirror circuit of Q5 and output to the integral capacitor C8 and buffer transistor Q6. It is fed back from the emitter of transistor Q6 to the base of transistor Q3, forming an operational amplifier type integrating circuit. The time constant in this case is approximately determined by R3, R4 and C8.

It was previously impossible to adjust the time constant of such a circuit, or the time constant adjustment circuit of the present invention can be used to adjust the integral capacitance C.
All you need to do is convert 8 to PCA. When this time constant becomes constant, the variation in input/output gain becomes smaller, so the chroma section can reduce the variation in the VCO oscillation frequency, and the slew rate becomes stable for pulse input, so the vertical synchronization input/output It is possible to reduce the time difference variation.

Note that the time constant detection means 4 in FIG.
It does not have to be, but anything that can be determined as the product or ratio of capacitance and resistance may be used. It is also possible to use the same circuit as another circuit such as an AGC circuit. Further, the BUS in FIG. 5 has been explained using a 12CBUS for simplicity, but it may be another BUS system.

Applications of this invention to other circuits are not limited to those described above.
Regarding the video signal processing section of a television receiver,
Users are interested in, for example, the horizontal resolution of the video signal system, the degree of image quality correction, the color field saturation of the chroma signal system, the fading time of seven colors, the fading performance in weak electric field areas, and the horizontal/vertical synchronization signal system. There are variations between cents due to screen position, weak electric field synchronization performance, and the overall time difference between the video signal and chroma signal. In particular, the time difference between the video signal and the chroma signal results in blurring of brightness and color on the screen. I
It is virtually impossible to adjust the delay time of the delay line that delays the luminance signal due to the variation in the time constant of I.
It is necessary to suppress variations in C as much as possible. For this purpose,
It is necessary to suppress variations in group delay time that occur in filters, and by using the time constant adjustment circuit of the present invention, extremely good characteristics can be obtained.

"Effects of the Invention As described above, according to the time constant adjustment circuit of the present invention, the time constant adjustment information is versatile, the time constant of the entire IC can be adjusted, and the variation in characteristics of the set can be extremely reduced. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of FIG. 1, and FIGS. 3 and 4 respectively show the programmable capacitor array of FIG. A circuit diagram showing a specific example, Fig. 5 is a system diagram showing the initial setting of Fig. 1, Figs. 6 and 7 are circuit diagrams showing examples to which this invention is applied, and Fig. 8 is a conventional time constant adjustment. A circuit diagram showing the circuit, FIG. 9 is a timing chart diagram for explaining the operation of FIG. 8. 5...Charge/discharge circuit IC0nt...Charge/discharge current source 6...Sample hold circuit C4...Capacitor 7.8/Comparator 1] Up/down counter 12/PCA

Claims (5)

[Claims] (1) a detection means for detecting the product or ratio of resistance (current) and capacitance; and a first conversion means for determining whether the output of the detection means is within a first threshold value and converting it into a pulse; ,
a second conversion means that determines which of the second threshold values the output of the detection means is at and converts it into pulses, and counts and holds the pulses output from the first and second conversion means. A time constant adjustment circuit comprising: a counter; and a control means for controlling at least one of the resistance (current) and the capacitance of the detection means based on the output of the counter. (2) The time constant adjustment circuit according to claim 1, wherein the detection means is realized by a digital-to-analog converter or a programmable capacitor array, and is controlled by a control means. (3) The detection means is realized by a charging/discharging circuit that has a first timing for charging the capacitor and a second timing for discharging the capacitor, performs charging/discharging operations at predetermined intervals, and obtains a trapezoidal charging/discharging waveform. The time constant adjustment circuit according to claim 1, characterized in that: (4) The time constant setting means of another circuit equipped with a time constant circuit is realized by a digital-to-analog converter or a programmable capacitor array, and the output data of the counter is used not only for the detection means but also for setting the time constant of the other circuit. 2. The time constant adjusting circuit according to claim 1, wherein the time constant is also supplied to the means for adjusting the time constant. (5) Equipped with a BUS system interface circuit,
2. The time constant adjustment circuit according to claim 1, wherein the value of the counter is output and stored via a BUS line, and read as necessary, such as when power is turned on.