JPH08274595A - Voltage-controlled oscillator circuit - Google Patents

Abstract

PURPOSE: To suppress the dispersion of a clock signal period by providing a pulse width adjustment circuit and keeping the charging rate of a capacitor in a clock generation circuit part constant by taking into account the response time of a voltage comparator and a control circuit. CONSTITUTION: The clock generation circuit part 30 is controlled by switching circuits SW1 , SW2 so as to repeat the charge/discharge of capacitors C1, C2 alternately, and the charge/discharge waveforms of the capacitors C1, C2 are made into pulses by a threshold value in accordance with a control voltage by voltage comparators 13, 14. The control circuit controls the operation of the switching circuits SW1 , SW2 based on a pulsated signal, and also, generates a clock signal whose pulse duty is controlled. Also, the pulse width adjusting circuit 25 performs such control to keep the charging rate of the capacitors C1, C2 of the circuit part 30 constant by taking into account the response time of the comparators 13, 14 and a flip-flop 15. Therefore, since the circuit 25 is inserted between a timing control circuit 21 and a charge switching circuit SW 31, the dispersion is suppressed by adjusting pulse width.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator circuit (VCO circuit) provided in an LSI (Large Scale Semiconductor Integrated Circuit), and more particularly to controlling a charging speed in a clock generation circuit using a charge / discharge operation of a capacitor. Bias generation circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a VC provided in a conventional LSI.
An example of an O circuit is shown. The VCO circuit has a clock generation circuit section 30 and a bias generation circuit section 31.

In the clock generation circuit section 30, the first capacitor C1 and the second capacitor C2 have the same capacitance value, and one ends thereof are connected to the ground potential (Vss) node.

The first constant current source circuit 9 is provided for flowing a current through the first capacitor C1 and the second capacitor C2, and one end thereof is connected to the power supply potential Vcc node.

The first switching circuit SW1 comprises a PMOS transistor 7 and an NMOS transistor 8 connected to the other end (charge / discharge node) of the first capacitor,
A second switch which is controlled by the first switching control signal and selectively connects the charge / discharge node of the first capacitor C1 to the first constant current source circuit 9 or the ground potential Vss. It becomes a state.

The second switching circuit SW2 is connected to the other end (charging / discharging node) of the second capacitor C2 and is controlled by the second switching control signal.
0 and an NMOS transistor 11 are placed in a first switch state in which the charge / discharge node of the second capacitor C2 is connected to the first constant current source circuit 9 or in a second switch state in which it is selectively connected to the ground potential Vss. Become.

The charge / discharge node of the first capacitor C1 is connected to the positive phase input terminal (+) of the first voltage comparison circuit 13, and the charge / discharge node of the second capacitor C2 is It is connected to the positive phase input terminal (+) of the second voltage comparison circuit 14.

A control voltage Vcont is applied as a comparison reference voltage to the inverting input terminal (-) of the first voltage comparing circuit 13 and the inverting input terminal (-) of the second voltage comparing circuit 14.

The output of the first voltage comparison circuit 13 and the output of the second voltage comparison circuit 14 are set correspondingly.
It is supplied to the set input terminal S and the reset input terminal R of the reset type flip-flop circuit 15. Then, the complementary outputs (set output Q, reset output / Q) of the flip-flop circuit 15 are respectively supplied as the first switching control signal and the second switching control signal.

The operation of the clock generating circuit section having the above configuration is as follows.
The circuit connection to the two capacitors is controlled by the control circuit, so that the two capacitors are alternately charged,
The operation (oscillation) of repeating discharge is performed, and a pulse duty-controlled clock signal is generated by pulsing the charge / discharge waveform of this capacitor with a threshold value according to the control voltage Vcont.

Next, the operation of the clock generating circuit section will be described in detail with reference to the waveform chart shown in FIG. Now, the set output Q of the flip-flop circuit 15,
The reset output / Q goes to "L" and "H" levels correspondingly, and the first switching circuit SW1 / second switching circuit SW2 correspondingly goes to, for example, the first switch state / second switch state. Shall be controlled.

When the second switching circuit SW2 is controlled to the second switch state, the second capacitor C2 is immediately discharged, and the voltage Vb at the charge / discharge node is the control voltage Vcont.
It becomes lower, and the output of the second voltage comparison circuit 14 becomes “L”.
Return to level.

On the other hand, the first switching circuit SW1
Is controlled to the first switch state, the first capacitor C1 starts to be charged, and the voltage Va at its charge / discharge node gradually increases. This voltage Va is the control voltage Vco
When nt is exceeded, the output of the first voltage comparison circuit 13 is "L".
The level is inverted to the "H" level.

The flip-flop circuit 15 outputs a set output Q and a reset output / Q when the output of the first voltage comparison circuit 13 and the output of the second voltage comparison circuit 14 are both at "L" level. Although the level is maintained as it is, the set output Q and the reset output / Q correspond to each other in response to the change of the output of the first voltage comparison circuit 13 from the “L” level to the “H” level as described above. And then "H",
Inverts to "L" level.

As a result, the first switching circuit SW1 / second
The switching circuit SW2 is controlled to a switch state opposite to that before, that is, corresponding to the second switch state / first switch state.

Then, this time, the first capacitor C1 is immediately discharged and the second capacitor C2 starts to be charged. Then, the voltage Va at the charge / discharge node of the first capacitor C1 becomes lower than the control voltage Vcont, and the output of the first voltage comparison circuit 13 returns to the “L” level.

When the voltage Vb at the charge / discharge node of the second capacitor C2 exceeds the control voltage Vcont, the second voltage
The output of the voltage comparison circuit 14 is inverted from "L" level to "H" level. In response to this change, the set output Q and the reset output / Q of the flip-flop circuit 15 are respectively inverted to "L" and "H" levels.

As a result, the first switching circuit SW1 / second
The switching circuit SW2 of corresponds to the first switch state /
Controlled to the second switch state, the second capacitor C2
Immediately discharges and the first capacitor C1 begins to charge again.

By repeating the above-described operation, the two capacitors C1 and C2 having the same capacitance value are alternately charged and discharged (oscillation), and the charging and discharging waveforms of the capacitors C1 and C2 are pulsed. As a result, the clock signal CK (VCO output) is obtained as the reset output / Q of the flip-flop circuit 15.

Oscillation frequency fos of the clock generating circuit section
c is fosc = 1 / 2T (1), where T is the time required to charge the capacitor C1 or C2 from the start of charging to the control voltage Vcont.

In other words, the cycle of the clock signal generated from the clock generation circuit section is the capacitor C1 or C2.
Is twice the time it takes to charge before reaching a predetermined threshold. On the other hand, the bias generation circuit section 31 has a third capacitor C3 having the same capacitance value as the first capacitor C1 and the second capacitor C2, and a second capacitor having the same characteristics as the first constant current source circuit 9. Constant current source circuit 20, a third switching circuit having the same characteristics as the first switching circuit SW1 and the second switching circuit SW2, a timing control circuit 21, a sample hold circuit 22, and the first switching circuit. It includes a third voltage comparison circuit 23 having the same characteristics as the voltage comparison circuit 13 and the second voltage comparison circuit 14, and a reference voltage generation circuit 24.

The timing control circuit 21 is supplied with a reference clock signal and outputs various timing signals whose timing is controlled by the reference clock signal.
The third switching circuit includes a charge switch circuit SW31 and a discharge switch circuit SW32. The charge switch circuit SW31 includes a PMOS transistor 2 connected between the output node of the second constant current source circuit 20 and the other end (charge / discharge node) of the third capacitor C3, and the timing control is performed. Switch control is performed by the control signal supplied from the circuit 21, and the charge / discharge node of the third capacitor C3 is selectively connected to the second constant current source circuit 20.

Further, the discharge switch circuit SW32 is
The third capacitor C3 includes an NMOS transistor 3 connected between a charge / discharge node and a ground potential node, and is switch-controlled by a control signal supplied from the timing control circuit 21 to charge the third capacitor C3. The discharge node is selectively connected to the ground potential Vss.

The sample-hold circuit 22 samples and holds the potential of the charge / discharge node of the third capacitor C3 at the timing of the control signal supplied from the timing control circuit 21, and depending on the sampling timing. Hold voltage is controlled. In this case, an example of the sample-hold circuit 23 has an array of a plurality of sample-hold capacitors whose sample-hold operation is controlled corresponding to each timing of a plurality of control signals.

In the third voltage comparison circuit 23, the output voltage of the sample hold circuit 22 is a positive phase input terminal (+).
A predetermined reference voltage Vref generated from the reference voltage generating circuit 24 is input to the inverting input terminal (-), and the first constant current source circuit 9 and the second constant current source circuit are output by comparison output. 20 in common.

The operation of the bias generating circuit section having the above configuration is as follows.
The charge switch circuit SW31, the discharge switch circuit SW32, and the sample hold circuit 22 are controlled by the timing signal whose timing is controlled by the reference clock signal supplied from the outside to the third voltage comparison circuit 23. Is controlled to be constant, and the first constant current source circuit 9 and the second constant current source circuit 20 are commonly controlled by this comparison output. Thereby, the charging rates in the bias generating circuit section 31 and the clock generating circuit 30 are respectively controlled,
Compensate for characteristic variations due to process variations.

By the way, the cycle (output wavelength) of the clock signal generated from the clock generation circuit section 30 of the VCO circuit shown in FIG. 4 is, as described above, the first capacitor C1.
Alternatively, it is twice as long as the second capacitor C2 is charged until it reaches a predetermined threshold value.

In this case, as shown in FIG. 2, when the response times of the voltage comparison circuits 13 and 14 and the flip-flop circuit 15 are also taken into consideration, the actual clock signal period is the charging time of the capacitors C1 and C2 and the response time. It is twice the sum of time.

In consideration of this point, the bias generation circuit section 31
Characteristic compensation should be performed (addition of the response time of the voltage comparison circuits 13 and 14 and the flip-flop circuit 15 to the charging time of the third capacitor C3).
In the frequency range where the VCO circuit as described above is used, the response time is shorter than the charging time of the capacitors C1 and C2, and therefore the correction is not performed.

However, when the VCO circuit as described above is used in a relatively high frequency region, the response time (delay time) of the voltage comparison circuits 13 and 14 and the flip-flop circuit 15 as described above is ignored. However, this causes a problem that the clock signal period greatly varies due to an error due to variation in response time due to variation in LSI manufacturing process.

[0031]

As described above, the VCO circuit provided in the conventional LSI is used as a voltage comparison circuit or a flip-flop circuit in the clock generation circuit section when it is used in a relatively high frequency region. There has been a problem that the clock signal period greatly varies due to the response time.

The present invention has been made to solve the above problems, and even when used in a relatively high frequency range,
An object of the present invention is to provide a voltage controlled oscillator circuit capable of suppressing variations in clock signal cycle due to the response time of a voltage comparison circuit or a flip-flop circuit in a clock generation circuit section and obtaining good characteristics in a relatively wide frequency range. To do.

[0033]

The VCO circuit of the present invention comprises:
The switching circuit is provided on the LSI chip and is controlled by the switching circuit so that the first capacitor and the second capacitor are alternately charged and discharged repeatedly. The charge / discharge waveforms of the two capacitors are controlled by the voltage comparison circuit. A clock that is pulsed with a threshold value according to the control circuit, controls the switching operation of the charging / discharging operation by the switching circuit based on the pulsed signal by the control circuit, and generates a clock signal whose pulse duty is controlled according to the control voltage. The bias generating circuit section is also provided on the LSI chip and controls the charging speed of the capacitor of the clock generating circuit section at a constant rate based on a reference clock signal supplied from the outside. The generation circuit section determines the response time of the voltage comparison circuit and the control circuit in the clock generation circuit section. Characterized by including a pulse width adjusting circuit for controlling the taste to constant charging rate of the capacitor of the clock generating circuit portion.

[0034]

In the clock generation circuit section, the connection between the two capacitors and the first constant current source circuit or the ground potential is controlled by the switching circuit, so that the two capacitors alternately charge and discharge (oscillation). ) Is done, and above 2
The charge and discharge waveforms of the two capacitors are pulsed by the voltage comparison circuit at a threshold value according to the control voltage, and the control circuit controls the switching operation of the charge and discharge operation by the switching circuit and the pulse duty based on this pulsed signal. Generate a clock signal that has been processed.

In the bias generation circuit section, the connection between one capacitor and the second constant current source circuit is controlled by the charge switch circuit, the connection between the capacitor and the ground potential is controlled by the discharge switch circuit, and the capacitor The terminal voltage is sampled and held by the sample and hold circuit, and then compared with the reference voltage by the voltage comparison circuit, and the second constant current source circuit and the first constant current source of the clock generation circuit section are obtained by the comparison output of the voltage comparison circuit. Control the circuits in common.

In this case, the charge switch circuit, the discharge switch circuit, and the sample hold circuit are controlled by the timing signal whose timing is controlled by the reference clock signal supplied from the outside, so that the comparison output of the voltage comparison circuit becomes constant. Since it is controlled, the charging speed of the capacitor in the bias generation circuit section and the clock generation circuit is controlled, and the characteristic variation due to the process variation is compensated.

The present invention has a pulse width adjusting circuit for widening the pulse width of the timing signal supplied to the charging switch circuit by the response time of the voltage comparing circuit and the control circuit in the clock generating circuit section. Even when used in a relatively high frequency region, it is possible to suppress variations in the clock signal cycle (compensate for variations in characteristics) due to variations in response time of the voltage comparison circuit and the flip-flop circuit in the clock generation circuit section. Therefore, good characteristics can be obtained in a relatively wide frequency range.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the VCO circuit of the present invention. The VCO circuit of FIG. 1 is different from the VCO circuit described with reference to FIG.
1a is partly different and the others are the same, and therefore the same reference numerals as in FIG. 4 are given.

That is, the clock generating circuit unit 30 is, like the clock generating circuit unit 30 in FIG. 4, configured by a switching circuit so that the first capacitor and the second capacitor alternately perform charging and discharging operations. The charging / discharging waveforms of the two capacitors are controlled by the voltage comparison circuit to be pulsed at a threshold value according to the control voltage, and the control circuit controls the switching operation of the charging / discharging operation by the switching circuit based on the pulsed signal. At the same time, a clock signal whose pulse duty is controlled according to the control voltage is generated. Further, the bias generation circuit unit 31a controls the charging speed of the capacitor of the clock generation circuit unit to be constant based on a reference clock signal supplied from the outside. In consideration of the response times of the circuits 13 and 14 and the flip-flop circuit 15, the capacitor C of the clock generation circuit unit 30.
It has a pulse width adjusting circuit 25 for controlling the charging speed of C1 and C2 to be constant. That is, the bias generation circuit section 31a
In comparison with the bias generation circuit section 31 in FIG. 3, a pulse width adjustment circuit 25 is inserted between the timing control circuit 21 and the charge switch circuit SW31. The pulse width adjustment circuit 25 adjusts the pulse width. A first delay gate circuit 28 and a second delay gate circuit 29 having a delay time corresponding to the delay time of the timing signal associated with the above, respectively, correspond to between the timing control circuit 21 and the discharge switch circuit SW32, and the timing control circuit. The difference is that it is inserted between 21 and the sample and hold circuit 22.

In the clock generation circuit section 30, the first capacitor C1 and the second capacitor C2 are included.
Have the same capacitance value and one end is connected to the ground potential (Vss) node.

The first constant current source circuit 9 is provided for flowing a current through the first capacitor C1 and the second capacitor C2, and one end thereof is connected to the power supply potential Vcc node.

The first switching circuit SW1 is connected to the other end (charging / discharging node) of the first capacitor and is controlled by the first switching control signal so that the charging / discharging node of the first capacitor C1 becomes the first switching circuit. Of the constant current source circuit 9 or the second switch state of selectively connecting to the ground potential Vss.

The second switching circuit SW2 is connected to the other end (charging / discharging node) of the second capacitor C2 and is controlled by a second switching control signal so that the charging / discharging node of the second capacitor C2 is connected to the second switching circuit SW2. The first switch state is connected to the first constant current source circuit 9 or the second switch state is selectively connected to the ground potential Vss.

The charge / discharge node of the first capacitor C1 is connected to the positive phase input terminal (+) of the first voltage comparison circuit 13, and the charge / discharge node of the second capacitor C2 is It is connected to the positive phase input terminal (+) of the second voltage comparison circuit 14.

The control voltage Vcont is applied as a comparison reference voltage to the inverting input terminal (-) of the first voltage comparing circuit 13 and the inverting input terminal (-) of the second voltage comparing circuit 14.

The output of the first voltage comparison circuit 13 and the output of the second voltage comparison circuit 14 are set correspondingly.
It is supplied to the set input terminal S and the reset input terminal R of the reset type flip-flop circuit 15. Then, the complementary outputs (set output Q, reset output / Q) of the flip-flop circuit 15 are respectively supplied as the first switching control signal and the second switching control signal.

On the other hand, the bias generation circuit section 31a has
The first capacitor C1 and the second capacitor C2
A third capacitor C3 having the same capacitance value, a second constant current source circuit 20 having the same characteristics as the first constant current source circuit 9, the first switching circuit SW1 and the second switching circuit SW2. A third switching circuit having the same characteristics as the above, a timing control circuit 21, a sample hold circuit 22, the first voltage comparison circuit 13 and the second voltage comparison circuit 1
The third voltage comparison circuit 23 having the same characteristics as those of No. 4 and the reference voltage generation circuit 24 are provided.

The timing control circuit 21 is supplied with the reference clock signal and outputs various timing signals whose timing is controlled by the reference clock signal.
The third switching circuit includes a charge switch circuit SW31 and a discharge switch circuit SW32. The charge switch circuit SW31 includes a PMOS transistor 2 connected between the output node of the second constant current source circuit 20 and the other end (charge / discharge node) of the third capacitor C3, and the timing control is performed. Switch control is performed by the control signal supplied from the circuit 21, and the charge / discharge node of the third capacitor C3 is selectively connected to the second constant current source circuit 20.

Further, the discharge switch circuit SW32 is
The third capacitor C3 includes an NMOS transistor 3 connected between a charge / discharge node and a ground potential node, and is switch-controlled by a control signal supplied from the timing control circuit 21 to charge the third capacitor C3. The discharge node is selectively connected to the ground potential Vss.

The sample-hold circuit 22 samples and holds the potential of the charge / discharge node of the third capacitor C3 at the timing of the control signal supplied from the timing control circuit 21, and holds the sampling timing. The hold voltage is controlled accordingly. In this case, as an example of the sample hold circuit 22,
It has an array of a plurality of sample and hold capacitors whose sample and hold operations are controlled correspondingly to respective timings of a plurality of control signals.

The third voltage comparison circuit 23 has the first voltage
Has the same characteristics as the voltage comparison circuit 13 and the second voltage comparison circuit 14, and the output voltage of the sample and hold circuit 22 is input to the positive phase input terminal (+) and is generated from the reference voltage generation circuit 24. Is input to the inverting input terminal (-), and the first constant current source circuit 9 and the second constant current source circuit 20 are commonly controlled by the comparison output.

The pulse width adjusting circuit 25 determines the pulse width of the timing signal supplied from the timing control circuit 21 to the charging switch circuit SW31 in the voltage comparing circuits 13 and 14 and the flip-flop circuit 15 in the clock generating circuit section 30. The adjustment is made so as to be wider by the response time.

The first delay gate circuit 28 is inserted between the timing control circuit 21 and the discharge switch circuit SW32, and corresponds to the delay time of the timing signal accompanying the pulse width adjustment by the pulse width adjusting circuit 25. Has a delay time.

The second delay gate circuit 29 is inserted between the timing control circuit 21 and the sample hold circuit 22, and corresponds to the delay time of the timing signal accompanying the pulse width adjustment by the pulse width adjusting circuit 25. Has a delay time.

The pulse width adjusting circuit 25 includes the voltage comparing circuits 13 and 1 in the clock generating circuit section 30.
4 and the delay circuit 26 having a delay time corresponding to the response time of the control circuit 15, the output signal of the delay circuit 26, the timing control circuit 21 to the charging switch circuit SW31.
And an OR gate circuit 27 that takes the logical sum of the output signal for supplying to the charge switch circuit SW31.

FIGS. 3A to 3E show different specific examples of the delay circuit 26 in the pulse width adjusting circuit 25 in FIG. The delay circuit shown in FIG. 3A includes a voltage comparison circuit 41 to which the input signal voltage from the timing control circuit 21 and the reference voltage Vref are input, and an AND gate to which the output signal of this voltage comparison circuit and the Vcc voltage are input. And a circuit 42.

The delay circuit shown in FIG. 3B is composed of an AND gate circuit 42 to which the input signal from the timing control circuit 21 and the Vcc voltage are input. The delay circuit shown in FIG. 3C includes a voltage comparison circuit 41 to which the input signal voltage from the timing control circuit 21 and the reference voltage Vref are input.

The delay circuit shown in FIG. 3D has a NAND gate circuit 43 to which the input signal from the timing control circuit 21 and the Vcc voltage are input, and a NAND gate circuit 44 to which the output signal of the NAND gate circuit and the Vcc voltage are input. Consists of.

The delay circuit shown in FIG. 3 (e) is a NAND gate circuit 43 to which the input signal from the timing control circuit 21 and the Vcc voltage are input, and a NAND gate circuit 44 to which the output signal of this NAND gate circuit and the Vcc voltage are input. And a NAND gate circuit 45 to which the output signal of the NAND gate circuit and the Vcc voltage are input.

FIG. 2 shows an operation example of the clock generation circuit section shown in FIG. In the VCO circuit of the above embodiment, the clock generation circuit unit 30 has two capacitors C1 and C2.
The connection between the and the first constant current source circuit 10 or the ground potential Vss is controlled by the switching circuits SW1 and SW2, so that the two capacitors alternately perform charging and discharging operations (oscillation). The charge / discharge waveforms of the two capacitors are pulsed by the voltage comparison circuits 13 and 14 at a threshold value according to the control voltage Vcont, and the control circuit 15 switches the charge / discharge operation by the switching circuits SW1 and SW2 based on the pulsed signal. A clock signal whose pulse duty is controlled while controlling its operation is generated.

In the bias generation circuit section 31a, the connection between one capacitor C3 and the second constant current source circuit 20 is controlled by the charging switch circuit SW31, and the capacitor C3
3 is connected to the ground potential Vss by the discharge switch circuit SW32.
The voltage of the terminal of the capacitor C3 is sampled and held by the sample and hold circuit 22, and then compared with the reference voltage Vref by the voltage comparison circuit 23.
The second constant current source circuit 20 and the first constant current source circuit 10 of the clock generation circuit section 30 are commonly controlled by the comparison output of the voltage comparison circuit 23.

In this case, the charge switch circuit SW31 and the discharge switch circuit S are controlled by the timing signal whose timing is controlled by the reference clock signal supplied from the outside.
By controlling W32 and the sample and hold circuit 22, the comparison output of the voltage comparison circuit 23 is controlled to be constant, so that the charging speed of the capacitors in the bias generation circuit section 31a and the clock generation circuit 30 is controlled, and the process Compensate for fluctuations in characteristics due to variations.

In the VCO circuit of the above embodiment, the pulse width of the timing signal supplied to the charging switch circuit SW31 is widened by the response time of the voltage comparison circuits 13 and 14 and the control circuit 15 in the clock generation circuit section 30. Since it has a pulse width adjustment circuit that suppresses fluctuations in the clock signal cycle due to fluctuations in the response time of the voltage comparison circuit and the flip-flop circuit in the clock generation circuit section even when used in a relatively high frequency region (characteristic fluctuations) Can be compensated). Therefore, good characteristics can be obtained in a relatively wide frequency range.

[0064]

As described above, according to the VCO circuit of the present invention, even when the VCO circuit is used in a relatively high frequency range, the clock signal cycle caused by the response time of the voltage comparison circuit and the control circuit in the clock generation circuit section is reduced. Variation can be suppressed, and good characteristics can be obtained in a relatively wide frequency range.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a VCO circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation example of the clock generation circuit unit in FIG.

3 is a circuit diagram showing a different specific example of a delay circuit in the pulse width adjustment circuit in FIG.

FIG. 4 is a circuit diagram showing an example of a conventional VCO circuit.

[Explanation of symbols]

10 ... 1st constant current source circuit, 13 ... 1st voltage comparison circuit, 14 ... 2nd voltage comparison circuit, 15 ... Flip-flop circuit, 20 ... 2nd constant current source circuit, 21 ... Timing control circuit, 22 ... Sample hold circuit, 23 ... Third voltage comparison circuit, 24 ... Reference voltage generation circuit, 25 ... Pulse width adjustment circuit, 26 ... Delay circuit, 27 ... OR gate circuit,
28 ... 1st delay gate circuit, 29 ... 2nd delay gate circuit, 30 ... Clock generation circuit part, 31a ... Bias generation circuit part, C1 ... 1st capacitor, C2 ... 2nd capacitor, C3 ... 3rd , SW1 ... First switching circuit, SW2 ... Second switching circuit, SW31 ... Charging switch circuit, SW32 ... Discharging switch circuit.

Claims (4)

[Claims] 1. A switching circuit provided on an LSI chip, controlled by a switching circuit so that a first capacitor and a second capacitor alternately repeat charging and discharging, and the charge and discharge waveforms of the two capacitors are voltage. A clock which is pulsed by a threshold value according to a control voltage by a comparison circuit, controls the switching operation of the charging / discharging operation by the switching circuit based on the pulsed signal by the control circuit, and has a pulse duty controlled according to the control voltage. A clock generation circuit unit for generating a signal and a bias generation circuit unit provided on the LSI chip for controlling the charging speed of the capacitor of the clock generation circuit unit to be constant based on a reference clock signal REF supplied from the outside. The bias generating circuit section includes a voltage comparing circuit and a control circuit in the clock generating circuit section. And a pulse width adjusting circuit for controlling the charging speed of the capacitor of the clock generating circuit unit to be constant in consideration of the response time of the control circuit. 2. The voltage controlled oscillator circuit according to claim 1, wherein the clock generation circuit section includes a first capacitor and a second capacitor each having one end connected to a ground potential, the first capacitor, and A first constant current source circuit provided for setting a current flowing through the second capacitor; and a first constant current source circuit connected to the other end of the first capacitor,
A first switching circuit which is controlled by the switching control signal of (1) to selectively connect the other end of the first capacitor to the first constant current source circuit or the ground potential, and the other end of the second capacitor. A second switching circuit connected to the first constant current source circuit or the ground potential, the second switching circuit being controlled by a second switching control signal and selectively connecting the other end of the second capacitor to the first constant current source circuit or the ground potential. The first capacitor and the second capacitor are alternately connected to the first constant current source circuit, and the first capacitor
And a control circuit that controls the first switching circuit and the second switching circuit each time the charging voltage of the capacitor or the charging voltage of the second capacitor reaches a predetermined voltage. . 3. The voltage controlled oscillator circuit according to claim 2, wherein the control circuit includes a reference voltage generating circuit for generating a predetermined comparison reference voltage, a voltage at the other end of the first capacitor, and the reference voltage generating circuit. A comparison reference voltage generated by the reference voltage generation circuit and a first voltage comparison circuit that receives the comparison reference voltage generated by the circuit and compares the voltages of both inputs with the voltage of the other end of the second capacitor. And a second voltage comparison circuit for inputting a voltage and comparing the voltages of both inputs, and an output of the first voltage comparison circuit and an output of the second voltage comparison circuit respectively correspond to a set input terminal and a reset input. And a flip-flop circuit which supplies complementary outputs to the terminals as the first switching control signal and the second switching control signal. 4. The voltage controlled oscillator circuit according to claim 1, wherein the bias generation circuit section includes a third capacitor having a capacitance value equal to that of the first capacitor and the second capacitor, and the first constant current. A second constant current source circuit having the same characteristics as the source circuit; a timing control circuit which is supplied with a reference clock signal and outputs various timing signals whose timing is controlled by the reference clock signal; and the second constant circuit. A PMO connected between the output node of the current source circuit and the other end (charge / discharge node) of the third capacitor.
A charge switch circuit which is composed of an S-transistor, is switch-controlled by a control signal supplied from the timing control circuit, and selectively connects the charge / discharge node of the third capacitor to the second constant current source circuit; Connected between the charging / discharging node of the capacitor and the ground potential node
A third MOS transistor, which is switch-controlled by a control signal supplied from the timing control circuit;
And a discharge switch circuit for selectively connecting the charge / discharge node of the capacitor to the ground potential Vss, and the potential of the charge / discharge node of the third capacitor is sampled and held at the timing of the control signal supplied from the timing control circuit. Has the same characteristics as the sample-hold circuit and the first voltage comparison circuit and the second voltage comparison circuit, the output voltage of the sample-hold circuit is input to the positive phase input terminal, and the predetermined control voltage Vcont is inverted. The voltage is supplied to the charge switch circuit from a third voltage comparison circuit that inputs the signal to an input terminal and commonly controls the first constant current source circuit and the second constant current source circuit by a comparison output. Pulse width adjustment for narrowing the pulse width of the timing signal by the response time of the voltage comparison circuit or control circuit in the clock generation circuit section A first delay gate circuit inserted between the timing control circuit and the discharge switch circuit, the first delay gate circuit having a delay time corresponding to the delay time of the timing signal accompanying the pulse width adjustment by the pulse width adjustment circuit; A second delay gate circuit inserted between the timing control circuit and the sample hold circuit, the second delay gate circuit having a delay time corresponding to the delay time of the timing signal associated with the pulse width adjustment by the pulse width adjustment circuit. A voltage controlled oscillator circuit.