JPH1117504A - Comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily secure comparison accuracy by using a 1st switch which causes a short circuit between the input and output sides of a CMOS inverter and a 2nd switch which secures connection of the refresh voltage that is common to the inputs of all capacitances for the capacitive coupling. SOLUTION: When a 1st refresh switch SW1 is closed, the input/output of a CMOS inverter I1 is set at its threshold voltage level. The refresh voltage Vref is set equal to the threshold voltage level and at 1/2 normal power voltage level. The voltage inputted to the capacitors C1 to Cn are set at V1 to Vn and the switches SWin and SW21 to SW2n are connected to the voltage Vref when the switch SW1 is closed. Thus, the electric charge is accumulated to the capacitive coupling and the parasitic capacitance Cp. Then the switch SW1 is opened with switches SWin and SW21 to SW2n connected to the voltage Vin and V1 to Vn respectively, and a comparative operation is carried out. Thus, the measurement value that is never affected by the capacitance Cp and the threshold voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit for comparing an analog input voltage with a predetermined voltage.

[0002]

2. Description of the Related Art Advances in digital technology are largely due to advances in microfabrication technology. However, the amount of capital investment is increasing at an accelerating rate, and analog technology and analog / digital mixed technology are currently attracting attention. Therefore, the applicant has realized high-precision arithmetic using many analog / digital mixed circuits, and has developed a circuit shown in FIG. 2 as a circuit for comparing an analog input voltage with a predetermined voltage.

In FIG. 2, the comparison circuit has a capacitive coupling CC2 in which a plurality of capacitances C21 and C22 are arranged in parallel and their outputs are integrated, and the output is connected to a CMOS inverter I2. When the analog input voltages Vin and Vo are applied to C21 and C22, the input voltage Vb of I2 is as shown in Expression (1).

(Equation 1) The CMOS inverter I1 outputs an output voltage Vout equal to the power supply voltage Vdd when Vb is equal to or lower than the threshold voltage, and inverts the output Vout to the ground voltage when Vb exceeds the threshold voltage. This enables comparison between the voltage Vb and the threshold voltage.

The comparison accuracy of the above-described comparison circuit is affected by the residual charges in the capacitances C21 and C22 and the residual charges of the parasitic capacitances associated therewith, and changes due to variations in the manufacturing of the threshold voltage of I2. For this reason, conventionally, a large amount of simulation and trial work were required to equalize the parasitic capacitance and the threshold voltage.

[0005]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object of the present invention is to provide a comparison circuit which can easily ensure comparison accuracy.

A comparison circuit according to the present invention secures comparison accuracy only by short-circuiting the input and output of a CMOS inverter and connecting a predetermined refresh voltage to the input side of capacitive coupling.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The applicant of the present invention has studied for a long time to ensure the accuracy of comparison, and has studied the significance of error factors. As a result, a correlation between the influence of the parasitic capacitance and the variation in the threshold value of the inverter was found, and a configuration capable of eliminating most error factors was proposed.

FIG. 1 shows a comparison circuit developed on the basis of such knowledge. A plurality of capacitances Cin and C1 to Cn are arranged in parallel, and a capacitive coupling CC1 is formed by integrating the outputs thereof. The total sum of the parasitic capacitance of the whole, the wiring and the gate of the CMOS inverter is indicated by Cp. The output of the capacitive coupling CC1 is connected to the CMOS inverter I1.

The input and output of the CMOS inverter I1 are connected by a first refresh switch SW1, so that these inputs and outputs can be short-circuited as appropriate. An analog input voltage or a refresh voltage Vref is input to the input of each of the capacitances Cin and C1 to Cn via the second refresh switches SWin and SW21 to SW2n, respectively.
Is connected.

When the first refresh switch SW1 is closed, the input / output of the CMOS inverter I1 becomes the threshold voltage Vt of the CMOS inverter. Vref is usually set to be equal to the threshold voltage Vt, but is indicated by a different symbol here. Vt and Vref are equal to the normal power supply voltage Vdd
Is set to の. The analog input voltage input to Cin is Vin, the voltages input to C1 to Cn are V1 to Vn, and when SW1 is closed, the switches SWin,
When SW21 to SW2n are connected to Vref, the following charges Q are accumulated in the capacitive coupling and the parasitic capacitance.

(Equation 2)

When performing the comparison operation, SW1 is opened and SWin and SW21 to SW2n are changed to Vin, V1 to V1.
n. In this comparison operation, the voltage at which the Vb is equal to the threshold voltage Vt is important, and the charge at this time is:

(Equation 3) According to the law of conservation of charge, the charges Q in the equations (2) and (3) are equal. Therefore,

(Equation 4) And rearranging both sides of equation (4) yields equation (5).

(Equation 5)

Equation (5) shows that for a given V1 to Vn, V
When in is input, a condition is shown in which Vb becomes equal to Vt, which is a voltage at which the comparison operation result for Vin is inverted from the power supply voltage to the ground voltage. In equation (5),
The term including the parasitic capacitance Cp and the threshold Vt has been eliminated, and it can be seen that these effects have been completely eliminated.
In addition, Vin when Vb = Vt changes depending on the value of Vref, and therefore, the comparison condition can be easily adjusted only by setting Vref.

Here, Vin is an analog input voltage to be measured, and V1 to Vn are reference voltages for comparison. The comparison condition can be changed by changing one or more of these V1 to Vn.

That is, comparison accuracy can be easily ensured only by adding a refresh switch. Further, Vb
The time point at which = Vt can be set by Ci / Cin, and Vin can be compared with various voltages. Since the influence of these capacitances on Vin is given in the form of the ratio Ci / Cin, the influence of minute errors in each capacitance can be neglected and the comparison accuracy is good. By making Ci / Cin a value of a power of 2, as shown in Expression (6), a result obtained by weighting V1 to Vn with a binary number can be used as a comparison reference.

(Equation 6) It is practically advantageous.

[0015]

The comparison circuit according to the present invention secures the comparison accuracy only by short-circuiting the input and output of the CMOS inverter and connecting a predetermined refresh voltage to the input side of the capacitive coupling. It has an excellent effect that it can be secured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a comparison circuit according to the present invention.

FIG. 2 is a circuit diagram showing a conventional comparison circuit.

[Explanation of symbols]

 C1 to Cn, C21, C22. . . Capacitance CC1, CC2. . . Capacitive coupling Cp. . . Parasitic capacitances I1, I2. . . CMOS inverter Vin, V1 to Vn, Vo. . . Input analog voltage Vout. . . Output voltage Vb. . . Capacitively coupled output voltage. SW1. . . First refresh switches SW21 to SW2n. . . Second refresh switch.

Claims (4)

[Claims] 1. A capacitive coupling in which a plurality of capacitances are connected in parallel and their outputs are integrated, and a CMOS inverter connected to an output of the capacitive coupling is provided, and a weight of an analog input voltage inputted to each of the capacitances is provided. The magnitude relationship between the addition result and the threshold voltage of the CMOS inverter is represented by C
In a comparison circuit for making a determination based on the output of a MOS inverter, a first refresh switch for short-circuiting the input and output of the CMOS inverter is connected to the CMOS inverter,
A comparison circuit, wherein a second refresh switch for connecting a common refresh voltage to inputs of all capacitances in the capacitive coupling is connected. 2. The comparison circuit according to claim 1, wherein the refresh voltage is a half of the power supply voltage. 3. The comparison circuit according to claim 1, wherein the refresh voltage is variable, so that the condition for determining the magnitude relation can be changed. 4. The analog input voltage according to claim 1, wherein the analog input voltage comprises one or more measurement objects and one or more reference voltages, and the one or more reference voltages are variable. Comparison circuit.