JPH09306932A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH09306932A JPH09306932A JP12348896A JP12348896A JPH09306932A JP H09306932 A JPH09306932 A JP H09306932A JP 12348896 A JP12348896 A JP 12348896A JP 12348896 A JP12348896 A JP 12348896A JP H09306932 A JPH09306932 A JP H09306932A
- Authority
- JP
- Japan
- Prior art keywords
- sheet
- back surface
- semiconductor
- ultraviolet
- adhesive sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ガリウムひ素（以
下、ＧａＡｓという）基板を用いた半導体装置の製造方
法に関し、特に薄肉のＧａＡｓ基板の裏面に金メッキ層
を形成した半導体ウェハのダイシングを精度良く行うと
ともに、ダイボンディングを効率的に行うことができる
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a gallium arsenide (hereinafter referred to as GaAs) substrate, and more particularly, to accurately dicing a semiconductor wafer having a gold plating layer formed on the back surface of a thin GaAs substrate. The present invention relates to a method for manufacturing a semiconductor device, which can perform die bonding efficiently.
【０００２】[0002]
【従来の技術】従来、ＧａＡｓ基板の表面に半導体素子
を形成した、いわゆるＧａＡｓデバイスには、一般に１
３０〜１５０μｍ程度の肉厚のＧａＡｓ基板が使用され
ており、この種の半導体ウェハのダイシングは、この裏
面に、例えば１５０ｇ／ｃｍ２程度の粘着強度（粘着
力）を有する粘着シートを貼り付けた状態で、例えばダ
イヤモンドブレード等のＧａＡｓ切削用メタルブレード
を使用して、ＧａＡｓ基板の表面から粘着シートの内部
に達する切削を行うことによって行われていた。2. Description of the Related Art Conventionally, a so-called GaAs device in which a semiconductor element is formed on the surface of a GaAs substrate is generally used.
A GaAs substrate having a thickness of about 30 to 150 μm is used, and a dicing of a semiconductor wafer of this type is performed by attaching an adhesive sheet having an adhesive strength (adhesive force) of about 150 g / cm 2 to the back surface of the semiconductor wafer. Then, for example, a metal blade for GaAs cutting such as a diamond blade is used to perform cutting from the surface of the GaAs substrate to the inside of the adhesive sheet.
【０００３】近年、例えば、携帯電話用の１．５ＧＨｚ
帯で使用される高周波電力増幅用ＦＥＴとして、３０μ
ｍ厚程度の薄肉のＧａＡｓ基板の表面に半導体素子を形
成し、この裏面に２０μｍ程度の金メッキ層を形成した
半導体ウエハが用いられ、半導体素子はより薄型化され
る傾向にある。In recent years, for example, 1.5 GHz for mobile phones
30μ as a high frequency power amplification FET used in the band
A semiconductor wafer is used in which a semiconductor element is formed on the surface of a thin GaAs substrate having a thickness of about m, and a gold plating layer having a thickness of about 20 μm is formed on the back surface of the substrate, and the semiconductor element tends to be thinner.
【０００４】ここに、この種の半導体ウェハのダイシン
グ（フルカット）は、図２に示すように、ＧａＡｓ基板
１の裏面に金メッキ層２を形成した半導体ウェハ３の裏
面に、前記とほぼ同様に、例えば１５０ｇ／ｃｍ２ 程
度の粘着強度を有する粘着シート４を貼り付ける。この
状態で、ダイヤモンドブレード等のＧａＡｓ切削用メタ
ルブレードを使用して、ＧａＡｓ基板１の表面から金メ
ッキ層２を通過して粘着シート４の内部に達する切削を
行う。即ち、格子状に延びるダイシングラインに沿って
粘着シート４の内部に達する切削溝５を形成することに
よって、一般にダイシングが行われている。Here, the dicing (full cut) of this type of semiconductor wafer is performed on the back surface of the semiconductor wafer 3 having the gold plating layer 2 formed on the back surface of the GaAs substrate 1 as shown in FIG. For example, an adhesive sheet 4 having an adhesive strength of about 150 g / cm 2 is attached. In this state, a metal blade for cutting GaAs such as a diamond blade is used to cut the surface of the GaAs substrate 1 through the gold plating layer 2 to reach the inside of the adhesive sheet 4. That is, dicing is generally performed by forming the cutting grooves 5 that reach the inside of the adhesive sheet 4 along the dicing lines extending in a grid pattern.
【０００５】そして、ダイシングによって個々に分離し
た半導体チップのリードフレーム等へのダイボンディン
グは、半導体チップの裏面にＡｕＳｎ材等のハンダ共晶
を用いて接着したり、または銀ペースト材を塗布して接
着した後にこれを硬化させることによって、リードフレ
ーム上に固着することが一般に行われていた。Die bonding of the semiconductor chips individually separated by dicing to a lead frame or the like is performed by bonding the back surface of the semiconductor chip with a solder eutectic such as AuSn material or by applying a silver paste material. It is generally performed to fix the lead frame on the lead frame by hardening the adhesive after the bonding.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来例のように、メタルブレード等を用いてＧａＡｓ基板
の表面から粘着シートの内部に達する切削を行うと、Ｇ
ａＡｓ基板層が薄く金メッキ層が比較的厚くかつ柔らか
いため、これを完全に切断できずに、図２に示すよう
に、切削溝５の底部に残った連絡部６を介して金メッキ
層２同士が互いに連絡してしまうことがある。そして、
このように金メッキ層を完全に切断できないまま半導体
チップの分離を行うと、粘着シートの裏面側から針を突
き上げて持ち上げ、コレットで半導体チップを真空吸着
保持する際に、半導体チップの周縁部に割れや欠けが発
生してしまうことがある。特にこの種の半導体チップ
は、その肉厚が薄く、かつ面積が大きいため、この欠点
が助長されてしまい、歩留りを低下させる等の問題があ
った。However, when cutting is performed from the surface of the GaAs substrate to the inside of the adhesive sheet using a metal blade or the like as in the above-mentioned conventional example, G
Since the aAs substrate layer is thin and the gold plating layer is relatively thick and soft, it cannot be completely cut, and as shown in FIG. 2, the gold plating layers 2 are separated from each other via the connecting portion 6 remaining at the bottom of the cutting groove 5. Sometimes they contact each other. And
When the semiconductor chip is separated without completely cutting the gold plating layer in this way, the needle is pushed up from the back side of the adhesive sheet and lifted up, and when the semiconductor chip is vacuum-sucked and held by the collet, the peripheral edge of the semiconductor chip cracks. It may cause chipping. In particular, this type of semiconductor chip has a problem that the thickness is thin and the area is large, which promotes this defect and reduces the yield.
【０００７】更に、半導体チップのリードフレーム等へ
のダイボンディングの際に、半導体チップを半田共晶又
は銀ペーストを用いてリードフレーム上に固定する必要
があり、ＡｎＳｎ材又は銀ペースト等の材料が必要であ
り、又この溶融又は塗布作業が必要であるといった問題
があった。Further, at the time of die bonding of a semiconductor chip to a lead frame or the like, it is necessary to fix the semiconductor chip on the lead frame by using a solder eutectic or silver paste, and a material such as AnSn material or silver paste is used. There is a problem that it is necessary and that this melting or coating operation is necessary.
【０００８】本発明は上記事情に鑑みて為されたもの
で、薄肉のＧａＡｓ基板の裏面に金メッキ層を形成した
半導体ウェハを精度良くダイシングでき、且つダイシン
グ後の半導体チップのダイボンディングを効率的に行う
ことができる半導体装置の製造方法を提供することを目
的とする。The present invention has been made in view of the above circumstances. It is possible to accurately dice a semiconductor wafer having a gold plating layer formed on the back surface of a thin GaAs substrate, and to efficiently perform die bonding of semiconductor chips after dicing. An object of the present invention is to provide a semiconductor device manufacturing method that can be performed.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、導電性接着シートと紫外線シートとを貼り合
わせて２層のシート構造とする工程と、前記導電性接着
シート表面に薄肉のガリウムひ素基板の裏面に金メッキ
層を形成した半導体ウエハを貼付ける工程と、前記ガリ
ウムひ素基板の表面から前記紫外線シートの内部に達す
る切削を行う工程と、前記２層構造のシート裏面から紫
外線を照射して前記紫外線シートの接着力を弱めて導電
性接着シートが付着した半導体チップを分離する工程
と、前記導電性シートが裏面に付着した半導体チップを
ダイボンディングする工程とからなることを特徴とす
る。A method of manufacturing a semiconductor device according to the present invention comprises a step of laminating a conductive adhesive sheet and an ultraviolet ray sheet to form a two-layer sheet structure, and a thin-walled surface of the conductive adhesive sheet. A step of attaching a semiconductor wafer having a gold-plated layer formed on the back surface of the gallium arsenide substrate, a step of cutting the surface of the gallium arsenide substrate to reach the inside of the ultraviolet sheet; and an irradiation of ultraviolet rays from the back surface of the sheet having the two-layer structure. And weakening the adhesive force of the ultraviolet ray sheet to separate the semiconductor chip to which the conductive adhesive sheet is attached, and the step of die-bonding the semiconductor chip to which the conductive sheet is attached to the back surface. .
【００１０】上記のように構成した本発明によれば、ガ
リウムひ素基板の表面から導電性粘着シートを通過して
紫外線シートの内部に達する充分な切込み量の切削を行
うことによって、金メッキ層を確実に切断して半導体ウ
ェハのフルカットを行うことができる。これとともに、
フルカット後に紫外線を照射することによって、紫外線
シートの粘着力を弱めて半導体チップをシートから容易
に取出しつつ、個々に分離した半導体チップ裏面に付着
した粘着シートを用いてダイボンディングをそのままリ
ードフレーム等に対して行うことができる。According to the present invention configured as described above, the gold plating layer is surely cut by cutting the surface of the gallium arsenide substrate through the conductive adhesive sheet to reach the inside of the ultraviolet ray sheet. It is possible to cut the semiconductor wafer into full cuts. With this,
By irradiating ultraviolet rays after full cutting, weakening the adhesive force of the ultraviolet sheet and easily taking out the semiconductor chip from the sheet, die bonding is performed as it is using the adhesive sheet attached to the back surface of the individually separated semiconductor chip etc. Can be done against.
【００１１】[0011]
【発明の実施の形態】以下、本発明の発明の実施の形態
を図１の工程順に示す断面図に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the sectional views of FIG.
【００１２】この発明の実施の形態に使用される半導体
ウェハ１０には、図１（ａ）に示すように、例えば肉厚
ｔ１ が３０μｍ程度の薄肉のＧａＡｓ基板１１の表面
に、例えば携帯電話で使用されるのに好適な超高周波パ
ワーＦＥＴ（Field-Effet Transistor)素子が形成さ
れ、その裏面に金メッキを施すことによって、例えば肉
厚ｔ２ が２０μｍ程度の金メッキ層１２が形成されて
いる。As shown in FIG. 1A, the semiconductor wafer 10 used in the embodiment of the present invention has a thin GaAs substrate 11 having a thickness t1 of about 30 μm, for example, a mobile phone. A super high frequency power FET (Field-Effet Transistor) element suitable for use is formed, and a gold plating layer 12 having a thickness t2 of about 20 μm is formed by plating the back surface thereof with gold.
【００１３】そして、前記半導体ウェハ１０に格子状の
ダイシングラインに沿ったダイシングを施して、矩形状
の個々の半導体チップ毎に分離するのであるが、これを
以下のように行っている。Then, the semiconductor wafer 10 is diced along a grid-like dicing line to separate each of the rectangular semiconductor chips, which is performed as follows.
【００１４】先ず、導電性粘着シート１３と紫外線シー
ト１４とを貼り合わせて、２層構造のシートを作成す
る。ここに導電性粘着シートは、前記従来例における粘
着シートとほぼ同じ粘着強度を有する導電性粘着シート
である。紫外線シートは、表面に粘着物質を塗布したシ
ートであり、紫外線を照射することによって、その粘着
強度が、例えば８００ｇ／ｃｍ２ から１０〜２０ｇ／
ｃｍ２ 程度まで急激に落ちる性質を有する。First, the electroconductive pressure-sensitive adhesive sheet 13 and the ultraviolet ray sheet 14 are attached to each other to form a two-layer structure sheet. Here, the conductive pressure-sensitive adhesive sheet is a conductive pressure-sensitive adhesive sheet having substantially the same pressure-sensitive adhesive strength as the pressure-sensitive adhesive sheet in the conventional example. The ultraviolet ray sheet is a sheet having a surface coated with an adhesive substance, and has an adhesive strength of, for example, 800 g / cm 2 to 10 to 20 g / by being irradiated with ultraviolet rays.
It has the property of rapidly dropping to about cm 2.
【００１５】次にこの２層構造のシートに、ダイシング
対象の金メッキ層１２を有する半導体ウエハ１１を貼り
付ける。そして、第１図（ｂ）に示すように、例えばレ
ジンブレードを用いて、ＧａＡｓ基板１１の表面から金
メッキ層１２及び導電性粘着シート１３を通過して紫外
線シート１４の内部に達する切削を行って、ＧａＡｓ基
板１１の表面から紫外線シート１４の内部に達する切削
溝１５を形成する。Next, the semiconductor wafer 11 having the gold plating layer 12 to be diced is attached to the two-layer structure sheet. Then, as shown in FIG. 1 (b), a resin blade is used to cut the surface of the GaAs substrate 11 through the gold plating layer 12 and the conductive adhesive sheet 13 to reach the inside of the ultraviolet sheet 14. , A cutting groove 15 reaching the inside of the ultraviolet ray sheet 14 from the surface of the GaAs substrate 11.
【００１６】このように、ＧａＡｓ基板１１の表面から
紫外線シート１４の内部に達する切削を行うことによ
り、ブレードによる切込み量を増し、充分な切削深さを
確保して、例え厚さが厚くかつ比較的柔らかい金メッキ
層１２であっても、これを確実に切断することができ
る。In this way, by cutting from the surface of the GaAs substrate 11 to reach the inside of the ultraviolet sheet 14, the amount of cutting by the blade is increased and a sufficient cutting depth is secured, so that the thickness is thick and comparative. Even the soft gold plating layer 12 can be reliably cut.
【００１７】次に、紫外線シート１４の裏面側から紫外
線を照射して、該紫外線シート１４の粘着強度を、例え
ば８００ｇ／ｃｍ２ から１０〜２０ｇ／ｃｍ２ 程度
まで落とす。これにより、紫外線シート１４から金メッ
キ層１２の裏面に導電性粘着シート１３を付着した半導
体チップ１１が容易に離脱可能となる。Next, ultraviolet rays are radiated from the back side of the ultraviolet sheet 14 to reduce the adhesive strength of the ultraviolet sheet 14 from, for example, 800 g / cm 2 to 10 to 20 g / cm 2. As a result, the semiconductor chip 11 having the conductive adhesive sheet 13 attached to the back surface of the gold-plated layer 12 can be easily separated from the ultraviolet sheet 14.
【００１８】この状態で、紫外線シート１４の下から針
を突き当てて持ち上げ、個々に分離した半導体チップ１
６（同図（ｃ）参照）を導電性粘着テープ１３が貼り付
いたままコレットで真空吸着保持する。この時、前述の
ように、金メッキ層１２はダイシングラインに沿って完
全に切断させ、しかも紫外線シート１４の粘着力も急減
して弱くなっているため、半導体チップ１６の周縁部に
割れや欠けが発生することなく、容易にコレットで保持
することができる。In this state, a needle is abutted from below the ultraviolet sheet 14 and lifted up, and the semiconductor chips 1 are individually separated.
6 (see FIG. 7C) is held by vacuum suction with a collet while the conductive adhesive tape 13 is attached. At this time, as described above, the gold plating layer 12 is completely cut along the dicing line, and the adhesive force of the ultraviolet sheet 14 is also rapidly reduced and weakened, so that the peripheral edge of the semiconductor chip 16 is cracked or chipped. It can be easily held by the collet without doing.
【００１９】次に、同図（ｃ）に示すように、リードフ
レーム１７のアイランドに半導体チップ１６をダイボン
ドする。これは、コレットで吸着した導電性接着シート
が付着した半導体チップ１６をリードフレーム１７上に
移動させ、コレットでリードフレーム１７に押し当て
る。リードフレーム１７の上面に導電性接着シート１４
が接着し、更にリードフレーム１７を加熱することによ
り導電性接着シート１３が溶融することによって、半導
体チップ１６の裏面側の金メッキ層がリードフレーム１
７へ固着される。Next, as shown in FIG. 3C, the semiconductor chip 16 is die-bonded to the island of the lead frame 17. The semiconductor chip 16 to which the conductive adhesive sheet adsorbed by the collet is attached is moved onto the lead frame 17 and pressed against the lead frame 17 by the collet. The conductive adhesive sheet 14 is formed on the upper surface of the lead frame 17.
Adhere to each other, and the conductive adhesive sheet 13 is melted by further heating the lead frame 17, so that the gold plating layer on the back surface side of the semiconductor chip 16 is connected to the lead frame 1.
It is fixed to 7.
【００２０】このように、ダイシング前に予め貼り付け
た導電性粘着シート１３を利用して半導体チップ１６の
ダイボンディングを行うことにより、半導体チップの裏
面にＡｕＳｎ材を半田共晶したり、銀ペーストを塗布し
てこれを硬化させるといった工程を省略することができ
る。As described above, the semiconductor chip 16 is die-bonded by using the conductive pressure-sensitive adhesive sheet 13 previously attached before dicing, so that the AuSn material is solder eutectic on the back surface of the semiconductor chip or the silver paste is used. It is possible to omit the step of applying and curing this.
【００２１】以上のようにして、金メッキ層１２を確実
に切断した半導体ウェハ１０のダイシングを割れや欠け
を発生することなく正確に行うとともに、ダイシング後
の半導体チップ１６のダイボンディングを効率的に行う
ことができる。しかる後、通常のように、樹脂モールド
して、リードの切断等の工程を経て半導体装置を完成さ
せる。As described above, the dicing of the semiconductor wafer 10 in which the gold plating layer 12 is surely cut is accurately performed without causing cracks or chips, and the die bonding of the semiconductor chip 16 after dicing is efficiently performed. be able to. Thereafter, as usual, resin molding is performed, and a semiconductor device is completed through steps such as cutting of leads.
【００２２】[0022]
【発明の効果】以上に説明したように、本発明によれ
ば、金メッキ層を裏面に備えた３０μ厚程度の薄肉Ｇａ
Ａｓ半導体ウェハのダイシングを行うことができ、これ
によって、半導体チップの周縁部に割れや欠けが生じて
しまうことを確実に防止することができる。しかもダイ
シングによって個々に分離した半導体チップのダイボン
ディングをＡｎＳｎ材を用いた半田共晶、或いは銀ペー
スト材を用いることなく効率的に行うことができる。As described above, according to the present invention, a thin Ga layer having a gold plating layer on the back surface and having a thickness of about 30 μm is used.
It is possible to perform dicing of the As semiconductor wafer, and it is possible to reliably prevent the peripheral edge portion of the semiconductor chip from being cracked or chipped. Moreover, the die bonding of the semiconductor chips individually separated by dicing can be efficiently performed without using the solder eutectic using the AnSn material or the silver paste material.
【図１】本発明の一発明の実施の形態の半導体装置の製
造方法を工程順に示す断面図。1A to 1C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【図２】従来例におけるダイシング後の半導体ウエハの
部分断面図。FIG. 2 is a partial cross-sectional view of a semiconductor wafer after dicing in a conventional example.
Claims (1)
り合わせて２層のシート構造とする工程と、前記導電性
接着シート表面に薄肉のガリウムひ素基板の裏面に金メ
ッキ層を形成した半導体ウエハを貼付ける工程と、前記
ガリウムひ素基板の表面から前記紫外線シートの内部に
達する切削を行う工程と、前記２層構造のシート裏面か
ら紫外線を照射して前記紫外線シートの接着力を弱めて
導電性接着シートが付着した半導体チップを分離する工
程と、前記導電性シートが裏面に付着した半導体チップ
をダイボンディングする工程とからなることを特徴とす
る半導体装置の製造方法。1. A step of laminating a conductive adhesive sheet and an ultraviolet ray sheet to form a two-layered sheet structure, and a semiconductor wafer having a gold plating layer formed on the back surface of a thin gallium arsenide substrate on the surface of the conductive adhesive sheet. A step of adhering, a step of cutting the surface of the gallium arsenide substrate to reach the inside of the ultraviolet ray sheet, and irradiation of ultraviolet rays from the back surface of the sheet having the two-layer structure to weaken the adhesive force of the ultraviolet ray sheet and conductive adhesion. A method of manufacturing a semiconductor device, comprising: a step of separating a semiconductor chip having a sheet attached thereto; and a step of die-bonding the semiconductor chip having the conductive sheet attached to a back surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12348896A JPH09306932A (en) | 1996-05-17 | 1996-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12348896A JPH09306932A (en) | 1996-05-17 | 1996-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09306932A true JPH09306932A (en) | 1997-11-28 |
Family
ID=14861875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12348896A Pending JPH09306932A (en) | 1996-05-17 | 1996-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09306932A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006517054A (en) * | 2002-11-27 | 2006-07-13 | フリースケール セミコンダクター インコーポレイテッド | GaAs thin die with copper backside metal structure |
-
1996
- 1996-05-17 JP JP12348896A patent/JPH09306932A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006517054A (en) * | 2002-11-27 | 2006-07-13 | フリースケール セミコンダクター インコーポレイテッド | GaAs thin die with copper backside metal structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4109823B2 (en) | Manufacturing method of semiconductor device | |
| US7297412B2 (en) | Fabrication of stacked microelectronic devices | |
| JP3662260B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5770468A (en) | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere | |
| JPH0554262B2 (en) | ||
| US5302554A (en) | Method for producing semiconductor device | |
| US20130328218A1 (en) | Sealed semiconductor device having adhesive patch with inwardly sloped side surfaces | |
| US5316853A (en) | Expand tape | |
| JP2000182995A (en) | Manufacture of semiconductor device | |
| US5762744A (en) | Method of producing a semiconductor device using an expand tape | |
| JPH09213662A (en) | Method of splitting wafer and method of manufacturing semiconductor device | |
| US20200058510A1 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JP2005050914A (en) | Method for manufacturing semiconductor device | |
| US4883773A (en) | Method of producing magnetosensitive semiconductor devices | |
| JP3013786B2 (en) | Method for manufacturing semiconductor device | |
| US8580070B2 (en) | Method of applying an adhesive layer on thincut semiconductor chips of a semiconductor wafer | |
| JP2001060591A (en) | Manufacture of semiconductor device | |
| JP2006294685A (en) | Semiconductor chip having back metal film and manufacturing method thereof | |
| JP2003318205A (en) | Method of bonding film-like die bonding material of diced wafer | |
| JPH09306932A (en) | Manufacture of semiconductor device | |
| JP2680364B2 (en) | Method for manufacturing semiconductor device | |
| JP3528412B2 (en) | Method for manufacturing semiconductor device | |
| JP2004128339A (en) | Method of manufacturing semiconductor | |
| Cheung | Dicing die attach films for high volume stacked die application | |
| TWI251924B (en) | A process applied to semiconductor |