JPH09305561A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the instruction throughput of a multiprocessor system from being lowered even when there is the erasing instruction of correspondent information in an address translation buffer. SOLUTION: Processors 1 and 2 share a main storage device 3. An address translation buffer index control part 13 receives a logical address from an instruction analytic part 11, indexes an address translation buffer 12 corresponding to the erasure contents of an address translation buffer erasure control part 14 and sends out erasing operation stop to the address translation buffer erasure control part 14 during the index of the address translation buffer 12. The address translation buffer erasure control part 14 receives an erasing instruction from the instruction analytic part 11 and erases the correspondent information in the address translation buffer 12 and at such a time, the erasing operation stop from the address translation buffer index control part 13 is received so that the erasing operation of the address translation buffer 12 is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of virtual memory type processors sharing a main memory, and more particularly to an address translation buffer (T
LB) erasure improvement.

[0002]

2. Description of the Related Art A conventional multiprocessor system is shown in FIG.
Refer to. In FIG. 4, two processors 1, 2
Are connected to the main storage device 3 by a bus 4. That is, the processors 1 and 2 share the main storage device 3.
Each processor 1 (2) includes an instruction analysis unit 1 that analyzes an instruction.
1 (21), an address translation buffer 12 that stores a logical page address and a real page address in pairs for fast translation of the logical page address into the real page address
(22), the address translation buffer index control unit 13 (23) that operates the address translation buffer 12 (22) to generate a real address based on the instruction analyzed by the instruction analysis unit 11 (21), and the instruction analysis unit 11 The address translation buffer erase controller 14 (24) erases (invalidates) the logical page address of the address translation buffer 12 (22) based on the instruction analyzed by (21). Here, the instruction analysis units 11 and 12, the address translation buffer erasure control unit 1
4, 24 are commonly connected by a bus 5. Also,
The instruction execution stopping unit 6 is the address translation buffer erasing control unit 1.
4 and 24 and the instruction analysis units 11 and 21 are connected.

First, the access operation of the main memory 3 of the processor 1 will be described. When the instruction analyzed by the instruction analysis unit 11 involves reading or writing of the main storage device 3, the logical address is sent to the address translation buffer index control unit 13. In response to this, the address translation buffer index control unit 13 separates the logical address into a logical page address that changes by the address translation and an in-page relative address that does not change even when the address translation is performed, and only the logical page address is translated into the address translation buffer 12. Send to. As a result,
In the address translation buffer 12, if there is information that is matched by being indexed by the logical page address (hit), the address translation buffer 12 sends the real page address to the address translation buffer index control unit 13. In response to this, the address translation buffer index control unit 13 combines the real page address and the above-mentioned in-page relative address to generate a real address, whereby the main memory 3
Will be able to access. In this case, although the address translation buffer index controller 13 (23) is not affected by the operation of the address translation buffer erase controller 14 (24), the address translation buffer erase controller 14 will be described later. (24) is the address translation buffer 12
When the corresponding information erasing operation of (22) is performed, the effect is received via the instruction execution stopping unit 6. The processor 2 also performs the same access operation.

Next, the operation of erasing the corresponding information in the address translation buffers 12 and 22 of the processors 1 and 2 will be described. When the operating system that manages the resources of the multiprocessor system deallocates the real page from the logical page, the address translation buffer erase control unit 1
Reference numerals 4 and 24 erase the corresponding information in the address translation buffers 12 and 22. That is, when the instruction analyzed by the instruction analysis unit 11 or 21 is the erase instruction of the address translation buffer erase control unit 12 or 22, the instruction analysis unit 11 or 2
1 sends an instruction for erasing the designated logical page to all the address translation buffer erasing control units 14 and 24 via the bus 5. In response to this, the address translation buffer erase control units 14 and 24 send the logical pages to be erased to the address translation buffers 12 and 22, and the instruction execution suspending unit 6 indicates that the address translation buffers 12 and 22 are to be erased. To notify. As a result, the address translation buffer 12,
22 erases the correspondence information between the designated logical page address and real page address. On the other hand, the instruction execution stopping unit 6 instructs the instruction analyzing units 11 and 21 of all the processors 1 and 2 to stop the execution of instructions other than the erase instruction. This guarantees the sameness of the conversion from the logical address to the real address performed in the multiprocessor system after the execution of the corresponding information erasing instruction of the address translation buffers 12 and 22. That is, in FIG. 4, the address translation buffer index control unit 13 (23) and the address translation buffer erase control unit 14 (24) do not directly interfere with each other, and the arbitration of the operation therebetween is performed by the address translation buffer erase control unit 14. When (24) operates, it is performed by the instruction execution stopping unit 6.

[0005]

However, in the above-mentioned conventional multiprocessor system, after the erasing instruction of the corresponding information of the address translation buffer is issued, the erasing operation of the address translation buffers of all the processors is completed. However, since the execution of all instructions other than the erase instruction is stopped, there is a problem that the instruction processing capability of the multiprocessor system deteriorates. Therefore, it is an object of the present invention to prevent the instruction processing capability of the multiprocessor system from deteriorating even when there is an instruction to erase the corresponding information in the address translation buffer.

[0006]

In order to solve the above problems, the present invention is directed to a multiprocessor system having a plurality of processors of a virtual memory system sharing a main memory, in which each processor is provided with a logical address and a real address. An address translation buffer for storing the correspondence information with, an instruction analysis means, an address translation buffer index control means, and an address translation buffer erase control means are provided. The instruction analysis unit analyzes the instruction, sends a logical address when the instruction involves access to the main memory, and sends an erase instruction when the instruction includes erasing corresponding information in the address translation buffer. The address translation buffer index control means receives the logical address from the instruction analysis means and indexes the address translation buffer. The address translation buffer index control means indexes the address translation buffer according to the erase contents of the address translation buffer erase control means, and During the indexing, the erase operation stop is sent to the address translation buffer erase control means. The address translation buffer index control means erases the corresponding information in the address translation buffer, and stops the erase operation of the address translation buffer in response to the erase operation stop from the address translation buffer index control means. That is, the address translation buffer index control means and the address translation buffer erase control means directly interfere with each other. Thus, even if the address translation buffer erasing control means is erasing the address translation buffer, the address translation buffer index control means stops the address translation buffer erasing operation if the logical address is not involved in erasing. Index the address translation buffer by logical address.

[0007]

1 is a block circuit diagram showing an embodiment of a multiprocessor system according to the present invention, in which the instruction execution suspending unit 6 of FIG. 3 does not exist. The address translation buffer index control units 13 and 23 and the address translation buffer erasure control units 14 and 24 are directly connected. Therefore, the address translation buffer index control unit 13 (2
3) Operation and address translation buffer erase controller 14 (2
It directly interferes with the operation of 4).

The operation of the address translation buffer index controller 13 of FIG. 1 will be described with reference to FIG. When the instruction analyzed by the instruction analysis unit 11 is an instruction that involves reading or writing of the main storage device 3, control enters step 201. In step 201, the address translation buffer erase controller 1
The output signal 4 controls whether the address translation buffer 12 is in the erasing operation. As a result, if the address translation buffer 12 is not being erased, the process proceeds to step 202,
If the address translation buffer 12 is being erased, the process proceeds to step 203.

In step 201, the address translation buffer index controller 13 separates the logical address received from the instruction analyzer 11 into a logical page address and an in-page relative address, and sends only the logical page address to the address translation buffer 12. . As a result, in the address translation buffer 12, if there is information that is indexed and matched with the logical page address (hit), the address translation buffer 12 sends the real page address to the address translation buffer index controller 13. In response to this, the address translation buffer index control unit 13 combines the real page address and the above-mentioned relative address within the page to generate a real address, and thereby accesses the main memory device 3.

In step 203, it is determined whether the logical address received from the instruction analysis unit 11 is within the erase address range. As a result, if the logical address is in the erase address range, the process proceeds to step 204, it is determined that the conversion is unsuccessful, and the address conversion buffer 12 is not indexed. On the other hand, if the logical address is not in the erase address range, the process proceeds to step 205.

At step 205, an erase operation stop signal is sent to the address translation buffer erase controller 14 to stop the erase operation of the address translation buffer 12 of the address translation buffer erase controller 14. And step 206
Proceed to. In step 206, as in step 202, the address translation buffer 12 is indexed to obtain a real page address, and a real address is generated to access the main memory device 3. In step 207, the erase operation stop signal sent to the address translation buffer erase controller 14 is released, and the address translation buffer erase controller 14 is released.
The erasing operation of the address translation buffer 12 is restarted.
Then, the process proceeds to step 208.

The routine of FIG. 2 ends with step 208. The address translation buffer index control unit 23 also performs the same operation.

The operation of the address translation buffer erase controller 14 of FIG. 1 will be described with reference to FIG. When the instruction analyzed by the instruction analysis unit 11 is an erase instruction for the address translation buffer 12, control enters step 301. Step 30
At 1, the erase signal and the erase address range indicating that the erase is effective are sent to the address conversion buffer index control unit 14. This operation is continued until it is canceled in step 305. In step 302, it is judged from the output signal of the address translation buffer index control unit 13 whether or not the erase operation stop signal is transmitted. As a result, if the erase operation stop signal has been sent, it waits until the erase operation stop signal is released. If the erase stop signal has not been sent, the process proceeds to step 303.

In step 303, it is judged whether or not there is a logical address to be erased (remains). As a result, if there is a logical address to be erased, the process proceeds to step 304, and if there is no logical address to be erased, step 30
Go to 5. In step 304, the logical address to be erased is erased for each set unit. At this time, the internal state is saved in preparation for restarting the erase operation. And step 302
Then, the above operation is repeated.

That is, if the erase operation stop signal is not generated at all, the erase operation of step 303 is repeated until all logical addresses to be erased are erased in steps 301 and 302, and the process proceeds to step 304.
When the erase operation stop signal is generated during the erase operation, the internal state is saved, and in step 301, the erase operation is restarted.

At step 305, the transmission of the erase signal and erase address range to the address translation buffer index controller 14 is canceled, and at step 306 the routine of FIG. 3 ends. The address translation buffer erase control unit 24 also performs the same operation.

In this way, the address translation buffer 1
It is also ensured that the logical address-to-real address conversion in the multiprocessor system is identical after the execution of the corresponding information erasing instructions 2 and 22.

[0018]

As described above, according to the present invention, even if an erase command for the corresponding information in the address translation buffer occurs, the execution of the erase command is temporarily stopped and an access command other than the erase command is executed. As a result, the instruction processing capability of the multiprocessor system can be improved.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a multiprocessor system according to the present invention.

2 is a flowchart showing an operation of an address translation buffer index controller of FIG.

FIG. 3 is a flowchart showing an operation of an address translation buffer erasing controller of FIG.

FIG. 4 is a block circuit diagram showing a conventional multiprocessor system.

[Explanation of symbols]

 1, 2 ... Processor 3 ... Main storage device 4, 5 ... Bus 6 ... Instruction execution stop unit 11, 21 ... Instruction analysis unit 12, 22 ... Address translation buffer 13, 23 ... Address translation buffer index control unit 14, 24 ... Address Conversion buffer cancellation control unit

Claims (3)

[Claims] 1. A multiprocessor system comprising a plurality of virtual memory type processors (1, 2) sharing a main memory (3), wherein each processor stores correspondence information between a logical address and a real address. An address translation buffer (12, 22) for performing analysis of an instruction, sending a logical address when the instruction involves access to the main memory, and the instruction includes erasing corresponding information in the address translation buffer In this case, an instruction analysis means (11, 21) for sending an erase instruction, the address translation buffer index control means (13, 23) which receives a logical address from the instruction analysis means, and an erase instruction from the instruction analysis means Address translation buffer erasing control means (14, 24) for receiving the address translation buffer and erasing the corresponding information in the address translation buffer. The address translation buffer index control means indexes the address translation buffer according to the erase content of the address translation buffer erase control means, and the address translation buffer erase control means stops the erase operation during the index of the address translation buffer. The multiprocessor system, wherein the address translation buffer erase control means stops the erase operation of the address translation buffer in response to the erase operation stop from the address translation buffer index control means. 2. The address translation buffer erase control means stores the internal state of the address translation buffer erase control means when it receives the erase operation halt from the address translation buffer index control means, and receives the erase operation halt release. The erasing of the address translation buffer is restarted from the internal state of the address translation buffer erasing control means.
The multiprocessor system according to. 3. A multiprocessor system comprising a plurality of virtual memory processors (1, 2) sharing a main memory (3), wherein each processor stores correspondence information between a logical address and a real address. And an address translation buffer (12, 22) for performing analysis of an instruction, and when the instruction involves access to the main storage device, the logical address is sent out, and the instruction erases corresponding information in the address translation buffer. Instruction analysis means (11, 21) for sending an erase instruction when included, the address translation buffer index control means (13, 23) that receives a logical address from the instruction analysis means, and erase from the instruction analysis means Address translation buffer erasing control means (14, 24) for erasing corresponding information of the address translation buffer in response to an instruction, The address translation buffer index control means, when erasing by the address translation buffer erasing control means is invalid, indexes the address translation buffer with the logical address of the instruction analysis means to obtain a real address to access the main storage device. Means for determining whether or not the logical address from the instruction analysis means is within the erase address range of the address translation buffer erase control means when the erase of the address translation buffer erase control means is valid; Means for failing address translation when the logical address from the means is within the erase address range of the address translation buffer erase control means, and the logical address from the instruction analysis means is the erase address range of the address translation buffer erase control means If not, the logical address of the instruction analysis means is used to Address translation buffer erase control means for continuously sending an erase operation stop to the address translation buffer erase control means while accessing the main storage device by indexing the address translation buffer to obtain a real address. The control means receives the erasing instruction from the instruction analysis means, sends the fact that erasing is effective and the erase address range to the address translation buffer index control means, and the erase operation from the address translation buffer index control means. Means for controlling whether a stop is sent, means for erasing the address translation buffer when the erase operation stop is not sent from the address translation buffer index control means, and means for erasing the address translation buffer. When completed, the erase is valid and the address change of the erase address range is completed. And a means for canceling the transmission to the replacement buffer index control means.