JP2517977B2 - Input / output interrupt control method in virtual machine - Google Patents

Description

The present invention relates to an input / output interrupt control method in a virtual computer, and more particularly to an input / output interrupt control method in a virtual computer capable of speeding up input / output control. .

[Prior art]

In conventional virtual machine control, all I / O devices are under the control of a control program (hereinafter referred to as VM monitor) that controls the virtual machine, and an operating system (hereinafter referred to as OS) that operates under VM monitor is issued. The I / O instruction to be executed is once trapped, and the VM monitor simulates it.

The input / output interrupt from the input / output device uses the prefix area (PXA) used by the VM monitor, and the VM monitor accepts the input / output interrupt once and then returns it to the I / O instruction issuer. Was there.

Such a virtual machine is, for example, as shown in FIG.
A U501, a main memory control unit 502, a channel control unit 503, input / output devices 541 and 542, and a main memory 505 are provided.

Further, the main memory 505 is divided into a VM monitor 551, an OS # 1 memory area 552, and an OS # 2 memory area 553, and a channel program storage area 5521 and a prefix area (PXA) 5510, It is equipped with 5520 and 5530.

Further, the main memory control unit 502 includes a head address holding circuit 521 of the VM monitor area 551, a prefix conversion circuit 522, a data holding circuit 523, a VMID holding circuit 524, a decoder circuit 525,
A buffer circuit (FXB) 526, a latch circuit 527, and a check circuit 528 are provided.

As shown in FIG. 6, the buffer circuit 526 stores the value to be added (AAA) and the upper limit address (UUU) corresponding to each OS.

The latch circuit 527 latches when the entry of the OS indicated by the decoder circuit 525 is read from the buffer circuit 526.

Further, in the check circuit 528, the contents of the latch circuit 527 and the contents of the signal 5312 are added, and the upper limit address (UU
Check that U) is not exceeded. In this case, the channel program in the channel program storage area 5521 can be accessed only when the upper limit address (UUU) is not exceeded.

When the main memory 505 is divided and used in this way,
Access from the channel control unit 503 to the main memory 505 is classified into two types.

That is, the access indicated by the signals 5311 and 5312 indicates the access path to the channel program and data of each OS in the channel program storage area 5521. In this case, the signal 5312 is the main program memory address indicated by each OS and the main memory address recognized by the following cormorant OS.
A signal 5311 is an indicator (hereinafter abbreviated as VMID) that identifies the OS.

However, even if the main memory 505 is accessed with the address of the signal 5312, the target channel program in the channel program storage area 5521 cannot be accessed. This is because the channel program is actually stored in the area indicated by the address to which a certain value is added, unlike the address recognized by the OS. In addition,
The value is set by the VM monitor at the initial stage of system construction.

Therefore, in order to access the channel program using the address of the signal 5312, it is necessary to add a certain value, and the necessary processing is performed by each of the circuits 524 to 528.

On the other hand, signals 5301 and 5302 are transmitted to the channel control unit 503.
This is the information stored in the main memory at the time of an interrupt from.

Further, since all input / output interrupts are processed in the VM monitor area 551, for example, even if the OS is OS # 1, the prefix of the VM monitor area 551 is not the prefix area 5520 of the memory area 552 for OS # 1. Must be stored in area 5510.

Therefore, the input / output interrupt information is stored in the prefix area 5510 via the head address holding circuit 521 holding the head address of the prefix area 5510, the prefix conversion circuit 522, and the data holding circuit 523 regardless of the VMID.

Therefore, the VM monitor passes the information to each OS after performing the simulation based on the information.

In this way, in order to operate the virtual machine at high speed, the main memory 505 is divided, a continuous area is allocated for each OS, and the main memory access from the channel control unit 503 is also performed by each OS.
The address of the channel program issued by is provided with a buffer that holds a preset value for each OS, and when the main memory is accessed, the value is added and accessed.

Even if the system that allocates the prefix area to each OS is adopted, the VM is
Interrupt acceptance processing is performed using the prefix area of the monitor.

That is, when an I / O interrupt is accepted, I / O information (channel status word (CS
W)) is stored, the new program status word of I / O interrupt (hereinafter abbreviated as PSW) is loaded from the prefix area to the current PSW, the interrupt acceptance processing is performed, and then the I / O device that caused the interrupt Since the interrupt is returned to the OS that issued the I / O instruction, simulation is performed to convert the interrupt information so that it matches the OS, and then the interrupt information is stored in the input / output interrupt information of the OS prefix area. After moving to the area, the new PSW of the input / output interrupt of the prefix area was loaded into the current PSW and a pseudo interrupt was generated.

[Problems to be solved by the invention]

In the above conventional technique, the VM monitor needs to perform a lot of processing regarding interrupts, which is a major cause of reducing the performance of the virtual machine.

An object of the present invention is to improve such a problem and to directly store the interrupt information in the OS prefix requesting the I / O processing, thereby reducing the overhead at the time of the I / O interrupt. It is to provide an input / output interrupt control system in a computer.

[Means for solving problems]

In order to achieve the above object, an input / output interrupt control method in a virtual computer according to the present invention is an input / output device, a main memory, a control program of a virtual computer, and a main memory area allocated corresponding to each operating system. And a means (buffer circuit) for storing address information indicating that the main memory is divided to allocate a continuous area for each operating system, and a prefix area used by each operating system is provided in the area. In the electronic computer which controls the virtual computer by allocating the above, in the buffer circuit, means for storing information designating direct execution of input / output control for each operating system (direct execution information storage circuit), each operating system -Means for storing the start address of the prefix area of the system (start address Holding circuit), and means for storing an indicator indicating whether the operating system is in operation (operating indicator storage circuit), and a latch for latching data from the direct execution information storage circuit. Circuit, specific operating system for the above I / O devices
A means for holding information designating direct execution of input / output control by the system (control instruction information storage circuit), a latch circuit for latching data from the buffer circuit, and a latch circuit for latching direct execution designation information of each OS When there is an input / output interrupt from the input / output device by providing means (judgment circuit) for judging the selection of the prefix area of the operating system by the signal of the control instruction information storage circuit
If both the direct execution specification information for each operating system and the direct execution specification information for the input / output device indicate direct execution and the operating system is not running, the prefix area for the control program is entered. Output interrupt information is stored, and I / O interrupt control is performed by the new program status word (hereinafter abbreviated as PSW) of the input / output interrupt in the prefix area, and direct execution designation information for each operating system and input / output Only when both the direct execution designation information corresponding to the device indicates direct execution and the operating system is operating, the input / output interrupt information is directly stored in the prefix area for the operating system, and the prefix is stored. I / O interrupt processing is performed based on the new PSW of the area I / O interrupt In addition, when the direct execution designation information corresponding to the input / output device indicates the direct execution, and the direct execution designation information for each operating system does not instruct the direct execution, or both of the information do not instruct the direct execution. In this case, the I / O interrupt is controlled in the prefix area for the control program, the direct execution designation information corresponding to the I / O device does not directly instruct the execution, and
When the direct execution designation information for each operating system indicates direct execution, it is characterized by not performing input / output interrupt control and reporting as an error.

[Action]

In the present invention, the input / output interrupt information is directly output to the OS that is allowed to directly execute the input / output control.
In order to store in the prefix area of the OS, the buffer circuit holds the prefix area start address corresponding to each OS, the prefix conversion function reads the start address, and performs the prefix conversion by the value.

In a conventional virtual machine, the hardware temporarily stores the input / output interrupt information in the prefix area of the VM monitor and performs the prefix conversion when the input / output is started by any OS.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an electronic computer system in one embodiment of the present invention, FIG. 2 is an explanatory diagram of a buffer circuit (FXB) in one embodiment of the present invention, and FIG. 3 is a view of one embodiment of the present invention. FIG. 4 is a configuration diagram of the decision circuit, and FIG. 4 is an input / output control flowchart in one embodiment of the present invention.

As shown in FIG. 1, the electronic computer system of this embodiment is
A CPU 1, a main memory control unit 2, a channel control unit 3, input / output devices 41 and 42, and a main memory 5 are provided.

In addition, the signals 301, 302, 31 sent from the channel control unit 3
1, 313 are signals indicating a main memory storage destination address of data, main memory storage data, VMID, and a direct execution instruction, respectively.

Further, the main memory 5 includes a specific area 50, a VM monitor area 51, an OS
It is divided into a memory area 52 for # 1 and a memory area 53 for OS # 2, a subchannel storage area 500 for the specific area 50, a VM monitor area 51, and a prefix area for the memory area 52 for OS # 1.
Includes 510 and 520.

The main memory control unit 2 also includes an input / output interrupt mask control circuit 20, a head address holding circuit 21 in the VM monitor area, a prefix conversion circuit 22, a data holding circuit 23, and a VMID holding circuit.
24, decoder circuit 25, buffer circuit (hereinafter abbreviated as FXB) 2
6, latch circuit 27, 271, 272, 273, check circuit 28, determination circuit 211, control instruction information storage circuit 241, direct execution information storage circuit 261, the start address holding circuit 262 in the OS memory area,
An operating indicator storage circuit 263 and an interrupt control unit 2121 are provided.

The control instruction information storage circuit 241 stores, in the input / output devices 41 and 42, the direct execution instruction signal 313 indicating that the specific OS indicated by the VMID holding circuit 24 is permitted to directly control.

It should be noted that this information is normally stored together with the VMID in the sub-channel storage area 500 that stores the information corresponding to the input / output device in the specific area 50 of the main memory 5, and the channel control unit 3 starts the input / output at the sub-channel storage area. Lead this information from 500.

Further, as shown in FIG. 2, a direct execution information storage circuit 261, a head address storage circuit 262, and an operating indicator storage circuit 263 are added to the buffer circuit 26.

The direct execution information storage circuit 261 indicates by the direct execution designation bit X whether or not the direct execution of the input / output control is permitted.

Further, the head address storage circuit 262 stores the prefix area head address YYY of the OS as a prefix value recognized by each OS.

Further, the operating indicator storage circuit 263 is currently
An in-operation indicator Z indicating whether or not S is in operation is stored.

The latch circuits 271, 272, 273 directly latch the data from the execution information storage circuit 261, the head address storage circuit 262, and the operating indicator storage circuit 263.

Further, the determination circuit 211, as shown in FIG.
10 ~ 2113,2115,2116,2210,2211, OR gate 2114,2119,
And a selector circuit 2117, 2118.
1, 273 and a signal from the control instruction information storage circuit 241 determine whether the content of the head address holding circuit 21 or the content of the latch circuit 272 is selected as the prefix area.

That is, both the signals from the latch circuit 271 and the control instruction information storage circuit 241 permit the direct execution of the input / output control, and the latch circuit 273 causes the OS, for example, OS # 1.
Is indicated to be operating, the contents of the latch circuit 272, that is, the prefix area start address of the OS # 1 memory area 52 is selected.

If the signal from the latch circuit 271 indicates non-permission and the signal from the control instruction information storage circuit 241 indicates permission, an error report is made.

Further, when the signals from the latch circuit 271 and the control instruction information storage circuit 241 both permit direct execution of input / output control, and the latch circuit 273 indicates that the OS # 1 is not in operation, When the signal from the circuit 271 indicates permission and the signal from the control instruction information storage circuit 241 indicates non-permission, or when both of these signals indicate non-permission, the contents of the head address holding circuit 21 are selected. Control to do.

For the new I / O interrupt PSW, see OR circuit 2119.
Is sent to the CPU1 and loaded into the PSW of the CPU1 from the prefix area specified by the OR circuit 2119.

The prefix conversion circuit 22 also performs prefix conversion using the prefix start address selected by the determination circuit 211.

Further, the interrupt control unit 2121 controls interrupt processing according to the determination signal 2120 sent from the determination circuit 211.

FIG. 4 is a flow chart of input / output interrupt control in one embodiment of the present invention.

In the computer of the present embodiment, when an input / output interrupt cause occurs (401), based on the VMID sent from the channel control unit 3, the direct execution designation bit and the prefix area (PXA) head from the OS entry of the buffer circuit. address,
And reading out the operating indicator (402).

Next, the control instruction from the channel control unit 3 is compared with the direct execution designation of the OS (403), and first, it is determined whether or not the OS directs the direct execution (404).

As a result of the determination (404), if direct execution is instructed, then it is determined whether the instruction from the channel control unit 3 is direct execution (405).

As a result of the determination (405), if the instruction from the channel control unit 3 is directly executed, it is next determined whether or not the OS is operating (406).

As a result of the determination (406), if the OS is operating,
Prefix conversion (PX conversion) is performed based on the prefix area (PXA) start address (407).

Next, the I / O interrupt information is stored in the pre-pix area (PXA) (408) and the new information in the prefix area 520 is stored.
I / O interrupt processing is executed by PSW (409).

In addition, as a result of determining whether the OS is directly instructing execution (404), if direct execution is not instructed,
Next, it is determined whether the instruction from the channel control unit 3 is directly executed (410).

As a result of the determination (410), if the instruction from the channel control unit 3 is directly executed, an error report is made.

As a result of the determination (410), if the instruction from the channel control unit 3 is not directly executed, the prefix conversion (PX conversion) is performed based on the prefix area (PXA) start address of the control program of the virtual machine (411). ).

Next, the input interrupt information is stored in the prefix area (PXA) (412), and the input / output interrupt processing is executed by the new PSW in the prefix area (413).

In this embodiment, a signal similar to the signal 5312 in FIG. 5 is sent on the same line as the signal 301, but since it is not an access to the prefix area, the prefix conversion circuit 22
Check circuit without undergoing prefix conversion in
Take the path entered at 28.

Further, when the input / output interrupt information is stored from the channel controller 3, the prefix conversion and the address addition are performed, but the sub-channel group is the characteristic area 50 of the main memory 5.
If it is stored in the sub-channel storage area 500 of the specific area 50 from the channel control unit 3, the CPU 1
When the input / output interrupt is enabled by, the CPU1 or the like reads the VMID from the sub-channel storage area 500 along with the directly executable bit, and stores it in the prefix area through the address translation path (circuits 24 to 28). take.

Further, the input / output interrupt mask control circuit 20 is set for each OS for which direct execution of input / output control is permitted.

Further, in this embodiment, the operating indicator storage circuit 263 and the latch circuit 273 can store the input / output interrupt information in the prefix area for the OS only when the OS is operating. When such a function is not provided, the selection of the prefix area is determined by the signals of the latch circuit 271 and the control instruction information storage circuit 241. That is, if both of these signals permit direct execution of input / output control, the contents of the latch circuit 272 are selected and the input / output interrupt information is stored in the prefix area for the OS.

〔The invention's effect〕

According to the present invention, at the time of an input / output interrupt, the input / output interrupt information can be directly stored in the prefix area of the OS requesting the input / output processing. Therefore, the mediation by the VM monitor is unnecessary, and the overhead of the input / output interrupt can be reduced. It is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an electronic computer system in one embodiment of the present invention, FIG. 2 is an explanatory diagram of FXB in one embodiment of the present invention, and FIG. 3 is a configuration of a determination circuit in one embodiment of the present invention. FIG. 4, FIG. 4 is an input / output control flowchart in one embodiment of the present invention, FIG. 5 is a block diagram of a conventional computer system, and FIG. 6 is an explanatory diagram of a conventional FXB. 1,501: CPU, 2,502: Main memory controller, 3,503: Channel controller, 5,505: Main memory, 20: I / O interrupt mask control circuit, 21,5
21: Start address holding circuit (VM monitor area), 22,522: Prefix conversion circuit, 23,523: Data holding circuit, 24,524: VM
ID holding circuit, 25,525: Decoder circuit, 26,526: Buffer circuit (FXB), 27,271,272,273,527: Latch circuit, 28,528: Check circuit, 41,42,541,542: Input / output device, 50: Specific area, 51,5
51: VM monitor area, 52,552: Memory area for OS # 1, 53,553: OS #
2 memory area, 211: judgment circuit, 241: control instruction information storage circuit, 261: direct execution information storage circuit, 262: start address holding circuit (OS memory area), 263: operating indicator storage circuit, 301, 30
2,311,5301,5302,5311,5312: Signal, 313: Direct execution instruction signal, 2120: Judgment signal, 500: Sub channel storage area, 510, 5510: V
M monitor area prefix area (PXA), 520,5520,5530: O
Prefix area (PXA) of S memory area, 2121: Interrupt controller, 2110 to 2113, 2115, 2116, 2210, 2211: AND gate, 211
4,2119: OR gate, 2117, 2118: Selector, 5521: Channel program storage area, AAA: Start address, UUU: Limit address, X: Direct execution designation bit, YYY: Prefix area start address of the OS, Z: Operation Middle indicator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Sakae Uozumi, City of Takeshi 1-2356, Yokosuka City, Kanagawa Nihon Telegraph and Telephone Corporation (56) Reference JP-A-62-31437 (JP, A) JP-A-61-240333 (JP, A)

Claims (2)

(57) [Claims] 1. An input / output device, a main memory, a control program for a virtual machine, and means for storing address information indicating a main memory area allocated corresponding to each operating system. In the electronic computer that controls the virtual computer by dividing the partition into a continuous area for each operating system and allocating a prefix area used by each operating system in the area, storing the address information. The means is provided with means for storing information designating direct execution of input / output control for each operating system, and means for storing the start address of the prefix area of each operating system, and the input / output Direct I / O control by a specific operating system is specified for the device. Information holding means, means for latching data from the direct execution designation information storage means, means for latching data from the head address storage means, and direct execution designation information latch means and the direct execution designation information A means for judging the selection of the prefix area of the operating system is provided by the signal of the holding means, and when there is an input / output interrupt from the input / output device, direct execution designation information for each operating system and the input / output. The input / output interrupt information is directly stored in the prefix area for the operating system only when the direct execution specification information corresponding to the device both direct execution, and the direct execution specification information corresponding to the input / output device is directly executed. And the direct execution designation information for each operating system does not instruct direct execution. If or,
If both of the information do not instruct direct execution, the I / O interrupt is controlled in the prefix area for the control program, and the direct execution designation information corresponding to the input / output device does not instruct direct execution. And the operating system
An I / O interrupt control method in a virtual machine characterized by not performing I / O interrupt control and reporting as an error when direct execution designation information for each system directs execution. 2. The address information storage means includes means for storing an indicator indicating whether or not the operating system is in operation, and direct execution designation information for each operating system and input / output device correspondence. If both of the direct execution specification information of # 1 and # 2 indicate direct execution and the operating system is not operating, the input / output interrupt information is stored in the prefix area for the control program, and the input / output of the prefix area is stored. I / O interrupt control is performed by the new program status word of the interrupt, and direct execution designation information for each operating system and direct execution designation information corresponding to the input / output device both direct execution, and Prefix for the operating system only if the system is running The input / output interrupt information is stored in the queue area, and the input / output interrupt processing is performed based on the new program status word of the input / output interrupt in the prefix area. Output interrupt control method.