KR960004059B1 - Asynchronous memory system access method - Google Patents

Abstract

sensing a request signal inputted from an exterior by an input interface; if it is determined that if a state of an input queue is full, requesting an approachment of a memory device through a connecting means; if the state of the input queue is not full, storing an input request in the input queue; if the input queue is empty, repeatedly determining whether the input request in the input queue is full; if the input queue is not empty, reading the stored input request to control a read/write operation of the memory device; determining whether the input request is read or written; if the write operation is needed, writing the data on the memory device and reading a new input request in the input queue; if the read operation is needed, reading the data on the memory device; generating an input request signal to an asynchronous output queue and if the output queue is full, waiting until the output queue is empty; if the output queue is not full, storing a response to the read request of a memory device controller; if the output queue is empty, waiting until the output queue is full; if the output queue is not empty, reading the data from the output queue; if the read data transmission is completed, checking whether the output queue is empty; and if the data transmission is not completed, repeating the transmitting operation.

Description

Asynchronous Storage Approach

1 and 2 are schematic diagrams of a typical processor system.

3 is a block diagram of a structure according to the invention.

4 is a flowchart of operation according to the present invention.

* Explanation of symbols for main parts of the drawings

4: input interface 5: input cue

6: storage controller 7: storage

8: output queue 9: output interface

The present invention relates to an asynchronous memory device access method between an input / output interface and an internal memory device in a main memory device of a computer system.

In general, the performance of a computer system is affected by the operating speed of the processor, the transfer speed of the connection medium, and the access time of the storage device.

Therefore, in order to construct a high performance computer system, a fast operating speed processor, a high speed connection medium, and a short time storage device must be used.

A general computer system is constructed as shown in FIGS. 1 and 2, in which FIG. 1 is a processor 1 for substantially executing a program in a single processor system, a storage device 3 for storing programs and data, and a processor ( The storage device 3 of 1) comprises a connection medium 2, such as a bus or an interconnection network, which is an access passage.

In addition, in a computer system such as the first diagram, changes in the operating speeds of the processor 1 and the memory device 3 can affect each other.

As a result, when the operating speed of the processor 1 is increased, the access time of the memory device 3 is relatively slow, and the waiting time of the processor 1 is increased.

Therefore, in order to prevent the relative increase in the access time of the memory device 3 due to the speeding up of the processor 1, the memory device 3 must also be speeded up, and the control devices of the memory device 3 must be modified for speeding up.

This phenomenon occurs especially between the connection medium 2 and the storage device 3, especially when the connection medium 2 between the processor 1 and the storage device 3 has a synchronous protocol.

That is, when the speed of the connection medium 2 is improved, the inside of the memory device 3 must be modified as a whole for efficient performance.

Next, FIG. 2 schematically shows a plurality of processors 1a... 1n sharing a connection medium 2 in a general multiprocessor system.

Therefore, when each processor 1a… 1n is a multiprocessor system sharing one or more storage devices 3a… 3m, the connection due to the speed difference between the processors 1a… 1n and the storage devices 3a… 3m This causes a problem that the occupancy rate of the medium 2 is increased.

That is, the connection medium 2 continues to be occupied until the storage device 3a… 3m of one of the processors 1a… 1n is secured, or the connection medium 2 is reoccupied in the order of release, release, and release. The attempt must be repeated. In this case, the connection medium 2 is occupied for a simple wait or retry, which is not useful, and becomes a problem in improving the performance of the entire system.

Therefore, in order to solve the above problems, the present invention provides an effective asynchronous operation between the processors 1, 1a ... 1n and the memory devices 3, 3a ... 3m or the connection medium 2 and the memory devices 3, 3a ... 3m. Approach provides flexibility in improving the individual operating speeds of each component such as processor (1,1a… 1n), connection medium (2), storage devices (3,3a… 3m), The goal is to provide an asynchronous storage approach that reduces occupancy.

Therefore, the configuration of the present invention will be described with reference to FIG. 3 in order to achieve the above object.

First, the input interface 4 performs the function of observing the operation of the connecting medium 2 and accepting the request. Also, when a plurality of storage devices 3a ... 3m are used, the input interface 4 determines whether it is its request through the address information. A differentiating function is performed, and an input request to the input queue 5 is generated.

The input queue 5 temporarily stores the input request generated by the input interface 4 in a first-in-first-out (FIFO) operation and stores the storage device in the storage controller 6. (7) is informed that the difference in response speed between the storage device 7 access request from the connecting medium 2 and the storage device 7 is buffered.

At this time, the storage device controller 6 controls the reading and writing of the storage device 7 in accordance with a request stored in the input queue 5 as the storage device 7 which is the actual control object, and at the time of controlling the read operation. When the response of (7) is completed, an input request to the output queue 8 is generated.

In addition, the memory device 7 is configured to use a memory device such as a DRAM as a part for performing an actual response under the control of the memory controller 6.

The output queue 8 stores, in FIFO operation, the response of the storage device 7 to the read request in response to the input request of the storage controller 6, and informs the output interface 9 that there is data to be transmitted.

When it is confirmed that there is data to be transmitted in the output queue 8, the data is transmitted in response to the read request through the connection medium 2.

The asynchronous access memory device of the present invention having the above-described configuration includes a memory controller for processing an input interface 4 and an input queue 5 for receiving a request from the connection medium 2, and an actual access request. (6) and memory (7), and output queue (8) and output interface (9), which process the response to read requests, operate independently of the processor (1, 1a ... 1n), The connecting medium 2 is configured to provide flexibility in changing the operating speed of the storage devices 3, 3a ... 3m and the like and reduce the occupancy of the connecting medium 2.

Accordingly, the detailed operation will be described with reference to FIG. 4, which is a flow chart summarizing the operation of the asynchronous storage approach.

First, the operation of the write request will be described.

A step (a) of sensing the request signal from which the input interface 4 is input from the outside through a medium connected to the input interface 4 and an asynchronous input queue 5 by the detection of the input interface 4. When the input queue 4 is filled to determine whether the state of the input queue 5 is full, the input interface 4 accesses the storage device 3, 3a, 3m, 7 through the connection medium 2. (B) requesting a retry to the eternal processors 1, 1a ... 1n, and on the other hand, if the state of the input queue 5 is not filled by this determination, regardless of the state of the storage controller 6 Storing the request from the input interface 4 in the input queue 5 in FIFO operation and simultaneously informing the storage controller 6 that there is a request to be processed, wherein the input interface 4 ) And the input queue (5) are the parts that accept requests from the connection medium (2). If not filled, the status of the input queue (5), which can accommodate a memory device (3,3a ... 3m) (7) access requirements that occur continuously.

In addition, it is determined whether the input queue 5 is empty, and if it is empty, waiting for input request to be filled in the input queue 5 again (d), and in this step (d), the input queue 5 If is not empty, the storage controller 6 reads the input request stored in the input queue 5 to control reading and writing of the storage device 7 and the input request of the input queue 5. A step (f) of determining whether is a read or a write, and a step of generating a control signal for writing data to the storage device (7) when a write operation is requested by the judgment (f) (g). In this case, when writing to the storage device 7 is completed, the storage controller 6 reads out a new request from the input queue 5 and processes it.

These steps are constituted so that the operation of write request is performed.

Meanwhile, the operation of the read request will be described below.

The operation for the read request is the same from the steps (a) to (e) in the operation for the write request, and the control required by the storage controller 6 to perform the read request in the determination step (f). A signal is generated to perform the reading (h) of the storage device 7.

And (i) generating an input request to the asynchronous output queue 8 according to the control signal of the storage controller 6 and waiting until it is empty if it is full, wherein the storage controller 6 of the storage controller 6 After confirming the input request to the output queue 8 by the control signal, the new request is read again from the performing step (c) of the input queue 5 regardless of the state of the output interface 9.

However, if the output queue 8 is not full, step (j) in which the response of the storage device 7 to the read request of the storage controller 6 is stored in a FIFO operation, and the output queue 8 Is judged by the output interface 9 if empty is empty or waits until the output queue 8 is filled; if the output queue 8 is not empty, the output interface 9 outputs the output queue. (1) reading out data from (8), and when the transmission of the read data is completed through the output interface 9, it is again checked whether the state of the output queue 8 is empty as a feedback loop, If the transfer is not complete, another read request operation is performed including steps (m) which repeat until the transfer is complete.

The present invention according to the above steps provides a flexibility in the use of the processor and the connection medium by operating the memory asynchronously with the operating speed of the processor and the transmission speed of the connection medium, and any connection medium is shared multiple The use of asynchronous I / O queues in the processing system reduces the occupancy of the connection medium, thereby improving the performance of the system.

Claims (3)

(A) detecting a request signal input from the outside of the input interface 4 through a medium connected with the input interface 4, and inputting to the asynchronous input queue 5 by detecting the input interface 4; Generating a request to determine whether the state of the input queue 5 is full and refilling the input interface 4 to the processor requesting access to the storage device 7 via the connection medium 2; b), if the state of the input queue 5 is not filled, step (c) in which the input request is stored in the input queue 5 in a FIFO operation, and if the input queue 5 is empty to determine whether it is empty, (D) iteratively determining until the input request is filled in the input queue 5 again, and if the input queue 5 is not empty in this step (d), the storage controller 6 causes the input queue 5 to Reads and writes the memory device (7) Step (e), a step (f) for determining whether the input request of the input queue (5) is a read or a write, and a storage device (7) if there is a request for a write operation by this determination (f). Write data to the memory controller 6, and the storage controller 6 reads a new request from the input queue 5 again, and if there is a request for a read operation in the judgment f, the storage controller 6 Step (h) of generating a control signal of a read request and reading from the storage device 7, and if the storage controller 6 generates and fills an input request signal to the asynchronous output queue 8, Waiting until empty (i), and if the output queue 8 is not full, step (j) in which the storage device's response to the read request of the storage controller 6 is stored in a FIFO operation; It is determined by the output interface 9 that the output queue 8 is empty or empty. (K) waiting until the output queue 8 is filled; if the output queue 8 is not empty, the output interface 9 reads data from the output queue 8; When the transfer of the read data is completed through the output interface 9, it is again checked whether the state of the output queue 8 is empty, and if the transfer is not completed, the step is repeated until the transfer is completed (m). Asynchronous storage access method comprising a. 2. A method according to claim 1, characterized in that the input and output interfaces (4) (9) operate independently of the state of the storage controller (6). 2. A method according to claim 1, characterized in that the storage controller (6) responds to a request from the input interface (4) regardless of the state of the output interface (9).