KR0119905B1 - Multi-processor system memory management - Google Patents

Abstract

A method for controlling multi-stage input que used at a multi processor system memory is disclosed. The system comprises an interface(8) receiving an address bus information and a data bus information; a checking unit(8) for determining the input address and the input data are normal or not; an input que controller(10) for controlling the input of the information according to the output from the checking unit(8); and a memory system(5,6,7) for determining the access between a DRAM controller(14) and a DRAM array(15) by using a multi address que(11) and a multi-data que(12).

Description

How to Control the Multiple Input Queues Used for Memory in Multiprocessor Systems

1 is a schematic diagram of a multiprocessor system using a shared bus.

2 is a configuration diagram of a memory device using a queue.

3 is a control timing diagram of an input queue when read.

4 is a control flow diagram of an input queue in case of reading.

5 is a control timing diagram of an input queue in the case of a single write.

6 is a control flow diagram of an input queue in the case of a single write.

7 is a control timing diagram of an input queue when a block is written.

8 is a control flowchart of an input queue when a block is written.

The present invention relates to a method for controlling a multi-stage input queue for use in a memory device of a multiprocessor system using a shared bus.

As shown in FIG. 1, a multiprocessor system using a shared bus includes a plurality of processors 1, 2, ..., 3 for executing a program, and a plurality of memory autonomouss 5, 6, for storing programs and data. ..., 7) and a bus 4 which is an information path therebetween.

Memory elements that make up memory devices and the speed of memory requests (read from or write to memory devices) required by multiple processors (1,2, ..., 3) in a multiprocessor system based on the bus of the pipeline protocol Processors that do not receive the requested service (read from memory device or write to memory device) from the memory device are retried due to the difference in response speed of DRAM.

The result is a load on the bus 4, which is a shared resource, which adversely affects the performance of the overall system.

For this reason, memory devices (figure 2) that use queues to buffer the difference between the processor's memory request rate and the memory device's DRAM response rate can reduce the number of retries of the processors and enable efficient use of the shared resource bus. It is a structure.

An object of the present invention is to provide a method of controlling an input queue which speeds up a response speed of a memory device 5, 6, ..., 7 in a bus-based multiprocessor system.

To this end, in the present invention, information that is not valid for the input queues 11, 12, 13 of the memory device (FIG. 2) in which the input queue controller 10 is configured in multiple stages (the validity checker 9 has an input address and input data). Information judged to be information is not inputted and information that is determined to be later valid among the information already input to the queues 11, 12 and 13 (the DRAM controller 14 outputs the error location information of the error queue 13). The speed of the response of the memory devices 5, 6,..., 7 is increased through a control method that the DRAM controller 14 invalidates before the DRAM array 15 approaches.

The validity checker 9 determines the input address and the input data information as invalid information as follows.

When the validity checker 9 detects an error while the address bus information and the data bus information transmitted by the processor pass through the bus 4 and the data requested by the processor 1 is stored in the memory devices 5, 6,... If not, the validity checker 9 of the memory devices 5, 6, ..., 7 determines this request as invalid information if it is in the internal memory of the other processor 2.

FIG. 2 is a portion corresponding to the memory devices 5, 6, ..., 7 of FIG. 1 and shows a configuration of a memory device using a queue buffering a difference between a memory request rate of a processor and a DRAM response speed of the memory device.

The memory requests of the processors in FIG. 1 are divided into reads which get information from the memory devices 5, 6, ..., and writes that write information to the memory devices 5, 6, ..., 7.

Writes can be divided into two cases: a single write that writes data of the bus 4 data width size and a block write that writes four times the information of the bus 4 data width size at a time.

The memory request information (address bus information and data bus information of FIG. 2) of the processors 1, 2, ..., 3 corresponds to the control of the input queue controller 10 through a bus interface 8. The information is stored in the input queues 11, 12, and 13 and is read from or written to the DRAM array 15 under the control of the DRAM controller 14.

[A] In case of reading, control timing and control of input queue are as follows.

First, when the processors (1, 2, ..., 3) read the information stored in the memory devices, the input queue is read while referring to FIGS. 3 and 4 showing control timing of the input queue and its control process, respectively. It demonstrates how to control.

Using the information indicating the memory requests of the processors, namely the address bus information 17, the bus interface 8 recognizes that the read operation is performed and the validity checker 9 checks whether the address bus information transmitted by the processor is valid. (27).

[A-1] Address bus information is valid.

If the address bus information is valid (21), at the rising edge of the address input control 20, the input address 18, IAO is put into the address queue 11 and the control ends (22, 30, 31). .

[A-2] Address bus information is invalid.

If the address bus information is invalid (23), the rising edge of the address input control 20 is prevented from occurring (23) and control is terminated without putting the input addresses 18 and IA1 into the address queue 11 (24). , 28,29).

If the address bus information is invalid, the input queue controller 10 does not execute access to the DRAM array 15 corresponding to the input addresses 18 and IA1 because the read operation requested by the processor is invalid in the memory device. Do not.

[B] The following describes the control timing and control of the input queue in the case of a single write.

A method of controlling an input queue of a memory device in the case of a single write will be described with reference to FIG. 5 which is a control timing diagram of the input queue and FIG. 6 which is a control flowchart.

Using the information representing the memory requests of the processors, namely address bus information 33, the bus interface 8 recognizes that it is a single write operation and the validity checker 9 checks whether the address bus information sent by the processor is valid. (61).

[B-1] Address bus information and data bus information are valid.

When the address bus information is valid (43), the input address 34 (IA0) is put into the address queue 11 (44, 64) at the rising edge of the address input control 36.

Valid validator 9 then checks if the data bus information 37 sent by the processor is valid (65).

If the data bus information is valid (45), the input data 38, ID0 is put into the data queue 12 (46, 68) at the rising edge of the data history control 40, and the error position 41, IE0 at the same point in time. ) Is set to the 4-bit binary information 0000 (47) and the error position 41, IE0 is put in the error queue 13 at the rising edge of the error input control 42 (48, 49, 68, 69). .

Making the error location 41, IE0 into 4-bit binary information 0000 indicates that the input address 34, IA0 entered into the address queue 11 and the input data 38, ID0 entered into the data queue 12 are valid information. This is to inform the controller 14.

[B-2] The address bus information is invalid.

If the address bus information is invalid (50), the rising edge of the address input control 36 is prevented from occurring so that the history address 34, IA1 is not put in the address queue 11 and the data bus information is valid or not. The rising edge of the data input control 40 is prevented from being generated (52), and control is terminated without putting the input data 38, ID1 into the data queue 12 (53) (51, 62, 63).

If the address bus information is not valid, the single write operation requested by the processor is not valid in the memory device, so the input queue controller 10 controls the input addresses 34 and IA1 not to be entered into the address queue 11. The input data 38, ID1 is controlled not to be input to the data queue 12 regardless of whether the data bus information is valid. As a result, the DRAM controller 14 does not execute access to the DRAM array 15 corresponding to the input addresses 34 and IA1.

[B-3] The address bus information is valid and the data bus information is invalid.

If the address bus information is valid (54), input addresses 34, IA2 are placed in the address queue 11 at the rising edge of the address input control 36 (55,64).

Valid validator 9 then checks if the data bus information 37 sent by the processor is valid (65).

If the data bus information is invalid (56), the rising edge of the data input control 40 is prevented from occurring so that the input data 38, ID2 is not put in the data queue 12 (57, 66) at the same time. With the error position 41, IE2 as the four-bit binary information 0001 (58), the error position 41, IE2 is put in the error queue 13 at the rising edge of the error input control 42, and the control is terminated (59, 60,66,67).

Making the error location 41, IE2 into 4-bit binary information 0001 is to inform the DRAM controller 14 that the input address 34, IA2 entered in the address queue 11 is invalid information.

The DRAM controller 14 looks at the 4-bit binary information 0001 of the error position 41, IE2, and recognizes that the input addresses 34 and IA2 previously entered into the address queue 11 are invalid information. The DRAM array 15 is not accessed by the IA2) information.

Considering that it takes the most time to access the DRAM, which is a memory device constituting the memory devices, the control method of allowing only the actual information to access the DRAM array 15 improves the response speed of the memory device.

[C] The following describes the control timing and control of the input queue when writing a block.

In the case of block writing, a method of controlling an input queue of a memory device will be described with reference to FIG. 7 which is a control timing diagram of the input queue and FIG. 8 which is a control flowchart.

Using the information indicating the memory requests of the processors, namely the address bus information 71, the bus interface 8 recognizes that it is a block write operation and the validity checker 9 checks whether the address bus information sent by the processor is valid ( 107).

[C-1] When address bus information and data bus number 4 are valid.

When the address bus information is valid (81), the input address 72 (IA0) is put into the address queue 11 (82,110) at the rising edge of the address input control 74.

The validity checker 9 then checks (111) whether the first data bus information 75, BD00 sent by the processor is valid.

If the first data bus information is valid (83), put the input data 76, ID00 into the data queue 12 (84, 114) at the rising edge of data input control 78.

The validity checker 9 then checks (115) whether the second data bus information 75, BD01 sent by the processor is valid.

If the second data bus information is valid (85), put the input data 76, ID01 into the data queue 12 at the rising edge of data input control 78 (86, 118).

The validity checker 9 then checks whether the third data bus information 75, BD02 sent by the processor is valid (119).

If the third data bus information is valid (87), put the input data 76, ID02 in the data queue 12 at the rising edge of data input control 78 (88, 122).

The validity checker 9 then checks whether the fourth data bus information 75 (BD03) transmitted by the processor is valid (123).

If the fourth data bus information is valid (89), put the input data 76, ID03 into the data queue 12 (90, 126) at the rising edge of data input control 78.

At the same time, the error position 79, IE0 is set as 4-bit binary information 0000 (91) and the error position 79, IE0 is put in the error queue 13 at the rising edge of the error input control 80, and the control ends. (92,93,126,127).

Making the error location 79, IE0 into the 4-bit binary information 0000 means the input address 72, IA0 entered into the address queue 11 and the input data 76, ID00, ID01, ID02, ID03 entered into the data queue 12. ) Is to inform the DRAM controller 14 that is valid information.

[C-2] The address bus information is invalid.

If the address bus information is invalid (94), the rising edge of the address input control 74 is prevented from occurring so that the input address 72 (IA1) is not put in the address queue 11 and the data bus information is valid. The rising edge of the data input control 78 is prevented from occurring (96), and the control is terminated without putting the historical data 76, ID10, ID11, ID12, and ID13 into the data queue 12 (97) (95, 108, 109). .

When the address bus information is not valid, the block write operation requested by the processor is not valid in the memory device. Therefore, the input queue controller 10 controls the input addresses 72 and IA1 not to be input to the address queue 11. The input data 76, ID10, ID11, ID12, and ID13 are not input to the data queue 12 regardless of whether the data bus information is valid. Thus, the DRAM controller 14 does not execute access to the DRAM array 15 corresponding to the input addresses 72 and IA1.

[C-3] The address bus information is valid and the data bus information is invalid.

[C-3-1] When the address bus information is valid, the first data bus information is valid and the second data bus information is invalid.

If the address bus information is valid (98), put the input addresses (72, IA2) into the address queue (11) at the rising edge of the address input control (74).

The validity checker 9 then checks (111) whether the first data bus information 75 (BD20) sent by the processor is valid.

If the first data bus information is valid (100), put the input data 76, ID20 into the data queue 12 at the rising edge of data input control 78 (101, 114).

The validity checker 9 then checks (115) whether the second data bus information 75 (BD21) sent by the processor is valid.

If the second data bus information is invalid (102), the rising edge of the data input control 78 does not occur so that the input data 76, ID21 is not put in the data queue 12 (103, 116) and at the same time error. With the position 79, IE2 as 4-bit binary information 0010 (104), the error position 79, IE2 is put in the error queue 13 at the rising edge of the error input control 80 (105, 106, 116, 117).

If the second data bus information is not valid, the third and fourth data bus information are not put in the data queue regardless of whether the third and fourth data bus information 75, BD22, and BD23 are valid.

Making the error location 79, IE2 into 4-bit binary information 0010 means that the input address 72, IA2 entered into the address queue 11 and the first input data 76, ID20 entered into the data queue 12 are invalid. This is to inform the DRAM controller 14 of the information.

The DRAM controller 14 looks at the 4-bit binary information 0010 of the error location 79, IE2, and input address 72, IA2 previously entered into the address queue 11 and the first input data 76 entered into the data queue 12. Recognizing that ID20 is invalid information does not access the DRAM array 15 with input address 72, IA2 information.

In consideration of the fact that it takes the most time to access the DRAM, which is a memory device constituting the memory devices, the control method of accessing the DRAM array 15 to only the actual valid information may increase the response speed of the memory devices 5, 6, and 7. Do it quickly.

[C-3-2] When address bus information is valid and data bus information is invalid.

The number of cases where the address bus information is valid and the data bus information is invalid is that the address bus information described in [D-3-1] is valid, the first data bus information is valid, and the second data bus information is invalid. Including cases. The block diagram of FIG. 8 will be described below with reference to a control flowchart of an input queue.

The checker 9 checks whether the first data bus information transmitted by the processor is valid (111).

If the first data bus information is not valid, the first input data is not put in the data queue 12 (112), and at the same time, the error position information is set to the 4-bit binary information 0001 (12), and the error queue 13 is entered. Control is terminated (113).

If the first data bus information is invalid, the second, third and fourth data bus information are not put in the data queue regardless of whether the second, third and fourth data bus information is valid later.

Before the DRAM controller 14 approaches the DRAM controller 15, the DRAM controller 14 informs the DRAM controller 14 that the input address 110 entered into the address queue 11 is invalid information to convert the error location information into 4-bit binary information 0001. This is for use as a control means for invalidating invalid information.

If the third data bus information is invalid, the third input data is not put into the data queue 12 (120), and at the same time, the error position information is set to the 4-bit binary information 0100 (120), and the error queue 13 Control is terminated (121).

If the third data bus information is invalid, the fourth data bus information is not put in the data queue regardless of whether the fourth data bus information is valid later.

The input address 110 entered into the address queue 11 and the first input data 114 and the second input data 118 entered into the data queue 12 to invalidate the error location information into 4-bit binary information 0100 are invalid information. This is to inform the DRAM controller 14 that the DRAM controller 14 is used as a control means for invalidating information that is not valid before the DRAM array 15 approaches.

If the fourth data bus information is not valid, the fourth input data is not put in the data queue 12 (124), and at the same time, the error position information is assumed to be 4-bit binary information 1000 (124), and the error queue 13 is entered. And control ends (125).

Making the error location information 4 bit binary information 1000 is the first input data 114 entered into the address queue 11 and the first input data 114 entered into the data queue 12, the second input data 118 and the third input data ( This is to inform the DRAM controller 14 that 122 is invalid information so that the DRAM controller 14 can be used as a control means for invalidating invalid information before the DRAM array 15 approaches.

Claims (1)

A bus interface 8 that receives address bus information and data bus information on the bus representing memory request information (read, single write, block write) of the processors, and the validity of the input address and input data entered through the bus interface 8. Input information, input data, and error location information are inputted into the validity checker 9 for checking whether there is a validity, and the multistage address queue 11, the multistage data queue 12, and the multistage error queue 13 according to the validity check result. The DRAM controller 14 is connected to the DRAM array 15 by using the input queue controller 10 for controlling whether or not to output the multi-stage address queue 11, the multi-stage data queue 12, and the multi-stage error queue 13. A method for controlling the multi-stage input queues in a multiprocessor system based on a pipelined protocol bus having a memory device for determining whether to access the Information that is not valid by the inspection of the inspector 9 is not input to the input queues 11, 12, 13 or is determined to be later invalid among information already input to the input queues 11, 12, 13; The control method of the multi-stage input queue used in the memory of the multiprocessor system, characterized in that for improving the response speed of the memory device through a control method to invalidate.