JPH09293904A - Led package - Google Patents
Led packageInfo
- Publication number
- JPH09293904A JPH09293904A JP10729396A JP10729396A JPH09293904A JP H09293904 A JPH09293904 A JP H09293904A JP 10729396 A JP10729396 A JP 10729396A JP 10729396 A JP10729396 A JP 10729396A JP H09293904 A JPH09293904 A JP H09293904A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- led
- electrode terminal
- electrode
- led device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はLEDを支持し電力を供
給するLEDパッケージに係り、特に、発光出力に優れ
たLEDパッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED package which supports an LED and supplies electric power, and more particularly to an LED package which is excellent in light emission output.
【0002】[0002]
【従来の技術】看板、広告塔等の平面型ディスプレイに
はLEDが使用されている。LEDディスプレイには、
LEDチップを基板上に載置して電極を接続し、樹脂で
モールドしたものとが知られ、例えば、基板に直接LE
D素子(ベアチップ)を実装するダイレクトボンディン
グタイプ、あるいは、図1に示すようなチップタイプL
EDを基板に表面実装するものがある。これらのLED
ディスプレイは、LED素子を支持し、電力を供給して
点灯させるためのLEDパッケージが必要である。2. Description of the Related Art LEDs are used in flat displays such as signboards and advertising towers. LED display has
It is known that an LED chip is placed on a substrate, electrodes are connected to the substrate, and the resin is molded. For example, LE is directly mounted on the substrate.
Direct bonding type for mounting D element (bare chip) or chip type L as shown in FIG.
There is one in which the ED is surface-mounted on the substrate. These LEDs
The display needs an LED package for supporting the LED element and supplying electric power to light the LED element.
【0003】従来より、LEDパッケージは、導電体層
14および電極端子15の導体部分はAu、Ag等の貴
金属の被覆が一様に被覆されていた。これは、主とし
て、導体部分の酸化を防ぐことを目的としていた。Conventionally, in the LED package, the conductor portions of the conductor layer 14 and the electrode terminals 15 are uniformly coated with a noble metal such as Au or Ag. This was mainly intended to prevent oxidation of the conductor portion.
【0004】電極端子15は給電回路との電気的接続を
とるために、半田付が通常施される。それで強い半田付
強度を得るためには、電極端子15は半田の濡れ性の良
いAuで被覆することが実装の信頼性を高めるのに必要
であった。The electrode terminals 15 are usually soldered in order to make an electrical connection with a power supply circuit. Therefore, in order to obtain a strong soldering strength, it was necessary to coat the electrode terminals 15 with Au having good solder wettability in order to improve the reliability of mounting.
【0005】Auで導体部分を被覆するには、通常電気
メッキ法が適用され、LED素子12の電極13と接続
される導電体層14も同時にAuメッキされる。ところ
が、導電体層14がAuメッキされた場合、実装するL
ED素子12の発光色が青色、青緑色、或いは緑色の場
合、発光出力が低下する欠点がある。特に青色のLED
の場合、約30%も出力が低下してしまう。これはAu
の被膜は全可視域において、一様な反射率を持たず、特
に、青色、青緑色、或いは緑色の発光を吸収するような
赤みを帯びた体色を持っているためである。Auの分光
反射率を表1に示す。この表から、反射率は波長が60
0nm以上で91.9%以上であり、大部分の光を反射
するが、これ以下の波長では、吸収が大きくなり、50
0nmでは反射率は50%以下となり、このことはAu
は黄色より短波長の光を大きく吸収することを示してい
る。To coat the conductor portion with Au, an electroplating method is usually applied, and the conductor layer 14 connected to the electrode 13 of the LED element 12 is also Au-plated at the same time. However, if the conductor layer 14 is plated with Au, the L
When the emission color of the ED element 12 is blue, blue green, or green, there is a drawback that the emission output is reduced. Especially blue LED
In the case of, the output is reduced by about 30%. This is Au
This is because the coating (1) does not have a uniform reflectance in the entire visible range, and in particular, has a reddish body color that absorbs blue, blue-green, or green light emission. Table 1 shows the spectral reflectance of Au. From this table, the reflectance is 60
It is 91.9% or more at 0 nm or more, and most of the light is reflected, but at wavelengths less than this, the absorption is large and 50
At 0 nm, the reflectance is 50% or less, which means that
Indicates that light having a wavelength shorter than that of yellow is largely absorbed.
【0006】[0006]
【表1】 [Table 1]
【0007】そこで、導電体層14と電極端子15から
なる導体部分の表面全体に銀白色系の貴金属として一般
的なAgをメッキした場合、LEDからの青色、青緑
色、及び緑色発光は吸収されず、殆ど反射され、Auを
使用した場合のような発光出力低下はない。しかし、A
gは半田の濡れ性が悪く、電極端子15にAg被覆した
場合、給電回路との半田付強度が弱くなり、給電回路基
板への実装の信頼性が悪くなるという欠点があった。Therefore, when Ag, which is generally used as a silver-white noble metal, is plated on the entire surface of the conductor portion consisting of the conductor layer 14 and the electrode terminal 15, blue, blue-green, and green light emission from the LED is absorbed. However, there is almost no reflection, and there is no reduction in light emission output as in the case of using Au. However, A
g has poor solder wettability, and when Ag is coated on the electrode terminal 15, the soldering strength to the power supply circuit is weakened, and the reliability of mounting on the power supply circuit board deteriorates.
【0008】[0008]
【発明が解決しようとする課題】従って、本発明はこの
ような事情に鑑みて成されたものであり、青色、青緑
色、あるいは緑色発光LEDチップを実装した場合、発
光出力低下の少なく、また給電回路基板への半田付によ
る実装の信頼性の高いLEDパッケージを提供すること
を目的とする。SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above circumstances, and when a blue, blue-green or green light emitting LED chip is mounted, a decrease in light emission output is small, and It is an object of the present invention to provide an LED package having high reliability of mounting by soldering to a power supply circuit board.
【0009】[0009]
【発明を解決するための手段】本発明者はセラミックス
LEDパッケージに形成された導電体層の表面と、電極
端子の表面に、異種の貴金属を選択的に被覆することで
課題を解決できる事を見いだし本発明を解決するに至っ
た。Means for Solving the Problems The present inventor can solve the problem by selectively coating different kinds of precious metals on the surface of a conductor layer formed on a ceramics LED package and the surfaces of electrode terminals. The present invention has been solved and the present invention has been solved.
【0010】すなわち、本発明のLEDパッケージは、
支持部材表面にLED素子の電極へ電力を供給する導電
体層と、支持部材裏面に外部から電力を供給される電極
端子を備え、電極端子が導電体層と電気的に接続されて
いるLEDパッケージにおいて、前記LED素子の発光
ピーク波長は600nm以下であり、前記導電体層の表
面には銀白色系の貴金属が被覆され、前記電極端子表面
にはAuが被覆されていることを特徴とする。That is, the LED package of the present invention is
An LED package in which a conductor layer for supplying electric power to the electrodes of the LED elements is provided on the surface of the supporting member and an electrode terminal for supplying electric power from the outside is provided on the rear surface of the supporting member, and the electrode terminals are electrically connected to the conductor layer. The light emitting peak wavelength of the LED element is 600 nm or less, the surface of the conductor layer is coated with a silver-white noble metal, and the surface of the electrode terminal is coated with Au.
【0011】また、本発明のLEDパッケージは、LE
D素子の電極と導電体層がAu線により電気的に接続さ
れる構造のLEDパッケージにおいて、前記導電体層は
Agにより被覆されていることを特徴とする。The LED package of the present invention is LE
In the LED package having a structure in which the electrode of the D element and the conductor layer are electrically connected by an Au wire, the conductor layer is covered with Ag.
【0012】[0012]
【発明の実施の形態】図1を参照して本発明のLEDパ
ッケージを説明する。支持部材11の表面にLED素子
12の電極13に電力を供給できる導電体層14を形成
し、支持部材11の裏面に外部の給電回路基板から電力
を供給される電極端子15を形成し、電極端子15は導
電体層14と電気的接続部16により接続されている。
そして、導電体層14の表面には銀白色系の貴金属が被
覆され、前記電極端子15の表面にはAuが被覆されて
いる。図1に示すLED素子の発光ピーク波長は600
nm以下である。BEST MODE FOR CARRYING OUT THE INVENTION An LED package of the present invention will be described with reference to FIG. An electric conductor layer 14 capable of supplying electric power to the electrode 13 of the LED element 12 is formed on the front surface of the supporting member 11, and an electrode terminal 15 to which electric power is supplied from an external power supply circuit board is formed on the rear surface of the supporting member 11, and the electrode The terminal 15 is connected to the conductor layer 14 by the electrical connection portion 16.
The surface of the conductor layer 14 is coated with a silver-white noble metal, and the surface of the electrode terminal 15 is coated with Au. The emission peak wavelength of the LED element shown in FIG. 1 is 600.
nm or less.
【0013】支持部材とは、LED素子を所望の場所に
配置して電気的に接続するために用いられるものであ
り、図1に示すようなチップタイプのLEDの基板でも
よいし、LED素子をマトリックス状に多数個実装する
ダイレクトボンディングタイプのモジュール基板でもよ
い。材質は機械的強度が強く、熱変形の少ないものが好
ましい。具体的には、セラミックス、ガラス、アルミニ
ウム合金等を用いたプリント基板、プラスチックが利用
できる。The support member is used for arranging and electrically connecting the LED element at a desired place, and may be a chip type LED substrate as shown in FIG. 1 or the LED element. A direct bonding type module substrate in which a large number are mounted in a matrix may be used. It is preferable that the material has high mechanical strength and little thermal deformation. Specifically, a printed circuit board made of ceramics, glass, an aluminum alloy or the like, or plastic can be used.
【0014】発光ピーク波長が600nm以下に発光す
るLED素子は、特に組成による限定はない。液層成長
法や、MOCVD法により、基体上にGaAlN、Zn
S、ZnSe、SiC、GaP、GaAlAs、AlI
nGaP、InGaN、GaN、AlInGaN等の半
導体を発光層として形成させた物が用いられる。The LED element that emits light having an emission peak wavelength of 600 nm or less is not particularly limited by its composition. GaAlN, Zn on the substrate by the liquid layer growth method or the MOCVD method.
S, ZnSe, SiC, GaP, GaAlAs, AlI
A material in which a semiconductor such as nGaP, InGaN, GaN, or AlInGaN is formed as a light emitting layer is used.
【0015】貴金属とは、金(Au)、銀(Ag)、及
び白金族元素であるルテニウム(Re)、ロジウム(R
h)、パラジウム(Pd)、オスミウム(Os)、イリ
ジウム(Ir)、白金(Pt)であり、これらの合金で
あってもよい。また、銀白色系の貴金属とは、銀(A
g)及び白金族元素であり、これらの合金であってもよ
い。Noble metals include gold (Au), silver (Ag), and platinum group elements ruthenium (Re) and rhodium (R).
h), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), and alloys thereof may be used. A silver-white noble metal is silver (A
g) and platinum group elements, and may be alloys thereof.
【0016】図1に示すようなLED素子12の電極1
3と導電体層14がAu線17により電気的に接続され
る構造のLEDパッケージにおいて、導電体層は銀白色
系の貴金属の内Agにより被覆されていることが好まし
い。それはAgの融点は962℃で、Auの融点の10
64℃と近似しているため、ワイヤーボンド時に両方の
金属が融け、理想的な融着が起こるからで、強固なワイ
ヤーボンディングが得られ、Au線の剥がれ不良のほと
んどないLEDを得ることができる。また、Agは銀白
色系の貴金属であるので、導電体層がAg被覆されてい
ることで、LED素子からの青色、青緑色、及び緑色の
発光を効率よく反射することができる。The electrode 1 of the LED element 12 as shown in FIG.
In the LED package having a structure in which 3 and the conductor layer 14 are electrically connected by the Au wire 17, it is preferable that the conductor layer is covered with Ag among the silver-white noble metals. It has a melting point of 962 ° C. for Ag and 10 for the melting point of Au.
Since it is close to 64 ° C., both metals are melted at the time of wire bonding, and ideal fusion occurs, so that strong wire bonding can be obtained and an LED having almost no Au wire peeling defect can be obtained. . In addition, since Ag is a silver-white noble metal, Ag is coated on the conductor layer, so that blue, blue-green, and green light emitted from the LED element can be efficiently reflected.
【0017】また、本発明は図2に示すように、LED
素子22の一対の電極23と、支持部材21の表面に設
けられたAg被覆された導電体層24を向かい合わせ
て、導電性のろう材27を介して接続するフリップチッ
プ接続する場合にも十分に有効である。この場合には融
着の必要がないので、導電体層に被覆されるのはAgで
なくとも、他の銀白色系の貴金属であれば高い反射効果
が期待できる。電極端子25は給電回路と接続され、電
力を電気的接続部26を介して導電体層24に供給す
る。The present invention also provides an LED as shown in FIG.
Sufficient for flip-chip connection in which the pair of electrodes 23 of the element 22 and the Ag-covered conductor layer 24 provided on the surface of the support member 21 are opposed to each other and are connected via the conductive brazing material 27. Is effective for. In this case, since fusion is not necessary, even if Ag is not coated on the conductor layer, a high reflection effect can be expected if it is another silver-white noble metal. The electrode terminal 25 is connected to a power supply circuit and supplies electric power to the conductor layer 24 via the electrical connection portion 26.
【0018】[0018]
【実施例】以下に、支持部材がアルミナを主成分としセ
ラミックスであり、導電体層の表面をAgで、電極端子
の表面をAuで被覆されたLEDパッケージの作製を例
に挙げて説明する。EXAMPLE An LED package in which the supporting member is a ceramic containing alumina as a main component, the surface of the conductor layer is covered with Ag, and the surfaces of the electrode terminals are covered with Au will be described as an example.
【0019】アルミナ粉末に溶剤、分散剤、バインダ
ー、および可塑剤を加えてスラリー状として、ドクター
ブレード法により、該アルミナスラリーを流出させ、乾
燥し、グリーンシートを得た。グリーンシートの両面の
導体印刷をつなぐ電気的接続部を形成する目的で常法に
従いスルーホールを開け、スクリーン印刷法によりタン
グステンペーストを両面に印刷し、図3に示す表面に最
終的にLEDパッケージの導電体層になる部分34と、
裏面には電極端子になる部分35及び電気的接続部にな
る部分36を形成した。次に、キャビティー39を形成
する隔壁38を形成するために、マトリックス状に孔を
開けたグリーンシートを導電体層側に重ねてプレスし
た。次に、グリーンシートを常法に従い、乾燥、脱脂、
焼結することで、タングステン導体配線が形成されたセ
ラミックス基板を得た。A solvent, a dispersant, a binder, and a plasticizer were added to alumina powder to form a slurry, and the alumina slurry was discharged by a doctor blade method and dried to obtain a green sheet. In order to form an electrical connection that connects the conductor prints on both sides of the green sheet, a through hole is opened according to a conventional method, a tungsten paste is printed on both sides by screen printing, and finally the surface of the LED package shown in FIG. 3 is printed. A portion 34 to be a conductor layer,
A portion 35 to be an electrode terminal and a portion 36 to be an electrical connection portion were formed on the back surface. Next, in order to form the partition walls 38 that form the cavities 39, a green sheet having holes formed in a matrix shape was stacked on the conductor layer side and pressed. Next, the green sheet is dried, degreased,
By sintering, a ceramic substrate having a tungsten conductor wiring formed was obtained.
【0020】貴金属被覆の第一工程では、導電体層にな
る部分34と電極端子になる部分35を同時にAuメッ
キする。Auメッキは次のように行った。セラミックス
基板を脱脂し、タングステン配線部のエッチング、酸活
性、ストライクNiメッキ、光沢Niメッキ、酸活性、
ストライクAuメッキ、光沢Auメッキの順に行い、乾
燥し、導電体層になる部分34と電極端子になる部分3
5にAuメッキした。In the first step of coating the noble metal, the portion 34 which becomes the conductor layer and the portion 35 which becomes the electrode terminal are Au-plated at the same time. Au plating was performed as follows. Degrease the ceramics substrate, etch tungsten wiring, acid activation, strike Ni plating, bright Ni plating, acid activation,
Strike Au plating and bright Au plating are performed in this order, and are dried to form a conductor layer portion 34 and an electrode terminal portion 3.
5 was Au plated.
【0021】貴金属被膜の第二工程では、Auメッキさ
れた電極端子になる部分35を樹脂で全体をマスクし、
マスクされていない部分をAgメッキすることで行っ
た。基板の電極端子になる部分35が形成されている側
のみを樹脂の中に漬け込み、引き上げ乾燥することで、
電極端子側のみに樹脂をマスクしたセラミックス基板を
得る。このマスクを使用することで、電極端子になる部
分35にはAgメッキはされず、導電体層になる部分3
4のみに選択的にAgメッキされる。セラミックス基板
を酸活性し、ストライクNiメッキ、光沢Niメッキ、
酸活性、ストライクAgメッキ、光沢Agメッキの順に
行い、乾燥して、導電体層になる部分34にAgをメッ
キした。In the second step of the noble metal coating, the portion 35 to be the Au-plated electrode terminal is entirely masked with resin,
The unmasked portion was plated with Ag. By immersing only the side of the substrate where the electrode terminal portion 35 is formed in resin, pulling it up and drying it,
A ceramic substrate having a resin mask only on the electrode terminal side is obtained. By using this mask, the portion 35 that becomes the electrode terminal is not Ag-plated, and the portion that becomes the conductor layer 3
Only 4 is Ag plated selectively. Acid activation of ceramics substrate, strike Ni plating, bright Ni plating,
The acid activation, the strike Ag plating, and the bright Ag plating were performed in this order, followed by drying, and the portion 34 to be the conductor layer was plated with Ag.
【0022】樹脂のマスクをとると、導電体層になる部
分34の表面にAgメッキが、電極端子になる部分35
の表面にAuメッキが施されたセラミックス基板が得ら
れた。When a resin mask is taken, Ag plating is applied to the surface of the portion 34 which becomes the conductor layer, and the portion 35 which becomes the electrode terminal.
As a result, a ceramics substrate whose surface was plated with Au was obtained.
【0023】得られたセラミックス基板に窒化物系の高
輝度青色LED素子を接着して、LED素子の電極とA
gがメッキされた導電体層になる部分34をAu線でワ
イヤーボンディングした。得られたセラミックス基板を
各キャビティー39の単位に割り出すことで、図1に示
すようなチップタイプのLEDが得られた。A nitride-based high-intensity blue LED element is adhered to the obtained ceramic substrate, and the electrode of the LED element and A
A portion 34 which becomes a conductor layer plated with g was wire-bonded with an Au wire. By indexing the obtained ceramic substrate into units of each cavity 39, a chip type LED as shown in FIG. 1 was obtained.
【0024】チップタイプLED素子に、駆動電圧Vf
=3.6v、電流20mAの電力を供給し、LEDの波
長450nmにおける相対発光出力を測定した。また、
電極端子の半田付の強度を、半田の剥がし取りに要する
力の相対置として測定する方法により、LEDパッケー
ジの電極端子の半田濡れ性を測定した。結果を表1にま
とめる。A driving voltage Vf is applied to the chip type LED element.
= 3.6v, electric current of 20mA was supplied, and the relative light emission output of the LED at a wavelength of 450nm was measured. Also,
The solder wettability of the electrode terminals of the LED package was measured by a method of measuring the soldering strength of the electrode terminals as a relative position of the force required for removing the solder. The results are summarized in Table 1.
【0025】[比較例1]第一工程で得られたAuメッ
キの後、電極端子になる部分35にAgのメッキをせず
に、窒化物系の高輝度青色LED素子を接着して、LE
D素子の電極とAuメッキされた導電体層になる部分3
4をAu線でワイヤーボンディングした。得られたセラ
ミックス基板を各キャビティー39の単位に割り出すこ
とでチップタイプのLEDが得られた。この得られたチ
ップタイプLEDは図1に示す導電体層14も、電極端
子15も共にAuがメッキされている。このチップタイ
プLEDを実施例1と同じ方法により、発光出力と、半
田濡れ性を測定し結果を表1にまとめた。[Comparative Example 1] After the Au plating obtained in the first step, a high brightness blue LED element of a nitride type is adhered to the portion 35 which will become an electrode terminal without plating Ag, and LE
Portion 3 to be the electrode of D element and the conductor layer plated with Au
4 was wire-bonded with Au wire. A chip-type LED was obtained by indexing the obtained ceramic substrate into units of each cavity 39. In the obtained chip-type LED, both the conductor layer 14 shown in FIG. 1 and the electrode terminals 15 are plated with Au. The emission output and solder wettability of this chip-type LED were measured by the same method as in Example 1, and the results are summarized in Table 1.
【0026】[比較例2]第一工程のAuメッキを省
き、セラミックス基板を脱脂して、第二工程を実施して
Agを導電体層になる部分34と電極端子になる部分に
メッキした。これに窒化物系の高輝度青色LED素子を
接着して、LED素子の電極とAgメッキされた導電体
層になる部分34をAu線でワイヤーボンディングし
た。得られたセラミックス基板を各キャビティー39の
単位に割り出すことでチップタイプのLEDが得られ
た。この得られたチップタイプLEDは図1に示す導体
配線14も、電極端子15も共にAgがメッキされてい
る。このチップタイプLEDを実施例1と同じ方法によ
り、発光出力と、半田濡れ性を測定し結果を表2にまと
めた。[Comparative Example 2] The Au plating in the first step was omitted, the ceramic substrate was degreased, and the second step was carried out to plate Ag on the portions 34 to be the conductor layer and the electrode terminals. A nitride-based high-intensity blue LED element was adhered to this, and the electrode of the LED element and the portion 34 to be the Ag-plated conductor layer were wire-bonded with an Au wire. A chip-type LED was obtained by indexing the obtained ceramic substrate into units of each cavity 39. In the obtained chip type LED, both the conductor wiring 14 shown in FIG. 1 and the electrode terminal 15 are plated with Ag. The emission output and solder wettability of this chip type LED were measured by the same method as in Example 1, and the results are summarized in Table 2.
【0027】[0027]
【表2】 [Table 2]
【0028】表2より本発明の実施例のLEDパッケー
ジを使用したチップタイプLEDは、450nmの波長
における相対発光出力が高く、しかも、LEDパッケー
ジの裏面の電極端子の半田の濡れ性が高く、より信頼性
の高い高密度に実装可能なチップタイプLEDを提供す
ることができる。From Table 2, the chip-type LED using the LED package of the embodiment of the present invention has a high relative light emission output at a wavelength of 450 nm, and the wettability of the solder of the electrode terminals on the back surface of the LED package is high. It is possible to provide a highly reliable chip-type LED that can be mounted at high density.
【0029】[0029]
【発明の効果】以上説明したように、本発明のLEDパ
ッケージは、支持部材表面のLED素子の電極に電力を
供給すべき導電体層に銀白色系の貴金属被覆を行い、支
持部材裏面の外部から電力を供給される電極端子にAu
被覆を選択的に行うことにより、発光ピーク波長が60
0nm以下のLEDからの発光を十分に反射することが
でき、給電回路基板への半田付強度の強い、高効率、高
発光出力のLEDを得ることができる。As described above, in the LED package of the present invention, a silver-white noble metal coating is applied to the conductor layer on the surface of the supporting member to supply electric power to the electrodes of the LED element, and the outer surface of the rear surface of the supporting member is covered. To the electrode terminals that are powered by
The emission peak wavelength is 60 by selectively coating.
It is possible to sufficiently reflect the light emitted from the LED having a wavelength of 0 nm or less, and to obtain the LED having the high soldering strength to the power supply circuit board, the high efficiency, and the high light emission output.
【0030】さらに、LEDチップの電極と導電体層が
Au線により電気的に接続される構造のLEDパッケー
ジにおいては、導電体層の銀白色系の貴金属としてAg
を使用することが最も好ましい。それは、Auの融点
と、導電体層のAgの融点が近似しているために、完全
な融着が起こり、Au線の剥がれによる不良が少なくな
るからである。Further, in an LED package having a structure in which the electrode of the LED chip and the conductor layer are electrically connected by an Au wire, Ag is used as the silver-white noble metal of the conductor layer.
Is most preferably used. This is because the melting point of Au and the melting point of Ag of the conductor layer are close to each other, so that complete fusion occurs and defects due to peeling of the Au wire are reduced.
【図1】LEDパッケージにLED素子を実装したチッ
プタイプLEDの模式断面図FIG. 1 is a schematic cross-sectional view of a chip type LED in which an LED element is mounted on an LED package.
【図2】LEDパッケージにLED素子を実装したチッ
プタイプLEDの模式断面図FIG. 2 is a schematic sectional view of a chip-type LED in which an LED element is mounted on an LED package.
【図3】LEDパッケージを貴金属被覆する一製造過程
を示す模式断面図FIG. 3 is a schematic cross-sectional view showing one manufacturing process of coating an LED package with a noble metal.
11、21・・・・・・支持部材 12、22・・・・・・LED素子 13、23・・・・・・電極 14、24・・・・・・導電体層 15・・・・・・・・・電極端子 16、26・・・・・・電気的接続部 17・・・・・・・・・Au線 18、38・・・・・・隔壁 19、39・・・・・・キャビティー 27・・・・・・・・・導電性ろう材 34・・・・・・・・・導電体層になる部分 35・・・・・・・・・電極端子になる部分 36・・・・・・・・・電気的接続部になる部分 11, 21 ... Support member 12, 22 LED element 13, 23 ... Electrode 14, 24 ... Conductor layer 15 ... .... Electrode terminals 16, 26 ... Electrical connection 17 ... Au wire 18, 38 ... Partition wall 19, 39 ... Cavity 27 ..... Conductive brazing material 34 ..... Part that becomes conductor layer 35 ..... ..... Parts that become electrical connection parts
Claims (2)
を供給する導電体層と、支持部材裏面に外部から電力を
供給される電極端子を備え、電極端子が導電体層と電気
的に接続されているLEDパッケージにおいて、前記L
ED素子の発光ピーク波長は600nm以下であり、前
記導電体層の表面には銀白色系の貴金属が被覆され、前
記電極端子表面にはAu被覆されていることを特徴とす
るLEDパッケージ。1. A support member front surface is provided with a conductor layer for supplying electric power to an electrode of an LED element, and a support member rear surface is provided with an electrode terminal for external power supply, and the electrode terminal is electrically connected to the conductor layer. The LED package
An LED package, wherein the ED element has an emission peak wavelength of 600 nm or less, the surface of the conductor layer is coated with a silver-white noble metal, and the surface of the electrode terminal is coated with Au.
線により電気的に接続される構造のLEDパッケージに
おいて、前記導電体層はAgにより被覆されていること
を特徴とする請求項1に記載のLEDパッケージ。2. The electrode of the LED element and the conductor layer are made of Au.
The LED package according to claim 1, wherein the conductor layer is covered with Ag in an LED package having a structure electrically connected by a wire.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10729396A JPH09293904A (en) | 1996-04-26 | 1996-04-26 | Led package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10729396A JPH09293904A (en) | 1996-04-26 | 1996-04-26 | Led package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09293904A true JPH09293904A (en) | 1997-11-11 |
Family
ID=14455438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10729396A Pending JPH09293904A (en) | 1996-04-26 | 1996-04-26 | Led package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09293904A (en) |
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