JPH09293395A - Method and equipment for checking high-speed memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check a high-speed memory with high efficiency by a simple checking program. SOLUTION: A DRAM 4 represents an EDO (an extended-data-out) DRAM, and outputs two data per one cycle (16 [nsec]). A timing generating section 5 has a double strobe function, and generates two strobe signals per one cycle. An expected-value generating section 7 reads one expected data per one cycle from an expected pattern memory 6, and outputs an expected value to an output from the DRAM 4. The expected-value generating section 7 has a function (an expected-value inversion function), in which the expected value is inverted automatically when the output data of the DRAM 4 is inverted during the cycle. A decision section 8 compares the output data of the DRAM 4 and the expected value of the expected-value generating section 7 when the strobe signal is input, and outputs the result of the comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device inspection, and more particularly to a high speed memory device inspection method and apparatus.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional memory device inspection apparatus. In this figure, the control unit 1 writes the inspection pattern read from the external storage device 3 into the DRAM.
After writing the expected pattern read out from the expected pattern memory 6, the inspection of the DRAM 4 is started.

Then, the timing generator 5'is
A control signal (RAS or CAS) is supplied to M.4, whereby the DRAM.4 outputs the data to the determination unit 8. On the other hand, the expected value generation unit 7 ′ reads expected data (each data forming the expected pattern) from the expected pattern memory 6 and outputs the expected data to the determination unit 8 as an expected value. The determination unit 8 compares the output data of the DRAM 4 with the expected value of the expected value generation unit 7'in response to the strobe signal input from the timing generation unit 5 ', and if they match, "0" (PASS) ), "1" if they do not match
(FAIL) is output.

The memory device inspection apparatus shown in FIG. 4 repeats the above-mentioned operation to inspect all the memory cells of the DRAM.4, accumulates the inspection result in the fail memory 9, and informs the alarm unit 10 when a defective product is found. Will inform you of this. Further, the reference clock generation unit built in the control unit 1 generates a reference clock of 60 [MHz]. Therefore, here, one cycle of the reference clock (1/60
[Second] ≈16 [nsec]) is called “one cycle”.

By the way, in DRAM, there is a high-speed memory capable of outputting continuous data by fixing the level of RAS and sequentially applying CAS. Some of such high speed memories can output data twice in one cycle (16 [nsec]). Therefore, FIG.
When testing such high-speed memory with the device shown in
Two strobe signals are used in one cycle (hereinafter,
This is referred to as a "double strobe function"), whereby the determination unit 8 makes two determinations in one cycle.
That method is possible.

However, in the device shown in FIG. 4, since the read speed of the expected pattern memory 6 does not change, the expected value generator 7'can only read one expected data within one cycle. Therefore, the expected value generator 7 '
As shown in FIG. 6A, the expected value output by is fixed at either the level "0" or "1" within one cycle. Therefore, the conventional memory device inspection apparatus shown in FIG.
It was not possible to test the high speed memory.

As a method for solving the above-mentioned problems, there is a function called "pin link function". FIG. 5 is a block diagram showing a configuration example of a high-speed memory device inspection apparatus using the pin link function. As shown in this figure, in the pin link function, one output pin of the DRAM 4 is connected in parallel to the two decision units 8. Furthermore, each determination unit 8 has
Different expected value generation units 7'are connected to each. As a result, as shown in FIG. 6B, one of the expected value generation unit 7'and the determination unit 8 causes the first half DRA in one cycle.
The determination is performed on the M data, and the other expected value generation unit 7 ′
And the determination unit 8 makes a determination on the DRAM data in the latter half and inspects the high speed memory (DRAM.4).

[0008]

By the way, the high-speed memory device inspection apparatus shown in FIG. 5 has a double configuration (expected) for inspecting one DRAM when compared with the memory device inspection apparatus shown in FIG. The pattern memory 6, expected value generation unit 7'and determination unit 8) are required. Therefore, 1
Set multiple DRAMs in one device and
When the AM is inspected in parallel at one time, the number of devices (DRAM) that can be inspected in parallel at one time is halved, which causes a problem that the inspection efficiency is reduced.

Since the high speed memory device inspection apparatus shown in FIG. 5 has two expected pattern memories 6,
Since the amount of expected patterns stored in the expected pattern memory 6 increases and the mutual relationship between these two expected patterns must be taken into consideration, there is a problem that the inspection program for processing the expected patterns becomes complicated. there were.

The present invention has been made under the above circumstances, and an object thereof is to provide a high-speed memory device inspection method and apparatus capable of highly efficiently inspecting a high-speed memory with a simple inspection program. To do.

[0011]

According to the first aspect of the present invention,
In the high-speed memory device inspection method for inspecting the memory device by comparing each output data of a memory device that outputs a plurality of data in one cycle of a predetermined cycle with an expected value for the output data, the one cycle A plurality of strobe signals for instructing the comparison are generated therein. The invention described in claim 2 is claim 1
In the high-speed memory device inspection method described above, one expected value is output at the beginning of each cycle, and when the output data is inverted in the middle of the cycle, the expected value is inverted accordingly. A third aspect of the present invention is a high-speed memory for inspecting the memory device by comparing each output data of a memory device that outputs two data in one cycle of a predetermined cycle with an expected value for the output data. In the device inspection method, two strobe signals for instructing the comparison are generated within the one cycle. According to a fourth aspect of the present invention, in the high-speed memory device inspection method according to the third aspect, one expected value is output at the beginning of each cycle, and when the output data is inverted in the latter half of the cycle, the expectation value is accompanied. It is characterized by inverting the value. According to a fifth aspect of the present invention, a high-speed memory that inspects the memory device by comparing each output data of a memory device that outputs a plurality of data within one cycle of a predetermined cycle with an expected value for the output data. The device inspection apparatus is characterized by comprising timing generation means for generating a plurality of strobe signals instructing the comparison within the one cycle. According to a sixth aspect of the present invention, in the high-speed memory device inspection apparatus according to the fifth aspect, one expected value is output at the beginning of each cycle, and when the output data is inverted in the middle of the cycle, the expectation value is accompanied. It is characterized by comprising expected value generating means for inverting the value. The invention according to claim 7 is a high-speed memory for inspecting the memory device by comparing each output data of a memory device that outputs two data in one cycle of a predetermined cycle with an expected value for the output data. The device inspection apparatus is characterized by comprising timing generation means for generating two strobe signals instructing the comparison within the one cycle. According to an eighth aspect of the present invention, in the high-speed memory device inspection apparatus according to the seventh aspect, one expected value is output at the beginning of each cycle, and when the output data is inverted in the latter half of the cycle, the expected value is accompanied. It is characterized by comprising expected value generating means for inverting the value.
According to a ninth aspect of the present invention, in the high-speed memory device inspection apparatus according to the sixth or eighth aspect, the expected value generation means includes a storage means that stores the expected value in advance, and each cycle At the beginning of, the expected value is read from the storage means. According to a tenth aspect of the present invention, in the high-speed memory device inspection apparatus according to the ninth aspect, the expected value generating means resets its output to "0" at least at the beginning of each cycle, and outputs the output data of the memory device. When is inverted, its output is "1"
A first flip-flop, an EXOR gate that performs an exclusive OR of the expected value read from the storage means and the output value of the first flip-flop, the beginning of each cycle, or the memory device. And a second flip-flop for reading and holding the output data of the EXOR gate when the output data of the above is inverted.

[0012]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. §1. Overview The high-speed memory device inspection method according to the present invention does not use the “pin link function” shown in FIG. 5, but instead uses the “double strobe function” that has two strobe signals in one cycle. When a test is performed using this double strobe function, the expected values in the first half and the second half of one cycle are the same, so the DRAM is
When the output is inverted, the "expected value inversion function" that automatically inverts the expected value is used to inspect the high-speed memory.

§2. Overall Configuration and Operation FIG. 1 is a block diagram showing a configuration example of a high speed memory device inspection apparatus according to an embodiment of the present invention. In this figure, parts corresponding to those in FIG. 4 are assigned the same reference numerals and explanations thereof are omitted. The memory device inspection apparatus shown in this figure is different from that of FIG. 4 in that the timing generation unit 5 ′ is changed to the timing generation unit 5 and the expected value generation unit 7 ′ is changed to the expected value generation unit 7. Is.

In the figure, the control unit 1 includes a CPU (central processing unit), a ROM (read only memory), and a RAM.
A computer circuit including (random access memory) and the like, and is connected to each unit of the apparatus by a bus and a control signal line (both not shown). As a result, the control unit 1 controls each part of the apparatus, executes the inspection program, and the like. The control unit 1 also has a built-in reference clock generation unit. Here, the reference clock generation unit is specifically composed of a crystal oscillator and its peripheral elements, and
A reference clock of [MHz] is generated.

The control unit 1 is also connected to an operation unit 2 including various switches and an external storage device 3 including a floppy disk drive and a hard disk drive. Here, the external storage device 3 is a DRA at the time of inspection.
The inspection pattern to be written in M4 and the expected pattern to be written in the expected pattern memory 6 at the time of the inspection are stored.

The DRAM 4 is an IC memory to be inspected by this device. In the present embodiment, DR
AM / 4 is an example of EDO (Extended Data Ou).
t) Assume that it is a DRAM. The timing generator 5 is specifically composed of a predetermined logic circuit including a DRAM controller. Then, the timing generator 5 outputs 60
Based on the reference clock of [MHz], while supplying control signals such as RAS and CAS to the DRAM 4,
Two strobe signals (that is, double strobe signals) are supplied to the determination unit 8 per cycle (16 [nsec]).

The expected pattern memory 6 is, specifically, S
It is an IC memory such as a RAM or a DRAM, and can be read / written by the control unit 1. The expected value generation unit 7 reads one expected data per cycle from the expected pattern memory 6 and outputs the expected value. The expected value generation unit 7 has a function of constantly monitoring the output data of the DRAM 4 and automatically inverting the expected value when the output data is inverted in the middle of the cycle (expected value inversion function). For details of the configuration and operation of the expected value generation unit 7, refer to "§
3. The expected value generation unit ”will be described.

When the strobe signal is input from the timing generating section 5, the judging section 8 compares the output data of the DRAM 4 with the expected value of the expected value generating section 7 and outputs the comparison result. In the present embodiment, as an example, the determination unit 8 includes an EXOR gate 8a and a D flip-flop 8b, as shown in FIG. Then, the determination unit 8 determines DR
If the output data of AM.4 and the expected value of the expected value generation unit 7 are equal, PASS ("0") is output, and if they are different, FAIL ("1") is output. The circuit configuration of the determination unit 8 and the level of the determination result are not limited to the above example, and “1” may be output as PASS and “0” may be output as FAIL.

The fail memory 9 is specifically a floppy disk drive or a hard disk drive,
The determination results output by the determination unit 8 are sequentially accumulated. Notification unit 1
For example, 0 is composed of a lamp or a buzzer and its drive circuit, and lights and sounds when the determination result of the determination unit 8 is FAIL.

Next, the operation of the high speed memory device inspection apparatus having the above configuration will be described. FIG. 3A is a time chart showing an operation example of the high-speed memory device inspection apparatus. When the operator turns on the power supply (not shown) of the apparatus, the control unit 1 initializes each unit of the apparatus. Further, when the power is turned on, the reference clock generation unit built in the control unit 1 starts generation of the reference clock of 60 [MHz] as shown in FIG.

Next, the operator uses the operation unit 2 to
When the writing of the inspection pattern and the expected pattern is instructed, the control unit 1 reads out the predetermined inspection pattern and the expected pattern from the external storage device 3, the DRAM 4 stores the inspection pattern, and the expected pattern memory stores the expected pattern. Write in 6 respectively.

In the present embodiment, the inspection pattern is
As an example, it is assumed that the pattern is a pattern in which "1" and "0" are alternately repeated, such as "1,0,1,0, ...". Further, the expected pattern corresponds to the inspection pattern, and in the present embodiment, as an example, “1, 1,
It is assumed that the pattern is a pattern in which "1" is repeated, such as 1, 1, ..... Here, the inspection pattern is "1", "0".
However, the expected value generation unit 7 does not need to repeat Ҥ3.
This is because the “expected value generation unit” has an expected value inversion function described later.

Next, the operator uses the operation unit 2 to
When the inspection start is instructed after instructing the use of the expected value inversion function, this apparatus inspects the DRAM 4 in the following procedure. The instruction to use the expected value inversion function may be written in the inspection program executed by the control unit 1 instead of being given from the operation unit 2.

When the inspection is started, the timing generator 5 first outputs the CAS in synchronization with the reference clock at a half cycle of the reference clock, as shown in FIG. That is, the timing generator 5 outputs two CASs in one cycle. In the present embodiment, the first CAS in one cycle is called "CAS1",
The second CAS is called "CAS2".

Each time the CAS rises, the DRAM 4, the inspection pattern ("1, 0,
One inspection data is output from 1, 0, ... ").
That is, here, the DRAM 4 outputs the inspection data "1" in response to the rise of CAS1, as shown in FIG. In this embodiment, the DRAM
The data output by 4 corresponding to CAS1 is called "data 1", and the data output corresponding to CAS2 is called "data 2".

On the other hand, the expected value generator 7 sequentially reads expected data from the expected pattern ("1, 1, 1, 1, ...") in the expected pattern memory 6 each time the reference clock is input. . When the expected value generation unit 7 reads the expected data, the expected value generation unit 7 performs the processing described below in "§3. Expected value generation unit",
The expected data (“1”) is output as it is as an expected value.

Further, the timing generator 5 is shown in FIG.
As shown in, the output of CAS is delayed by a predetermined time (in this embodiment, 4 [nsec] as an example),
Output strobe signal. The timing generator 5
The strobe signal output corresponding to CAS1 is referred to as "strobe signal 1", and the strobe signal output corresponding to CAS2 is referred to as "strobe signal 2".

On the other hand, the EXOR 8a of the judging section 8 is DR
The data output by AM.4 and the expected value output by the expected value generation unit 7 are compared, and if they match, PASS ("
0 "), if they do not match, FAIL (" 1 ") is output as the determination signal. Since both are" 1 "here, the determination signal is PASS (" 0 ").
The D flip-flop 8b of the determination unit 8 holds and outputs the determination signal ("0") at the rising edge of the strobe signal 1.

Next, when 1/2 cycle (8 [nsec]) has elapsed from the output of CAS1, the timing generator 5
Outputs CAS2 as shown in FIG. D
RAM4 is the DRA when CAS2 rises.
The inspection pattern ("1, 0,
The second inspection data ("1, 0, ...")
0 ") is output as data 2 (see FIG. 3A). Here, since the output data of the DRAM 4 is inverted in the middle of the cycle, the expected value generation unit 7 causes The expected data (“1”) read previously is inverted by performing the processing described later in the “generation unit”, and the inverted value (“1”) is inverted.
0 ") is output as an expected value (see FIG. 3A).

Further, the timing generator 5 is shown in FIG.
As shown in, a predetermined time (4 [ns
ec]) The strobe signal 2 is output after a delay. On the other hand, the EXOR 8a of the determination unit 8 compares the data 2 output by the DRAM 4 with the expected value output by the expected value generation unit 7 and outputs a determination signal. Here, both are "
Since it is "0", the determination signal becomes PASS ("0"). Then, the D flip-flop 8b of the determination unit 8 causes the determination signal ("
0 ") is held and output.

Hereinafter, each time the reference clock generation unit built in the control unit 1 outputs the reference clock, the timing generation unit 5
Are synchronized with CAS1 and CAS in synchronization with the reference clock.
Since 2 is output, the above-described operation is repeated. During this period, the determination signals output from the D flip-flop 8b of the determination unit 8 are sequentially output to the fail memory 9
Is accumulated in Then, the determination signal is FAIL ("
1 "), the notification unit 10 notifies the operator that the DRAM 4 is defective by a lamp or a buzzer. This allows the operator to know the defect of the DRAM 4 and the fail memory. The content of the defect can be analyzed based on the stored content of No. 9. The operation of the high-speed memory device inspection apparatus having the above-described configuration is now completed.

§3. Expected Value Generation Unit Next, details of the configuration and operation of the expected value generation unit 7 will be described. FIG. 2 is a circuit diagram showing a configuration example of the expected value generator 7. The circuit shown in this figure is merely an example, and any circuit may be used as long as it has the same function. In this figure, FF 7a, F
F · 7b is a D flip-flop. Also, EXO
R · 7c is an EXOR (exclusive OR) gate
R · 7d is an OR (logical sum) gate.

Further, in this figure, the inversion signal is a signal set by the controller 1 (see FIG. 1), and is always set to "1" when the expected value inversion function is used. The DRAM monitor signal is a signal which becomes a "1" level pulse when the output data of the DRAM4 (see FIG. 1) is inverted in the middle of the cycle. On the other hand, the reference clock signal generated by the reference clock generation unit built in the control unit 1 is FF
-Input to the R terminal of 7a and OR-7d. The expected data read from the expected pattern memory 6 (see FIG. 1) is input to the EXOR.7c.

Next, the operation of the expected value generating section 7 having the above configuration will be described. FIG. 3B is a time chart showing an operation example of the expected value generation unit 7. Note that, when the operator uses the operation unit 2 to instruct the use of the expected value inversion function before the inspection is started, the control unit 1 shows an inversion signal given to the expected value generation unit 7 in FIG. Like, always "1"
To hold. The above instruction may be described in the inspection program instead of being given from the operation unit 2.

In this state, the inspection of the DRAM 4 is started, and when the reference clock is input to the R terminal of the FF 7a, the FF 7a is reset and its output Q becomes "0". When the output data of the DRAM.4 is inverted in the middle of the cycle, the DRAM monitor signal becomes a "1" level pulse as shown in FIG.
Supplied to the terminal. DRAM monitoring signal is C of FF / 7a
When input to the terminal, the FF 7a holds the inverted signal ("1") input to the D terminal, and its output Q is "
It becomes 1 ". With the above operation, the output Q of FF 7a
Becomes "0" at the beginning of each cycle, and becomes "1" when the output data of the DRAM 4 is inverted in the middle of the cycle.

On the other hand, §2. As described above, the expected value generation unit 7 causes the expected pattern (“1, 1, 1, 1, ...
"), The expected data is sequentially read out, and the expected data is supplied to the EXOR 7c.

The EXOR.7c takes the exclusive OR of the output Q of the FF.7a and the expected data. That is, F
While the F · 7a outputs the inverted signal (“1”), the EXOR · 7c functions as a NOT gate. By the above operation, when the output data of the DRAM.4 is inverted in the middle of the cycle, the FF.7a outputs "1", and the expected data read from the expected pattern memory 6 as well as the output data of the DRAM.4. Invert.

On the other hand, the OR 7d takes the logical sum of the reference clock signal and the DRAM monitor signal (hereinafter referred to as "logical sum clock"). Then, the FF.7b outputs EXOR.7 each time the OR clock is input to the C terminal.
The output value of c is read, and the value is held and output as an expected value.

By the above operation, only when the inversion signal is set to "1" and the output data of the DRAM.4 is inverted in the middle of the cycle, the expected value generating section 7
The expected data read from the expected pattern memory 6 is inverted and output. As described above, the expected value generation unit 7 having the above configuration
The explanation of the operation of is ended.

§3. Supplement Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to the embodiment, and there may be a design change or the like without departing from the gist of the present invention. Even this is included in the present invention. For example, in one embodiment described above, EDO DRA is used as the high-speed memory.
Although an example of inspecting M has been shown, the high-speed memory to be inspected is not limited to EDO DRAM, but other ICs such as SRAM.
You can use memory.

Further, in the same embodiment, an example in which the determination is performed twice within one cycle has been shown, but it is conceivable that the determination is performed three times or more within one cycle by performing the same processing. .

[0042]

As described above, according to the present invention, by combining the double strobe function and the expected value reversing function, the pin link function is not used.
Multiple determinations can be made within one cycle. This eliminates the need for assigning a plurality of determination pins to one memory device as in the pin link function, and can double the number of memory devices to be inspected at the same time as compared with the case of using the pin link function. Therefore, the inspection of the memory device can be performed with high efficiency. Further, unlike the pin link function, it is not necessary to process a plurality of expected patterns (that is, a data string of expected values), and the expected pattern and the expected value generating means for processing the expected pattern can be unified. The inspection program can be simplified and the inspection program creation time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a high speed memory device inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an expected value generation unit 7 according to the same embodiment.

FIG. 3A is a time chart showing an operation example of the high-speed memory device inspection apparatus, and FIG. 3B is a time chart showing an operation example of an expected value generation unit 7.

FIG. 4 is a block diagram showing a configuration example of a conventional memory device inspection device.

FIG. 5 is a block diagram showing a configuration example of a high-speed memory device inspection apparatus using a pin link function.

FIG. 6A is a time chart showing an operation example of a conventional memory device inspection device, and FIG. 6B is a time chart showing an operation example of a high-speed memory device inspection device using a pin link function. .

[Explanation of symbols]

1 ... control unit, 2 ... operation unit, 3 ... external storage device, 4 ... DRAM, 5 ... timing generation unit, 6
...... Expected pattern memory, 7 ... Expected value generation unit, 8 ...
… Judgment part, 9 …… Fail memory, 10 …… Notification part

Claims (10)

[Claims] 1. A high-speed memory device inspection method for inspecting the memory device by comparing each output data of a memory device outputting a plurality of data within one cycle of a predetermined cycle with an expected value for the output data. 3. The high-speed memory device inspection method according to, wherein a plurality of strobe signals instructing the comparison are generated within the one cycle. 2. The high-speed memory device inspection method according to claim 1, wherein one expected value is output at the beginning of each cycle, and when the output data is inverted in the middle of the cycle, the expected value is inverted accordingly. A high-speed memory device inspection method characterized by: 3. A high-speed memory device inspection method for inspecting the memory device by comparing each output data of a memory device that outputs two data in one cycle of a predetermined cycle with an expected value for the output data. 2. The high-speed memory device inspection method according to, wherein two strobe signals instructing the comparison are generated within the one cycle. 4. The high-speed memory device inspection method according to claim 3, wherein one expected value is output at the beginning of each cycle, and when the output data is inverted in the latter half of the cycle, the expected value is inverted accordingly. A high-speed memory device inspection method characterized by: 5. A high-speed memory device inspection apparatus that inspects the memory device by comparing each output data of a memory device that outputs a plurality of data in one cycle of a predetermined cycle with an expected value for the output data. 3. The high-speed memory device inspection apparatus according to claim 1, further comprising timing generation means for generating a plurality of strobe signals instructing the comparison within the one cycle. 6. The high-speed memory device inspection apparatus according to claim 5, wherein one expected value is output at the beginning of each cycle, and when the output data is inverted during the cycle, the expected value is inverted accordingly. An apparatus for inspecting a high-speed memory device, which is provided with an expected value generating means. 7. A high-speed memory device inspection apparatus for inspecting the memory device by comparing each output data of a memory device that outputs two data in one cycle of a predetermined cycle with an expected value for the output data. 2. The high-speed memory device inspection apparatus according to claim 1, further comprising timing generation means for generating two strobe signals instructing the comparison within the one cycle. 8. The high-speed memory device inspection apparatus according to claim 7, wherein one expected value is output at the beginning of each cycle, and when the output data is inverted in the latter half of the cycle, the expected value is inverted accordingly. An apparatus for inspecting a high-speed memory device, which is provided with an expected value generating means. 9. The high-speed memory device inspection apparatus according to claim 6, wherein the expected value generation unit includes a storage unit that stores the expected value in advance, and the expected value generation unit is provided at the beginning of each cycle. A high-speed memory device inspection device, wherein the expected value is read from the storage means. 10. The high-speed memory device inspection apparatus according to claim 9, wherein the expected value generation means resets its output to “0” at least at the beginning of each cycle, and the output data of the memory device is inverted. EXOR which takes the exclusive OR of the first flip-flop whose output is "1", the expected value read from the storage means, and the output value of the first flip-flop
High-speed memory device test, comprising: a gate and a second flip-flop for reading and holding the output data of the EXOR gate at the beginning of each cycle or when the output data of the memory device is inverted. apparatus.