JP2000040400A - Semiconductor integrated circuit device and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a durability test even without use of a high functional LSI tester and to reduce the test cost by only imparting a basic clock signal from the outside at a test mode time and automatically and collectively performing write/erase operation in a circuit. SOLUTION: A signal level of a test terminal 2 for setting a test mode is made to Hi to be set in a durability test mode. An input level of the terminals XCE, XWE, etc. is made a Lo, and an EEPROM is made accessible. When a write data level is made to Lo with a chip enable 4, and a write-in/erase clock signal is inputted from a clock signal input terminal 3, a write/erase signal is generated in an EEPROM control circuit. The write signal to a write circuit is made to Hi, and the write operation is started. When the number of fixed clocks elapses, the write signal becomes to Lo, and the write operation is ended, and then, the erase signal is made to Hi, and the erase operation is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having an EEPROM and a test technique therefor.

[0002]

2. Description of the Related Art In general-purpose EEPROM products, tests for assuring the durability characteristics have been performed using a general-purpose ROM writer or the like or using an LSI tester. However, in particular, when an EEPROM is used in a part of an integrated circuit device such as an embedded array, the specification is different from a general-purpose product. Therefore, a ROM writer cannot be used as it is, and a high-performance LSI Testers were used to guarantee durability characteristics.

[0003]

However, since the test for guaranteeing the durability takes time, using an expensive LSI tester leads to an increase in test cost. It is also necessary to develop test programs individually. The present invention has been made in order to solve the above-described problem, and at the time of a durability test, by setting a test mode and inputting a clock signal,
Provided is a semiconductor integrated circuit device having a function of generating and repeating a write / erase waveform, and executing a collective write / erase cycle without using an LSI tester to reduce test costs. I do.

[0004]

SUMMARY OF THE INVENTION To solve this problem, a semiconductor integrated circuit inspection apparatus according to the present invention is a semiconductor integrated circuit device having an EEPROM, in which only a basic clock signal is externally supplied in a test mode. The erasing / erasing operation is automatically performed inside the circuit, and has a test function capable of simplifying a durability test. The test method uses the test function of the present invention to perform writing / erasing. The durability test can be performed only by giving the number of clocks corresponding to the number of cycles from the outside, and then performing non-defective / defective selection by an LSI tester.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device under test, which includes an EEPROM. 2 is a test terminal for enabling the test function of the present invention. In this case, the test mode is set when the input signal level is Hi. 3 is a clock input terminal. Basic clock signal for generating write / erase waveforms. 4 and 5 are control terminals of the EEPROM. It is fixed at Lo in order to keep the circuit active even in the test mode. 6 is an EEPROM control circuit. Test signals,
An EEPROM control signal is generated from the clock signal.
7 is a write circuit. The circuit performs a write operation in response to a signal from the EEPROM control circuit. 8 is an erasing circuit. EEP
The circuit performs an erasing operation according to a signal from the ROM control circuit. 9 is an address generation circuit. In the test mode, all the addresses are generated simultaneously in order to reduce the test time. As a result, all bits can be simultaneously accessed for writing / erasing. 10 is an EEPROM data input / output control circuit. In the test mode, there is only a write operation, and since data is written to all bits, all data is set to Lo.
Fixed to. 11 is an EEPROM memory cell. In this case, it is "0" in the write state. '1' for erase.

FIG. 2 shows EEPRO in the test mode.
It is an example of the operation timing in the M control circuit. 12 is TE
ST terminal waveform. Enter test mode with Hi. Therefore, Hi is fixed during the durability test. 13 is the waveform of the clock signal. 1
4 is a signal of the writing circuit. 15 is a signal of the erasing circuit. 1
Numerals 4 and 15 denote waveforms of signal levels 7 and 8 in FIG. 1, and each circuit becomes active at Hi level.
The operation will be described below. In order to set the durability test mode, the signal level of the TEST terminal 2 is fixed to Hi.
In order to make the EEPROM accessible, the input levels of the other terminals XCE and XWE are fixed at Lo,
Activate the circuit. Regarding the data terminal of No. 4,
The write data level is fixed to Lo. 3 CLK
From the terminal, the clock signal of the number of times corresponding to the specified cycle of writing / erasing is continuously input. This clock signal generates write / erase waveforms in the EEPROM control circuit as shown in FIGS. 14 and 15, and the generated signals are input to the write circuit and the erase circuit, respectively. When the signal to the write circuit becomes Hi, the circuit performs a write operation, and the data corresponding to the level of the ten data terminals is transmitted to the EE.
Start writing to the PROM. When a certain number of clocks elapses, the write signal becomes Lo, and the write ends.

Next, the erase signal 8 becomes Hi, during which the circuit performs an erase operation. While a clock signal is being input in the test mode, writing and erasing operations are repeatedly performed. By changing the number of input clocks, an arbitrary number of write / erase cycles can be set. When the clock signal for the specified number of times has been input, the signal level of the test terminal is set to Lo, and the test mode is released. In the test mode, all addresses can be accessed simultaneously by the address generation circuit, thereby shortening the time for writing / erasing.

[0008]

As described above, according to this test function, the setting of the power supply, the clock signal, the test terminal and the other input terminals are set to Hi or Lo, and the writing / erasing is repeated without complicated setting. After that, a good / defective product is selected, whereby a durability test can be performed. As a result, the durability test can be performed without using a high-performance LSI tester for a long time, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit device of the present invention.

FIG. 2 shows an EEPROM in a test mode according to the present invention.
FIG. 4 is an operation timing chart of a control circuit.

[Explanation of symbols]

 Reference Signs List 1 semiconductor integrated circuit device having EEPROM 2 test terminal for setting test mode 3 clock signal input terminal 4 chip enable 5 write enable terminal 7 write circuit 8 erase circuit 9 address generation circuit 10 data input / output circuit 11 EEPROM memory cell 12 Test terminal input waveform 13 Clock terminal input waveform 14 Write circuit control signal waveform 15 Erase circuit control signal waveform

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 2G032 AA08 AB03 AG03 AG07 AK01 AK14 AL00 AL16 4M106 AA04 AA07 AB08 AC02 BA14 CA56 5B025 AA00 AD01 AD04 AD08 AD16 AE08 AE09 5L106 AA10 DD11 DD25 DD37 GG03 GG05

Claims (2)

[Claims] In a semiconductor integrated circuit device having an EEPROM, in a test mode, a write / erase operation is performed automatically and collectively inside a circuit simply by supplying only a basic clock signal from the outside, and a durability test is performed. A semiconductor integrated circuit device having a test function A capable of simplifying the operation. 2. The EE of the semiconductor integrated circuit device according to claim 1.
In the write / erase durability test of the PROM, the test function A executes the write / erase a specified number of times only by externally providing a clock number corresponding to the write / erase cycle number, and then uses the LSI tester to perform a non-defective / erase test.
A test method characterized by enabling a durability test by selecting defective products.