JP4387640B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a logic cell block and a memory block, and a memory cell array having a redundant configuration for defect relief in the memory block.
[0002]
[Prior art]
Japanese Unexamined Patent Publication No. 2000-223661 discloses a semiconductor device having a chip-on-chip structure composed of a logic chip and a memory chip. The memory chip of this semiconductor device is, for example, a synchronous DRAM (Dynamic Random Access Memory) chip. After receiving a row address signal together with a row address strobe (RAS) signal from the logic chip, a column address strobe ( The column address signal is configured to be received together with the (CAS) signal. The delay of the CAS signal with respect to the RAS signal is generally called a RAS-CAS delay (RAS to CAS delay), and t _RCD It is written. In order to improve the yield, the DRAM chip of the publication includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells, and is programmed. A row redundancy control circuit for generating a row redundancy control signal indicating coincidence / mismatch between a relief row address and an address represented by a row address signal given from the logic chip, and a programmed relief column address and a logic chip And a column redundancy control circuit for generating a column redundancy control signal indicating coincidence / mismatch with the address represented by the column address signal.
[0003]
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor device, for example, a CPU (Central Processing Unit) on a logic chip issues a memory address signal, so that a row address signal and a column address signal are input to the DRAM chip, respectively. A normal memory cell or a redundant memory cell is selected after making a repair decision by the row redundancy control circuit and the column redundancy control circuit. Therefore, the time from the address issuance by the CPU to the selection of the memory cell becomes long, and the repair determination results in hindering the high-speed memory access.
[0004]
In the conventional DRAM chip, when the programming of the relief address is realized by a fuse circuit, it is difficult to miniaturize the fuse portion, and the occupied area becomes large. Because the fuse is cut by the laser irradiated from the laser repair device, it is necessary to secure a margin determined by the optical accuracy and a distance so that the fuse, wiring, etc. adjacent to the cutting location are not affected by the cutting. is there. In general, since a memory chip has a high process cost, an increase in the chip area is a big problem in cost of the entire semiconductor device.
[0005]
On the other hand, for example, when the conventional logic chip includes an SRAM (Static Random Access Memory) and a fuse circuit for programming the relief address, the same as the programming process of the fuse circuit on the DRAM chip by the laser repair device. The programming process of the fuse circuit on the logic chip by the laser repair device must be performed separately. Both chips are connected to each other via chip connection electrodes provided on each chip so that the main surfaces on which the fuse circuits are formed face each other, so that the fuse circuit on the DRAM chip is irradiated with laser after chip-on-chip connection. It can't be done.
[0006]
An object of the present invention is to shorten the time from address issuance to memory cell selection in a semiconductor device having a logic block and a memory block, thereby speeding up memory access.
[0007]
Another object of the present invention is to reduce the area of a memory chip in a semiconductor device having a chip-on-chip structure composed of a logic chip and a memory chip, thereby reducing the cost of the semiconductor device.
[0008]
Still another object of the present invention is to reduce the number of defect repair processes by a laser repair device in a semiconductor device having a chip-on-chip structure composed of a logic chip and a memory chip.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a repair determination circuit (for example, a fuse circuit) for repairing a defect in a memory chip (or memory block) is provided on the logic chip (or logic block) side.
[0010]
Specifically, the present invention is premised on a semiconductor device having a logic block and a memory block. The memory block includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells. On the other hand, the logic block includes an address signal supply circuit for supplying an address signal designating a normal memory cell to be accessed among the plurality of normal memory cells; A row redundancy control circuit that inputs a row address signal of the given memory address signal and outputs a row redundancy control signal, and a column address signal of the memory address signal and inputs a column redundancy control signal A column redundancy control circuit A relief determination circuit; Input signal to the memory block And a memory control circuit having a timing control circuit for supplying a strobe signal indicating the effective timing of the memory. And Judgment processing performed by the row redundancy control circuit to determine whether the programmed relief row address matches the row address indicated by the row address signal, and the programmed relief column performed by the column redundancy control circuit A determination process for determining whether or not an address matches a column address represented by the column address signal is performed in parallel. Above line Address signal The row redundancy control signal, the column address signal, And said Column The strobe signal is supplied from the logic block to the memory block together with the redundancy control signal. As a result, the result of the repair determination is determined early, so that the memory access speeds up. If the logic block and the memory block are formed on separate semiconductor chips, the area of the semiconductor chip on which the memory block is formed can be reduced.
[0011]
In the case where the logic block and the memory block are formed on separate semiconductor chips, and the two semiconductor chips are connected to each other via a chip connection electrode, the semiconductor chip on which the memory block is formed includes the address signal, A probe electrode for receiving the inspection input of each of the redundant control signal and the strobe signal from the outside is provided. In this case, a defect inspection of the memory cell array is performed using the probe electrode in the single semiconductor chip in which the memory block is formed, and the probe is also performed in the single semiconductor chip in which the memory block is formed. The redundant memory cell replacement confirmation test of the memory cell array can be performed using the electrodes.
[0012]
In addition, when the logic block and the memory block are formed on separate semiconductor chips and the two semiconductor chips are connected to each other via a chip connection electrode, the semiconductor chip on which the logic block is formed A fuse circuit for programming the function of the block is provided, and a fuse circuit for programming the relief address is provided in the relief determination circuit. In this way, the programming process of both the fuse circuits by the laser repair device can be continuously executed on a single semiconductor chip on which the logic block is formed.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a schematic exploded perspective view showing an example of a semiconductor device according to the present invention. The semiconductor device of FIG. 1 is a chip-on-chip composed of a semiconductor chip in which a logic block such as a CPU is formed, that is, a logic chip 10, and a semiconductor chip in which a memory block including a DRAM memory cell array is formed, that is, a DRAM chip 20. With structure. Both the chips 10 and 20 are connected to each other via chip connection electrodes 11 and 21 provided in each of the chips 10 and 20 so that their main surfaces face each other. In the logic chip 10, 12 is an SRAM, 13 is a memory control circuit for SRAM, and 100 is a memory control circuit for DRAM. The DRAM memory control circuit 100 includes an address signal supply circuit 14 for supplying an address signal designating a normal memory cell to be accessed on the DRAM chip 20, a programmed relief address, and an address represented by the address signal. And a repair determination circuit 15 for generating a redundancy control signal indicating coincidence / non-coincidence.
[0015]
FIG. 2 shows an electrode configuration of the DRAM chip 20 in FIG. The DRAM chip 20 is provided with a probe electrode 22 at the peripheral portion for receiving a test input from the outside and outputting a response to the test input to the outside, in addition to the chip connection electrode 21 described above.
[0016]
FIG. 3 shows a circuit configuration example of each of the logic chip 10 and the DRAM chip 20 in FIG. On the logic chip 10, the DRAM memory control circuit 100 receives a memory address signal ADR given from a CPU (not shown), and receives a clock signal CLK given from a clock generation circuit (not shown). In the DRAM chip 20, 200 is an address processing circuit, and 300 is a memory cell array. The address processing circuit 200 has a role of selecting a memory cell to be accessed in the memory cell array 300 based on a signal supplied from the memory control circuit 100 via the chip connection electrodes 11 and 21. In a single state of the DRAM chip 20, the test probe 18 of the tester 18 contacts the probe electrode 22, so that the address processing circuit 200 can receive a test input from the tester 18 instead of a signal from the memory control circuit 100. . Note that illustration and description of the data flow between the logic chip 10 and the DRAM chip 20 and the data flow between the tester 18 and the DRAM chip 20 are omitted.
[0017]
FIG. 4 shows a detailed configuration example of the memory cell array 300 in FIG. The memory cell array 300 has a normal memory cell region 301 and a redundant memory cell region 302 for defect relief. The normal memory cell 303 is designated by a combination of the row direction memory selection signal Xi and the column direction memory selection signal Yj. When the normal memory cell 303 is defective, the redundant memory cell 304 to be selected instead of the normal memory cell 303 is designated by a combination of the row direction redundant memory selection signal SXm and the column direction memory selection signal Yj, for example. The It is also possible to designate a redundant memory cell by a combination of the row direction memory selection signal Xi and the column direction redundant memory selection signal SYn, or a combination of the row direction redundant memory selection signal SXm and the column direction redundant memory selection signal SYN. . The SRAM 12 in FIG. 1 also has a redundant memory configuration similar to that in FIG.
[0018]
FIG. 5 shows a detailed configuration example of each of the memory control circuit 100 and the address processing circuit 200 in FIG. Detailed configurations of the memory control circuit 100 and the address processing circuit 200 will be sequentially described.
[0019]
The memory control circuit 100 includes an address signal supply circuit 14, a repair determination circuit 15, and a timing control circuit 106. The address signal supply circuit 14 latches a memory address signal ADR supplied from a CPU (not shown) and supplies a row address signal DXA and a column address signal DYA, and a column address signal DYA for a predetermined time. t _RCD And a delay circuit 103 for supplying a delay column address signal PDYA obtained by delaying by a delay amount. The latch circuit 101 operates in synchronization with the clock signal CLK. The relief determination circuit 15 includes a row redundancy control circuit 102 for generating a row redundancy control signal DFX indicating whether the programmed relief row address matches the address indicated by the row address signal DXA, and a programmed relief column. A column redundancy control circuit 104 for generating a column redundancy control signal DFY indicating the coincidence / mismatch between the address and the address indicated by the column address signal DYA, and the column redundancy control signal DFY for the predetermined time t _RCD And a delay circuit 105 for supplying a delay column redundancy control signal PDFY obtained by delaying by a delay amount. The timing control circuit 106 receives a memory read request signal RD and the like in addition to the clock signal CLK, and a fuse circuit enable signal FEN for activating the row redundancy control circuit 102 and the column redundancy control circuit 104, and a row address signal DXA. And a row address strobe signal NRAS indicating the effective timing of the row redundancy control signal DFX and a column address strobe signal NCAS indicating the effective timing of the delay column address signal PDYA and the delay column redundancy control signal PDFY. Accordingly, the row address strobe signal NRAS together with the row address signal DXA and the row redundancy control signal DFX, and the column address strobe signal NCAS together with the delay column address signal PDYA and the delay column redundancy control signal PDFY are respectively sent from the memory control circuit 100 to the address processing circuit 200. Supplied to. Note that “N” in NRAS and NCAS indicates that these address strobe signals are negative logic signals.
[0020]
On the other hand, the address processing circuit 200 includes an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a normal column decoder 204, and a column redundancy driver 205. The input circuit 201 operates in synchronization with the clock signal CLK, latches the row address signal DXA and the row redundancy control signal DFX according to the row address strobe signal NRAS, and outputs the internal row address signal XA and the internal row redundancy control signal FX to the column. This is a circuit for latching the delay column address signal PDYA and the delay column redundancy control signal PDFY according to the address strobe signal NCAS and supplying the internal column address signal YA and the internal column redundancy control signal FY, respectively. The normal row decoder 202 decodes the internal row address signal XA and supplies the row direction memory selection signal X to the memory cell array 300 when the internal row redundancy control signal FX indicates an address mismatch. Row redundancy driver 203 supplies row direction redundant memory selection signal SX to memory cell array 300 in accordance with internal row redundancy control signal FX. The normal column decoder 204 decodes the internal column address signal YA and supplies the column direction memory selection signal Y to the memory cell array 300 when the internal column redundancy control signal FY indicates an address mismatch. The column redundancy driver 205 supplies a column direction redundant memory selection signal SY to the memory cell array 300 in accordance with the internal column redundancy control signal FY.
[0021]
FIG. 6 shows a detailed configuration example of the row redundancy control circuit 102 in FIG. The row redundancy control circuit 102 includes a plurality of relief address determination circuits 110 that can each program one relief row address. Each relief address discrimination circuit 110 includes an address program circuit 111 and an address comparison circuit 112. The address program circuit 111 is composed of a number of fuse circuits 120 equal to the number of bits of the relief row address and one inverter 130 for supplying an inverted signal of the fuse circuit enable signal FEN to each fuse circuit 120. Each fuse circuit 120 includes one P-channel MOS transistor 121, two N-channel MOS transistors 122 and 123, one inverter 124, and one fuse 125 that can be cut by a laser. . R0 / NR0 in FIG. 6 is a complementary bit signal, and when the fuse circuit enable signal FEN holds an inactive level (Low level), R0 = High and NR0 regardless of whether the fuse 125 is cut or not. = Low. When the fuse circuit enable signal FEN is activated to a high level, R0 = High and NR0 = Low when the fuse 125 is cut, and R0 = Low and NR0 = High when the fuse 125 is not cut. It becomes. A group of complementary bit signals R0 / NR0 of each fuse circuit 120 is a relief row address signal RX, and the address comparison circuit 112 determines whether the relief row address signal RX and the row address signal DXA match. F0 in FIG. 6 is one relief address determination signal. When the relief row address signal RX and the row address signal DXA match, F0 = High, and when they do not match, F0 = Low. The above-described row redundancy control signal DFX is a summary of the determination results of each relief address determination circuit 110. The internal configuration of the column redundancy control circuit 104 in FIG. 5 is the same as that in FIG. The SRAM memory control circuit 13 in FIG. 1 also has a fuse circuit for relief address programming similar to that in FIG.
[0022]
FIG. 7 shows a detailed configuration example of the normal row decoder 202 in FIG. The normal row decoder 202 outputs the decoding result of the internal row address signal XA as a row direction memory selection signal when the internal row redundancy control signal FX indicates an address mismatch, that is, when all the bits of the internal row redundancy control signal FX are Low. A plurality of decoders 140 to 142, a plurality of two-input AND gates 143 to 145, and one multi-input OR gate 146 are configured so as to be supplied as X. The internal configuration of the normal column decoder 204 in FIG. 5 is the same as that in FIG.
[0023]
FIG. 8 shows a detailed configuration example of the row redundancy driver 203 in FIG. The row redundancy driver 203 includes a plurality of drivers 150 to 152 so as to supply a row direction redundancy memory selection signal SX corresponding to each bit of the internal row redundancy control signal FX. The internal configuration of the column redundancy driver 205 in FIG. 5 is the same as that in FIG.
[0024]
9 shows the operation of the memory control circuit 100 in FIG. 5, and FIG. 10 shows the operation of the address processing circuit 200 in FIG. T0 to T5 each represent one cycle of the clock signal CLK. Here, t _RCD Is described as corresponding to two cycles of the clock signal CLK.
[0025]
According to FIG. 9, when a memory address signal ADR is issued from a CPU (not shown) in cycle T0, the latch circuit 101 latches the memory address signal ADR in synchronization with the rising edge of the clock signal CLK in cycle T1. The row address signal DXA corresponding to the upper part of the memory address signal ADR and the column address signal DYA corresponding to the lower part of the memory address signal ADR are supplied. The row redundancy control circuit 102 and the column redundancy control circuit 104 immediately start the repair determination, and the row redundancy control signal DFX and the column redundancy control signal DFY are determined within the cycle T1. In FIG. 9, the DFX broken line (High level) indicates the case where the row addresses match, and the DFX solid line indicates the case where the row addresses do not match. Also, the DFY broken line (High level) indicates the case where the column addresses match, and the DFY solid line indicates the case where the column addresses do not match. The delayed column address signal PDYA is a signal delayed by 2 cycles of the column address signal DYA, and the delayed column redundancy control signal PDFF is a signal delayed by 2 cycles of the column redundancy control signal DFY. The timing control circuit 106 supplies the row address strobe signal NRAS so as to indicate a low level when the clock signal CLK rises in the cycle T2, and then supplies a column address strobe signal so as to indicate the low level when the clock signal CLK rises in the cycle T4. Supply NCAS.
[0026]
On the other hand, according to FIG. 10, the input circuit 201 latches the row address signal DXA and the row redundancy control signal DFX in synchronization with the rising edge of the clock signal CLK in the cycle T2 in accordance with the row address strobe signal NRAS. An internal row address signal XA and an internal row redundancy control signal FX are supplied. In response to this, the row direction memory selection signal X and the row direction redundant memory selection signal SX are determined in the cycle T2. Further, the input circuit 201 latches the delay column address signal PDYA and the delay column redundancy control signal PDFY in synchronization with the rising edge of the clock signal CLK in the cycle T4 in accordance with the column address strobe signal NCAS, and the internal column address as a result thereof. A signal YA and an internal column redundancy control signal FY are supplied. In response to this, the column direction memory selection signal Y and the column direction redundant memory selection signal SY are determined in the cycle T4.
[0027]
As described above, according to the memory control circuit 100 and the address processing circuit 200 shown in FIG. 5, the row redundancy control signal DFX and the column redundancy control signal DFY representing the result of the repair determination by the repair determination circuit 15 on the logic chip 10 are obtained. Since the determination is made at an early stage, the time from when the memory address signal ADR is input from the CPU to the memory control circuit 100 until the memory cell is selected in the DRAM chip 20 can be shortened compared to the conventional case. In addition, since the repair determination circuit 15 including the plurality of fuse circuits 120 is provided on the logic chip 10 side, the area of the DRAM chip 20 is reduced, and cost reduction is achieved.
[0028]
FIG. 11 shows a defect repair flow in the semiconductor device of FIG. Steps 401 and 402 are a flow of the DRAM chip 20 alone, and steps 403 to 405 are a flow of the logic chip 10 alone. In step 406, the chips 10 and 20 are connected.
[0029]
In step 401, a defect inspection of the DRAM memory cell array 300 is performed using the probe electrode 22 to identify the address (relief row address and relief column address) of the defective memory cell. Specifically, as shown in FIG. 3, the probe needle of the tester 18 is brought into contact with the probe electrode 22, and an inspection input is given from the tester 18 to the DRAM chip 20. In this case, address-related inspection inputs are a clock signal CLK, a row address signal DXA, a delayed column address signal PDYA, a row address strobe signal NRAS, and a column address strobe signal NCAS. The row redundancy control signal DFX and the delay column redundancy control signal PDFY are both inactive (all bits are at a low level). Then, the address of the normal memory cell 303 from which correct data cannot be read is specified.
[0030]
In the next step 402, a redundant memory cell replacement confirmation test of the DRAM memory cell array 300 is performed using the probe electrode 22. Specifically, not only the clock signal CLK, the row address signal DXA, the delayed column address signal PDYA, the row address strobe signal NRAS and the column address strobe signal NCAS, but also the row redundancy control signal according to the relief address specified in the step 401. The tester 18 supplies the DFX and the delay column redundancy control signal PDFY to the DRAM chip 20.
[0031]
In step 403, the defect inspection of the SRAM 12 is performed using a probe electrode (not shown) provided on the logic chip 10 to identify the address of the defective memory cell.
[0032]
In the next step 404, using a known laser repair device, a program step relating to each fuse circuit 120 in the DRAM memory control circuit 100 and a program step relating to each fuse circuit in the SRAM memory control circuit 13 are performed. Run continuously. That is, redundant memory cell use setting is performed by cutting a fuse using a laser repair device. At this time, the address of the defective memory cell in the DRAM memory cell array 300 specified in step 401 and the address of the defective memory cell in the SRAM 12 specified in step 403 are referred to.
[0033]
Further, in the next step 405, a redundant memory cell replacement confirmation test of the SRAM 12 is performed using a probe electrode (not shown) provided on the logic chip 10.
[0034]
In the final step 406, the logic chip 10 and the DRAM chip 20 are connected to each other via chip connection electrodes 11 and 21 provided respectively.
[0035]
According to the repair method of the semiconductor device described above, the defect relief fuse of the DRAM chip 20 is arranged on the logic chip 10 side, and this is cut in the same process as the SRAM defect relief fuse on the logic chip 10. Can do. In other words, the fuse cutting process using the laser repair device is only required once, and throughput can be improved and inspection cost can be reduced. Further, since the tester 18 can provide inspection inputs of redundant control signals (DFX and PDFY in the above example) via the probe electrode 22 in the DRAM chip 20, the DRAM chip 20 before the chip-on-chip connection is connected. Redundant memory cell replacement confirmation inspection can be performed.
[0036]
FIG. 12 shows a modification of the configuration of FIG. According to the example of FIG. 12, the delay circuit 105 in the repair determination circuit 15 in FIG. 5 is moved into the address processing circuit 200. Therefore, according to FIG. 12, the row address strobe signal NRAS together with the row address signal DXA, the row redundancy control signal DFX, and the column redundancy control signal DFY, and the column address strobe signal NCAS together with the delay column address signal PDYA are respectively stored in the memory control circuit 100. To the address processing circuit 200. The address processing circuit 200 of FIG. 12 includes an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a delay circuit 206, a normal column decoder 204, and a column redundancy driver 205. The input circuit 201 operates in synchronization with the clock signal CLK, latches the row address signal DXA, the row redundancy control signal DFX, and the column redundancy control signal DFY in accordance with the row address strobe signal NRAS, and internal row address signal XA, internal row redundancy. The control signal FX and the internal column redundancy control signal FY are circuits for latching the delay column address signal PDYA and supplying the internal column address signal YA in accordance with the column address strobe signal NCAS. The normal row decoder 202 decodes the internal row address signal XA and supplies the row direction memory selection signal X to the memory cell array 300 when the internal row redundancy control signal FX indicates an address mismatch. Row redundancy driver 203 supplies row direction redundant memory selection signal SX to memory cell array 300 in accordance with internal row redundancy control signal FX. The delay circuit 206 receives the internal column redundancy control signal FY for a predetermined time t. _RCD An internal delay string redundancy control signal PFY obtained by delaying only by the delay time is supplied. The normal column decoder 204 decodes the internal column address signal YA and supplies the column direction memory selection signal Y to the memory cell array 300 when the internal delay column redundancy control signal PFY indicates an address mismatch. The column redundancy driver 205 supplies the column direction redundancy memory selection signal SY to the memory cell array 300 according to the internal delay column redundancy control signal PFY.
[0037]
13 shows the operation of the memory control circuit 100 in FIG. 12, and FIG. 14 shows the operation of the address processing circuit 200 in FIG. Although detailed description of the timing is omitted, since the internal column redundancy control signal FY is determined earlier than in the case where the configuration of FIG. 5 is adopted, the determination of the column direction redundant memory selection signal SY is accelerated.
[0038]
FIG. 15 shows another modification of the configuration of FIG. According to the example of FIG. 15, the delay circuit 103 in the address signal supply circuit 14 and the delay circuit 105 in the repair determination circuit 15 in FIG. 5 are moved into the address processing circuit 200. Therefore, according to FIG. 15, the timing control circuit 106 generates a single address strobe signal NAS indicating the valid timing of the row address signal DXA, the column address signal DYA, the row redundancy control signal DFX, and the column redundancy control signal DFY. 200. The address processing circuit 200 of FIG. 15 includes an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a first delay circuit 207, a second delay circuit 206, and a normal column decoder 204. Column redundancy driver 205. The input circuit 201 operates in synchronization with the clock signal CLK, latches the row address signal DXA, the column address signal DYA, the row redundancy control signal DFX, and the column redundancy control signal DFY according to the address strobe signal NAS, and internal row address signal XA. , An internal column address signal YA, an internal row redundancy control signal FX, and an internal column redundancy control signal FY. The normal row decoder 202 decodes the internal row address signal XA and supplies the row direction memory selection signal X to the memory cell array 300 when the internal row redundancy control signal FX indicates an address mismatch. Row redundancy driver 203 supplies row direction redundant memory selection signal SX to memory cell array 300 in accordance with internal row redundancy control signal FX. The first delay circuit 207 receives the internal column address signal YA for a predetermined time t. _RCD An internal delay column address signal PYA obtained by delaying only by a delay time is supplied. The second delay circuit 206 sends the internal column redundancy control signal FY to the predetermined time t. _RCD An internal delay string redundancy control signal PFY obtained by delaying only by the delay time is supplied. The normal column decoder 204 decodes the internal delay column address signal PYA and supplies the column direction memory selection signal Y to the memory cell array 300 when the internal delay column redundancy control signal PFY indicates an address mismatch. The column redundancy driver 205 supplies the column direction redundancy memory selection signal SY to the memory cell array 300 according to the internal delay column redundancy control signal PFY.
[0039]
16 shows the operation of the memory control circuit 100 in FIG. 15, and FIG. 17 shows the operation of the address processing circuit 200 in FIG. Although a detailed description of the timing is omitted, the internal column address signal YA and the internal column redundancy control signal FY are determined earlier than in the case of adopting the configuration of FIG. The determination of the selection signal SY is accelerated.
[0040]
In the above example, the logic chip 10 and the DRAM chip 20 constitute a chip-on-chip semiconductor device. However, when other memory chips such as a flash memory chip and an SRAM chip are used instead of the DRAM chip 20. The present invention is also applicable.
[0041]
Further, the fuse circuit on the logic chip 10 to be cut by the laser repair device in step 404 in FIG. 11 is not limited to the fuse circuit for SRAM defect repair, and generally for programming the function of the logic chip 10. Any fuse circuit may be used. This fuse circuit and the fuse circuit 120 for relieving DRAM defects on the logic chip 10 are the targets of the continuous program process by the laser repair device.
[0042]
Furthermore, in a semiconductor device having a single chip structure having a logic block and a memory block, even if a repair determination circuit for repairing a defect in a memory block is provided on the logic block side, the time from address issuance to memory cell selection is shortened. As a result, the memory access speed can be increased.
[0043]
【The invention's effect】
As described above, according to the present invention, since a repair determination circuit (for example, a fuse circuit) for repairing a defect in a memory chip is provided on the logic chip side, the memory access speed is increased, and the area of the memory chip is increased. And the number of defect repair processes by the laser repair apparatus is reduced. However, in order to shorten the time from address issuance to memory cell selection, it is sufficient to provide a repair determination circuit for repairing a defect in the memory block on the logic block side.
[Brief description of the drawings]
FIG. 1 is a schematic exploded perspective view showing an example of a semiconductor device according to the present invention.
FIG. 2 is a plan view showing an electrode configuration of the DRAM chip in FIG. 1;
3 is a block diagram showing a circuit configuration example of each of the logic chip and the DRAM chip in FIG. 1. FIG.
4 is a conceptual diagram showing a detailed configuration example of a memory cell array in FIG. 3;
5 is a block diagram illustrating a detailed configuration example of each of a memory control circuit and an address processing circuit in FIG. 3. FIG.
6 is a circuit diagram showing a detailed configuration example of a row redundancy control circuit in FIG. 5. FIG.
7 is a circuit diagram showing a detailed configuration example of a normal row decoder in FIG. 5; FIG.
8 is a circuit diagram showing a detailed configuration example of a row redundancy driver in FIG. 5;
FIG. 9 is a timing chart showing the operation of the memory control circuit in FIG. 5;
10 is a timing chart showing the operation of the address processing circuit in FIG. 5. FIG.
11 is a repair flow diagram of defects in the semiconductor device of FIG. 1;
12 is a block diagram showing a modification of the configuration of FIG.
13 is a timing chart showing the operation of the memory control circuit in FIG. 12. FIG.
14 is a timing chart showing an operation of the address processing circuit in FIG. 12. FIG.
15 is a block diagram showing another modification of the configuration of FIG.
16 is a timing chart showing the operation of the memory control circuit in FIG. 15;
FIG. 17 is a timing chart showing the operation of the address processing circuit in FIG. 15;
[Explanation of symbols]
10 Logic chip
11 Chip connection electrode
12 SRAM
13 Memory control circuit for SRAM
14 Address signal supply circuit
15 Relief determination circuit
18 Tester
20 DRAM chip
21 Chip connection electrode
22 Probe electrode
Memory control circuit for 100 DRAM
101 Latch circuit
102 row redundancy control circuit
103 Delay circuit
104 column redundancy control circuit
105 Delay circuit
106 Timing control circuit
110 Relief address discrimination circuit
111 Address program circuit
112 Address comparison circuit
120 fuse circuit
125 fuse
200 Address processing circuit
201 Input circuit (latch)
202 Normal row decoder
203 line redundancy driver
204 Normal column decoder
205 column redundant driver
206 Delay circuit
207 Delay circuit
300 Memory cell array
301 Normal memory cell area
302 Redundant memory cell region
303 Normal memory cell
304 Redundant memory cell
ADR memory address signal
CLK clock signal
DFX row redundancy control signal
DFY column redundancy control signal
DXA row address signal
DYA column address signal
F0 relief address discrimination signal
FEN Fuse circuit enable signal
FX Internal row redundancy control signal
FY Internal column redundancy control signal
NAS address strobe signal
NCAS column address strobe signal
NRAS row address strobe signal
PDFY delay train redundancy control signal
PDYA Delay column address signal
PFY Internal delay train redundancy control signal
PYA internal delay column address signal
R0, NR0 complementary bit signals
RX relief row address signal
SX, SXm Row direction redundant memory selection signal
SY, SYn Column direction redundant memory selection signal
X, Xi Row direction memory selection signal
XA Internal row address signal
Y, Yj Column direction memory selection signal
YA Internal column address signal

Claims (6)

A semiconductor device having a logic block and a memory block,
The memory block includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells,
The logic block is
An address signal supply circuit for supplying an address signal specifying a normal memory cell to be accessed among the plurality of normal memory cells;
A row redundancy control circuit that inputs a row address signal of the given memory address signal and outputs a row redundancy control signal, and a column address signal of the memory address signal and inputs a column redundancy control signal A repair determination circuit having a column redundancy control circuit ;
A memory control circuit having a timing control circuit for supplying a strobe signal indicating a valid timing of an input signal to the memory block ;
A determination process performed by the row redundancy control circuit to determine whether or not the programmed relief row address matches the row address represented by the row address signal;
A determination process for determining whether or not the programmed relief column address and the column address represented by the column address signal are performed in the column redundancy control circuit is performed in parallel.
A semiconductor device characterized in that the strobe signal is supplied from the logic block to the memory block together with the row address signal , the row redundancy control signal, the column address signal, and the column redundancy control signal. . The semiconductor device according to claim 1,
Said address signal supply circuit, a delay column address obtained by the latch circuit for the memory address signal latched supplies the row address signal and the column address signal, delaying the column address signal for a predetermined time A first delay circuit for supplying a signal,
The relief decision circuit further comprises a second delay circuit for supplying a delay column redundancy control signal obtained by the pre-Symbol column redundancy control signals is delayed by the predetermined time,
Said timing control circuit, the row address signal and the row redundancy control signal and the first address strobe signal indicating the effective timing of the delayed column address signal and said delay line a second indicating the effective timing of the redundancy control signal a function for supplying an address strobe signal,
Before Symbol memory block,
Latches and the row redundancy control signal and the row address signal in accordance with said first address strobe signal, and outputs an internal row address signal and an internal row redundancy control signal, the delay line in accordance with said second address strobe signal It latches the address signal and the delayed column redundancy control signals, an input circuit for outputting an internal column address signal and an internal column redundancy control signals,
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A normal column decoder for decoding the internal column address signal and supplying a column direction memory selection signal to the memory cell array when the internal column redundancy control signal indicates an address mismatch;
A semiconductor device further comprising: a column redundancy driver for supplying a column direction redundant memory selection signal to the memory cell array in accordance with the internal column redundancy control signal. The semiconductor device according to claim 1,
Said address signal supply circuit, a delay column address obtained by the latch circuit for the memory address signal latched supplies the row address signal and the column address signal, delaying the column address signal for a predetermined time A first delay circuit for supplying a signal ,
Before Symbol timing control circuit, the row address signal and the row redundancy control signal and the first address strobe signal indicating the effective timing of the column redundancy control signal and the second indicating the valid timing of the delay column address signals A function of supplying an address strobe signal ;
Before Symbol memory block,
It said row address signal and the row redundancy control signal said column redundancy control signals and latches the accordance with the first address strobe signal, and outputs an internal row address signal and an internal row redundancy control signal and an internal column redundancy control signals latches the delayed column address signal in accordance with said second address strobe signal, an input circuit for outputting an internal column address signal,
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A second delay circuit for supplying an internal delay column redundancy control signal obtained by delaying the internal column redundancy control signal by the predetermined time;
A normal column decoder for decoding the internal column address signal and supplying a column direction memory selection signal to the memory cell array when the internal delay column redundancy control signal indicates an address mismatch;
A semiconductor device further comprising: a column redundancy driver for supplying a column direction redundant memory selection signal to the memory cell array in accordance with the internal delay column redundancy control signal. The semiconductor device according to claim 1,
It said address signal supply circuit includes a latch circuit for supplying the row address signal and the column address signal and latching the memory address signal,
Before Symbol timing control circuit has a function of supplying the row address signal and the column address signal and the row redundancy control signal and said column redundancy control signal and indicates to the address strobe signal to enable the timing of,
Before Symbol memory block,
And latching the row address signal and the column address signal and the row redundancy control signal and the column redundancy control signal in accordance with said address strobe signal, internal row address signal and an internal column address signal and an internal row redundancy control signals and internal column An input circuit for outputting a redundant control signal;
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A first delay circuit for supplying an internal delay column address signal obtained by delaying the internal column address signal by a predetermined time;
A second delay circuit for supplying an internal delay column redundancy control signal obtained by delaying the internal column redundancy control signal by the predetermined time;
A normal column decoder for decoding the internal delay column address signal and supplying a column direction memory selection signal to the memory cell array when the internal delay column redundancy control signal indicates an address mismatch;
A semiconductor device further comprising: a column redundancy driver for supplying a column direction redundant memory selection signal to the memory cell array in accordance with the internal delay column redundancy control signal. The semiconductor device according to claim 1,
The semiconductor device, wherein the logic block and the memory block are formed on separate semiconductor chips and connected to each other through a chip connection electrode. The semiconductor device according to claim 1 ,
The semiconductor device , wherein the memory block is a DRAM block .

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