JP2004054993A - Semiconductor device and its repair method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up memory access, reduce an area in a memory chip, and reduce the number of a defective repair processes by a laser repair system in a semiconductor device having a chip-on-chip structure constituted of a logic chip and a memory chip. <P>SOLUTION: A memory control circuit 100 having a relief determination circuit (including a fuse circuit) 15 for relieving from a defect in a memory chip (DRAM) 20 sets at a logic chip side 10. Besides, the logic chip 10 has a SRAM 12 and its memory control circuit 13. A program process of the relief determination circuit 15 for the DRAM and a program process of a relief determination circuit owned by the memory control circuit 13 for the SRAM are executed consecutively by using the same laser repair device. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a logic block and a memory block, and a memory cell array having a redundant configuration for relieving defects in the memory block.
[0002]
[Prior art]
Japanese Patent Laying-Open No. 2000-223661 discloses a semiconductor device having a chip-on-chip structure including a logic chip and a memory chip. A memory chip of the semiconductor device is, for example, a synchronous dynamic random access memory (DRAM) chip. After receiving a row address signal together with a row address strobe (RAS) signal from the logic chip, the memory chip of the semiconductor device is connected to a column address strobe (RAS) from the logic chip. CAS) signal and a column address signal. The delay of the CAS signal with respect to the RAS signal is generally called RAS-CAS delay (RAS to CAS delay), and t _RCD Is written. The DRAM chip of the publication includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells for improving the yield, and is programmed. A row redundancy control circuit for generating a row redundancy control signal indicating match / mismatch between the rescue row address and the address represented by the row address signal given from the logic chip; And a column redundancy control circuit for generating a column redundancy control signal indicating match / mismatch with the address represented by the column address signal.
[0003]
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor device, after a row address signal and a column address signal are input to the DRAM chip by a CPU (Central Processing Unit) on the logic chip, for example, issuing a memory address signal, The normal memory cell or the redundant memory cell is selected after the remedy is determined by the row redundancy control circuit and the column redundancy control circuit. Therefore, the time from the address issuance by the CPU to the selection of the memory cell is lengthened, and the rescue decision hinders high-speed memory access.
[0004]
In the above-described conventional DRAM chip, when the relief address is programmed by a fuse circuit, it is difficult to miniaturize the fuse portion, and the occupied area increases. Because the fuse is cut by the laser emitted from the laser repair device, a margin determined by the optical accuracy and a distance must be secured so that the fuse and wiring adjacent to the cut location are not affected by the cut. is there. Generally, a memory chip has a high process cost, so that an increase in the chip area is a major problem in the cost of the entire semiconductor device.
[0005]
On the other hand, for example, when the above-described conventional logic chip includes an SRAM (Static Random Access Memory) and a fuse circuit for programming a relief address thereof, the same steps are performed as in the step of programming the fuse circuit on the DRAM chip by the laser repair device. The programming process of the fuse circuit on the logic chip by the laser repair device must be performed separately. Both chips are connected to each other via the chip connection electrodes provided so that the main surfaces on which the fuse circuits are formed face each other, so that the laser is irradiated to the fuse circuits on the DRAM chip after chip-on-chip connection You cannot do it.
[0006]
An object of the present invention is to shorten the time from address issuance to memory cell selection in a semiconductor device having a logic block and a memory block, thereby speeding up memory access.
[0007]
Another object of the present invention is to reduce the area of a memory chip in a semiconductor device having a chip-on-chip structure composed of a logic chip and a memory chip, thereby reducing the cost of the semiconductor device.
[0008]
Still another object of the present invention is to reduce the number of defect repair steps by a laser repair device in a semiconductor device having a chip-on-chip structure composed of a logic chip and a memory chip.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a relief judgment circuit (for example, a fuse circuit) for relieving a defect of a memory chip (or a memory block) is provided on a logic chip (or a logic block) side.
[0010]
More specifically, the present invention is based on a semiconductor device having a logic block and a memory block. The memory block includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells. On the other hand, the logic block includes an address signal supply circuit for supplying an address signal designating a normal memory cell to be accessed among the plurality of normal memory cells, and a logic circuit including a programmed relief address and an address represented by the address signal. A memory control circuit having a relief determination circuit for generating a redundancy control signal indicating match / mismatch and a timing control circuit for supplying a strobe signal indicating valid timing of the address signal and the redundancy control signal; And The strobe signal is supplied from a logic block to a memory block together with the address signal and the redundancy control signal. As a result, the result of the rescue determination is determined early, and the memory access speeds up. If the logic block and the memory block are formed on separate semiconductor chips, the area of the semiconductor chip on which the memory block is formed can be reduced.
[0011]
When the logic block and the memory block are formed on separate semiconductor chips, respectively, and both semiconductor chips are connected to each other via a chip connection electrode, the semiconductor chip on which the memory block is formed includes the address signal, A probe electrode for receiving test input of each of the redundancy control signal and the strobe signal from outside is provided. With this configuration, a defect inspection of the memory cell array is performed by using the probe electrode on the semiconductor chip on which the memory block is formed, and the probe is similarly performed on the semiconductor chip on which the memory block is formed. A redundant memory cell replacement confirmation test of the memory cell array can be performed using the electrodes.
[0012]
Further, when the logic block and the memory block are formed on separate semiconductor chips, respectively, and the two semiconductor chips are connected to each other via a chip connection electrode, the semiconductor chip on which the logic block is formed includes the logic chip. A fuse circuit for programming the function of the block is provided, and a fuse circuit for programming the repair address is provided in the repair determination circuit. In this case, the semiconductor chip on which the logic block is formed can execute the programming process of the two fuse circuits by the laser repair device continuously.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a schematic exploded perspective view showing an example of a semiconductor device according to the present invention. The semiconductor device shown in FIG. 1 includes a semiconductor chip having a logic block such as a CPU, ie, a logic chip 10, and a semiconductor chip having a memory block including a DRAM memory cell array, ie, a DRAM chip 20, which is a chip-on-chip. With structure. Both chips 10 and 20 are connected to each other via chip connection electrodes 11 and 21 provided on the respective chips such that the main surfaces thereof face each other. In the logic chip 10, reference numeral 12 denotes an SRAM, reference numeral 13 denotes an SRAM memory control circuit, and reference numeral 100 denotes a DRAM memory control circuit. The memory control circuit 100 for the DRAM includes an address signal supply circuit 14 for supplying an address signal designating a normal memory cell to be accessed on the DRAM chip 20, a remedy address programmed and an address represented by the address signal. And a relief determination circuit 15 for generating a redundancy control signal indicating the match / mismatch of
[0015]
FIG. 2 shows an electrode configuration of the DRAM chip 20 in FIG. The DRAM chip 20 is provided with a probe electrode 22 for receiving a test input from the outside and outputting a response to the test input to the outside, in addition to the above-described chip connection electrode 21, at a peripheral portion.
[0016]
FIG. 3 shows a circuit configuration example of each of the logic chip 10 and the DRAM chip 20 in FIG. On the logic chip 10, the DRAM memory control circuit 100 receives a memory address signal ADR given from a CPU (not shown) and a clock signal CLK given from a clock generation circuit (not shown). In the DRAM chip 20, 200 is an address processing circuit, and 300 is a memory cell array. The address processing circuit 200 has a role of selecting a memory cell to be accessed in the memory cell array 300 based on a signal supplied from the memory control circuit 100 via the chip connection electrodes 11 and 21. In the single state of the DRAM chip 20, when the test probe needle of the tester 18 contacts the probe electrode 22, the address processing circuit 200 can receive a test input instead of a signal from the memory control circuit 100 from the tester 18. . The illustration and description of the data flow between the logic chip 10 and the DRAM chip 20 and the data flow between the tester 18 and the DRAM chip 20 are omitted.
[0017]
FIG. 4 shows a detailed configuration example of the memory cell array 300 in FIG. The memory cell array 300 has a normal memory cell area 301 and a redundant memory cell area 302 for relieving defects. The normal memory cell 303 is specified by a combination of the row direction memory selection signal Xi and the column direction memory selection signal Yj. When the normal memory cell 303 has a defect, the redundant memory cell 304 to be selected instead of the normal memory cell 303 is specified by, for example, a combination of a row-direction redundant memory selection signal SXm and a column-direction memory selection signal Yj. You. A redundant memory cell can be designated by a combination of the row direction memory selection signal Xi and the column direction redundancy memory selection signal SYn, or a combination of the row direction redundancy memory selection signal SXm and the column direction redundancy memory selection signal SYn. . The SRAM 12 in FIG. 1 also has the same redundant memory configuration as that in FIG.
[0018]
FIG. 5 shows a detailed configuration example of each of the memory control circuit 100 and the address processing circuit 200 in FIG. The detailed configurations of the memory control circuit 100 and the address processing circuit 200 will be sequentially described.
[0019]
The memory control circuit 100 has an address signal supply circuit 14, a relief determination circuit 15, and a timing control circuit 106. The address signal supply circuit 14 latches a memory address signal ADR given from a CPU (not shown) and supplies a row address signal DXA and a column address signal DYA, and a column address signal DYA for a predetermined time. t _RCD And a delay circuit 103 for supplying a delayed column address signal PDYA obtained by delaying only by a delay. The latch circuit 101 operates in synchronization with the clock signal CLK. The rescue determination circuit 15 includes a row redundancy control circuit 102 for generating a row redundancy control signal DFX indicating a match / mismatch between the programmed rescue row address and the address represented by the row address signal DXA, and a programmed rescue column. A column redundancy control circuit 104 for generating a column redundancy control signal DFY indicating a match / mismatch between an address and an address represented by the column address signal DYA; _RCD And a delay circuit 105 for supplying a delay column redundancy control signal PDFY obtained by delaying by only a delay. The timing control circuit 106 receives a memory read request signal RD and the like in addition to the clock signal CLK, and activates a fuse circuit enable signal FEN for activating the row redundancy control circuit 102 and the column redundancy control circuit 104, and a row address signal DXA. And a function of supplying a row address strobe signal NRAS indicating the valid timing of the row redundancy control signal DFX and a column address strobe signal NCAS indicating the valid timing of the delayed column address signal PDYA and the delayed column redundancy control signal PDFY. Therefore, the row address strobe signal NRAS together with the row address signal DXA and the row redundancy control signal DFX, and the column address strobe signal NCAS along with the delayed column address signal PDYA and the delayed column redundancy control signal PDFY are transmitted from the memory control circuit 100 to the address processing circuit 200, respectively. Supplied to Note that "N" in NRAS and NCAS indicates that these address strobe signals are negative logic signals.
[0020]
On the other hand, the address processing circuit 200 has an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a normal column decoder 204, and a column redundancy driver 205. Input circuit 201 operates in synchronization with clock signal CLK, latches row address signal DXA and row redundancy control signal DFX according to row address strobe signal NRAS, and outputs internal row address signal XA and internal row redundancy control signal FX to the column. This is a circuit for latching the delayed column address signal PDYA and the delayed column redundancy control signal PDFY in accordance with the address strobe signal NCAS and supplying the internal column address signal YA and the internal column redundancy control signal FY, respectively. Normal row decoder 202 decodes internal row address signal XA and supplies row direction memory selection signal X to memory cell array 300 when internal row redundancy control signal FX indicates address mismatch. Row redundancy driver 203 supplies a row direction redundancy memory selection signal SX to memory cell array 300 according to internal row redundancy control signal FX. Normal column decoder 204 decodes internal column address signal YA and supplies column direction memory selection signal Y to memory cell array 300 when internal column redundancy control signal FY indicates address mismatch. The column redundancy driver 205 supplies a column direction redundancy memory selection signal SY to the memory cell array 300 according to the internal column redundancy control signal FY.
[0021]
FIG. 6 shows a detailed configuration example of the row redundancy control circuit 102 in FIG. The row redundancy control circuit 102 includes a plurality of rescue address determination circuits 110 each of which can program one rescue row address. Each relief address determination circuit 110 has an address program circuit 111 and an address comparison circuit 112. The address program circuit 111 includes fuse circuits 120 equal in number to the number of bits in the rescue row address, and one inverter 130 for supplying an inverted signal of the fuse circuit enable signal FEN to each fuse circuit 120. Each fuse circuit 120 includes one P-channel MOS transistor 121, two N-channel MOS transistors 122 and 123, one inverter 124, and one fuse 125 that can be cut by a laser. . R0 / NR0 in FIG. 6 is a complementary bit signal. When the fuse circuit enable signal FEN holds an inactive level (Low level), R0 = High and NR0 regardless of whether the fuse 125 is cut or not. = Low. When the fuse circuit enable signal FEN is activated to a high level, R0 = High and NR0 = Low when the fuse 125 is cut, and R0 = Low and NR0 = High when the fuse 125 is not cut. It becomes. The sum of the complementary bit signals R0 / NR0 of each fuse circuit 120 is the rescue row address signal RX, and the address comparison circuit 112 determines whether the rescue row address signal RX matches the row address signal DXA. F0 in FIG. 6 is one rescue address discrimination signal. When the rescue row address signal RX and the row address signal DXA match, F0 = High, and when they do not match, F0 = Low. The above-mentioned row redundancy control signal DFX is obtained by summarizing the determination results of the respective relief address determination circuits 110. The internal configuration of the column redundancy control circuit 104 in FIG. 5 is the same as that in FIG. The SRAM memory control circuit 13 in FIG. 1 also has a fuse circuit for rescue address programming as in FIG.
[0022]
FIG. 7 shows a detailed configuration example of the normal row decoder 202 in FIG. When the internal row redundancy control signal FX indicates address mismatch, that is, when all the bits of the internal row redundancy control signal FX are low, the normal row decoder 202 outputs the decoding result of the internal row address signal XA to the row direction memory selection signal. A plurality of decoders 140 to 142, a plurality of two-input AND gates 143 to 145, and one multi-input OR gate 146 are provided so as to supply X. The internal configuration of the normal column decoder 204 in FIG. 5 is the same as that in FIG.
[0023]
FIG. 8 shows a detailed configuration example of the row redundancy driver 203 in FIG. The row redundancy driver 203 includes a plurality of drivers 150 to 152 so as to supply a row redundancy memory selection signal SX corresponding to each bit of the internal row redundancy control signal FX. The internal configuration of the column redundancy driver 205 in FIG. 5 is the same as that in FIG.
[0024]
9 shows the operation of the memory control circuit 100 in FIG. 5, and FIG. 10 shows the operation of the address processing circuit 200 in FIG. T0 to T5 each represent one cycle of the clock signal CLK. Here, t _RCD Correspond to two cycles of the clock signal CLK.
[0025]
According to FIG. 9, when a memory address signal ADR is issued from a CPU (not shown) in the cycle T0, the latch circuit 101 latches the memory address signal ADR in synchronization with the rising edge of the clock signal CLK in the cycle T1. , A row address signal DXA corresponding to the upper part of the memory address signal ADR and a column address signal DYA corresponding to the lower part of the memory address signal ADR. The row redundancy control circuit 102 and the column redundancy control circuit 104 immediately start the rescue judgment, and the row redundancy control signal DFX and the column redundancy control signal DFY are determined in the cycle T1. The broken line (High level) of DFX in FIG. 9 indicates the case where the row addresses match, and the solid line of DFX indicates the case where the row addresses do not match. A broken line (high level) of DFY indicates a case where the column addresses match, and a solid line of DFY indicates a case where the column addresses do not match. The delayed column address signal PDYA is a signal delayed by two cycles of the column address signal DYA, and the delayed column redundancy control signal PDFY is a signal delayed by two cycles of the column redundancy control signal DFY. After supplying the row address strobe signal NRAS so as to indicate a low level when the clock signal CLK rises in the cycle T2, the timing control circuit 106 supplies the column address strobe signal so as to indicate a low level when the clock signal CLK rises in the cycle T4. Supply NCAS.
[0026]
On the other hand, according to FIG. 10, the input circuit 201 latches the row address signal DXA and the row redundancy control signal DFX in synchronization with the rising edge of the clock signal CLK in the cycle T2 in accordance with the row address strobe signal NRAS. An internal row address signal XA and an internal row redundancy control signal FX are supplied. In response, the row direction memory selection signal X and the row direction redundancy memory selection signal SX are determined in the cycle T2. Further, according to the column address strobe signal NCAS, the input circuit 201 latches the delayed column address signal PDYA and the delayed column redundancy control signal PDFY in synchronization with the rising edge of the clock signal CLK in cycle T4, and the internal column address as a result is latched. A signal YA and an internal column redundancy control signal FY are supplied. In response, the column direction memory selection signal Y and the column direction redundancy memory selection signal SY are determined in the cycle T4.
[0027]
As described above, according to the memory control circuit 100 and the address processing circuit 200 shown in FIG. 5, the row redundancy control signal DFX and the column redundancy control signal DFX representing the result of the repair determination by the repair determination circuit 15 on the logic chip 10 are generated. Since the determination is made early, the time from when the memory address signal ADR is input from the CPU to the memory control circuit 100 to when the memory cell is selected in the DRAM chip 20 can be reduced as compared with the related art. Further, since the rescue determination circuit 15 including the plurality of fuse circuits 120 is provided on the logic chip 10 side, the area of the DRAM chip 20 is reduced, and cost reduction is achieved.
[0028]
FIG. 11 shows a defect repair flow in the semiconductor device of FIG. Steps 401 and 402 are a flow for the DRAM chip 20 alone, and steps 403 to 405 are a flow for the logic chip 10 alone.
[0029]
In step 401, a defect inspection of the DRAM memory cell array 300 is performed using the probe electrode 22 to specify the address of the defective memory cell (the rescue row address and the rescue column address). More specifically, as shown in FIG. 3, the probe needle of the tester 18 is brought into contact with the probe electrode 22 to provide an inspection input from the tester 18 to the DRAM chip 20. In this case, the address-related inspection inputs are the clock signal CLK, the row address signal DXA, the delayed column address signal PDYA, the row address strobe signal NRAS, and the column address strobe signal NCAS. The row redundancy control signal DFX and the delay column redundancy control signal PDFY are both inactivated (all bits are at the low level). Then, the address of the normal memory cell 303 from which correct data cannot be read is specified.
[0030]
In the next step 402, a redundant memory cell replacement confirmation test of the DRAM memory cell array 300 is performed using the probe electrode 22. Specifically, according to the relief address specified in the step 401, not only the clock signal CLK, the row address signal DXA, the delayed column address signal PDYA, the row address strobe signal NRAS and the column address strobe signal NCAS, but also the row redundancy control signal The tester 18 supplies the DFX and the delay column redundancy control signal PDFY to the DRAM chip 20.
[0031]
In step 403, an address of a defective memory cell is specified by performing a defect inspection of the SRAM 12 using a probe electrode (not shown) provided on the logic chip 10.
[0032]
In the next step 404, a program step for each fuse circuit 120 in the DRAM memory control circuit 100 and a program step for each fuse circuit in the SRAM memory control circuit 13 are performed using a known laser repair device. Run continuously. That is, the fuse is cut using the laser repair device to set the use of the redundant memory cell. At this time, the address of the defective memory cell in the DRAM memory cell array 300 specified in the step 401 and the address of the defective memory cell in the SRAM 12 specified in the step 403 are referred to.
[0033]
Further, in the next step 405, a redundant memory cell replacement check test of the SRAM 12 is executed using a probe electrode (not shown) provided on the logic chip 10.
[0034]
In the last step 406, the logic chip 10 and the DRAM chip 20 are connected to each other via the chip connection electrodes 11 and 21 provided respectively.
[0035]
According to the above-described method for repairing a semiconductor device, the defect repair fuse of the DRAM chip 20 is arranged on the logic chip 10 side, and is cut in the same step as the SRAM defect relief fuse on the logic chip 10. Can be. In other words, only one fuse cutting step using the laser repair device is required, thereby improving the throughput and reducing the inspection cost. Further, since the test input of the redundancy control signal (DFX and PDFY in the above example) can be given from the tester 18 via the probe electrode 22 in the DRAM chip 20, the DRAM chip 20 before the chip-on-chip connection is connected. A redundant memory cell replacement check test can be performed.
[0036]
FIG. 12 shows a modification of the configuration of FIG. According to the example of FIG. 12, the delay circuit 105 in the rescue judging circuit 15 in FIG. Therefore, according to FIG. 12, the row address strobe signal NRAS together with the row address signal DXA, the row redundancy control signal DFX and the column redundancy control signal DFY, and the column address strobe signal NCAS along with the delayed column address signal PDYA are respectively stored in the memory control circuit 100. To the address processing circuit 200. The address processing circuit 200 in FIG. 12 includes an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a delay circuit 206, a normal column decoder 204, and a column redundancy driver 205. Input circuit 201 operates in synchronization with clock signal CLK, latches row address signal DXA, row redundancy control signal DFX and column redundancy control signal DFY according to row address strobe signal NRAS, and outputs internal row address signal XA and internal row redundancy. This is a circuit for latching a control signal FX and an internal column redundancy control signal FY, a delayed column address signal PDYA in accordance with a column address strobe signal NCAS, and supplying an internal column address signal YA. Normal row decoder 202 decodes internal row address signal XA and supplies row direction memory selection signal X to memory cell array 300 when internal row redundancy control signal FX indicates address mismatch. Row redundancy driver 203 supplies a row direction redundancy memory selection signal SX to memory cell array 300 according to internal row redundancy control signal FX. Delay circuit 206 outputs internal column redundancy control signal FY for a predetermined time t. _RCD The internal delay train redundancy control signal PFY obtained by delaying the internal delay train is supplied. Normal column decoder 204 decodes internal column address signal YA and supplies column memory select signal Y to memory cell array 300 when internal delay column redundancy control signal PFY indicates address mismatch. The column redundancy driver 205 supplies a column direction redundant memory selection signal SY to the memory cell array 300 according to the internal delay column redundancy control signal PFY.
[0037]
FIG. 13 shows the operation of the memory control circuit 100 in FIG. 12, and FIG. 14 shows the operation of the address processing circuit 200 in FIG. Although detailed description of the timing is omitted, the internal column redundancy control signal FY is determined earlier than in the case where the configuration of FIG. 5 is employed, so that the determination of the column direction redundant memory selection signal SY is hastened.
[0038]
FIG. 15 shows another modification of the configuration of FIG. According to the example of FIG. 15, the delay circuit 103 in the address signal supply circuit 14 and the delay circuit 105 in the repair determination circuit 15 in FIG. Therefore, according to FIG. 15, the timing control circuit 106 generates a single address strobe signal NAS indicating the valid timing of the row address signal DXA, the column address signal DYA, the row redundancy control signal DFX, and the column redundancy control signal DFY. 200. 15 includes an input circuit (latch) 201, a normal row decoder 202, a row redundancy driver 203, a first delay circuit 207, a second delay circuit 206, and a normal column decoder 204. , A column redundancy driver 205. The input circuit 201 operates in synchronization with the clock signal CLK, latches the row address signal DXA, the column address signal DYA, the row redundancy control signal DFX, and the column redundancy control signal DFY according to the address strobe signal NAS, and latches the internal row address signal XA. , An internal column address signal YA, an internal row redundancy control signal FX, and an internal column redundancy control signal FY. Normal row decoder 202 decodes internal row address signal XA and supplies row direction memory selection signal X to memory cell array 300 when internal row redundancy control signal FX indicates address mismatch. Row redundancy driver 203 supplies a row direction redundancy memory selection signal SX to memory cell array 300 according to internal row redundancy control signal FX. The first delay circuit 207 outputs the internal column address signal YA for a predetermined time t. _RCD And an internal delay column address signal PYA obtained by delaying the internal delay column address signal PYA. The second delay circuit 206 outputs the internal column redundancy control signal FY for the predetermined time t. _RCD The internal delay train redundancy control signal PFY obtained by delaying the internal delay train is supplied. Normal column decoder 204 decodes internal delayed column address signal PYA and supplies column memory select signal Y to memory cell array 300 when internal delayed column redundancy control signal PFY indicates address mismatch. The column redundancy driver 205 supplies a column direction redundant memory selection signal SY to the memory cell array 300 according to the internal delay column redundancy control signal PFY.
[0039]
16 shows the operation of the memory control circuit 100 in FIG. 15, and FIG. 17 shows the operation of the address processing circuit 200 in FIG. Although the detailed description of the timing is omitted, since the internal column address signal YA and the internal column redundancy control signal FY are determined earlier than in the case of employing the configuration of FIG. 5, the column direction memory selection signal Y and the column direction redundancy memory are determined. The determination of the selection signal SY is hastened.
[0040]
In the above example, the logic chip 10 and the DRAM chip 20 constitute a semiconductor device having a chip-on-chip structure. However, when the DRAM chip 20 is replaced with another memory chip such as a flash memory chip or an SRAM chip, The present invention is also applicable.
[0041]
Further, the fuse circuit on the logic chip 10 to be cut by the laser repair device in the step 404 in FIG. 11 is not limited to the fuse circuit for repairing the SRAM defect, but is generally used for programming the function of the logic chip 10. Any fuse circuit may be used. This fuse circuit and the fuse circuit 120 for relieving DRAM defects on the logic chip 10 are subjected to a continuous programming step by a laser repair device.
[0042]
Further, in a semiconductor device having a single-chip structure having a logic block and a memory block, the time from address issuance to selection of a memory cell can be reduced by providing a repair determination circuit for repairing a defect in the memory block on the logic block side. This has the advantage that memory access can be speeded up.
[0043]
【The invention's effect】
As described above, according to the present invention, a relief judgment circuit (for example, a fuse circuit) for relieving a defect of a memory chip is provided on the logic chip side, so that memory access is speeded up and the area of the memory chip is increased. Is reduced, and the number of defect repair processes by the laser repair device is reduced. However, in order to shorten the time from address issuance to selection of a memory cell, it is sufficient to provide a repair determination circuit for repairing a defect in a memory block on the logic block side.
[Brief description of the drawings]
FIG. 1 is a schematic exploded perspective view showing an example of a semiconductor device according to the present invention.
FIG. 2 is a plan view showing an electrode configuration of a DRAM chip in FIG.
FIG. 3 is a block diagram illustrating an example of a circuit configuration of each of a logic chip and a DRAM chip in FIG. 1;
FIG. 4 is a conceptual diagram showing a detailed configuration example of a memory cell array in FIG. 3;
FIG. 5 is a block diagram illustrating a detailed configuration example of each of a memory control circuit and an address processing circuit in FIG. 3;
FIG. 6 is a circuit diagram showing a detailed configuration example of a row redundancy control circuit in FIG. 5;
FIG. 7 is a circuit diagram showing a detailed configuration example of a normal row decoder in FIG. 5;
8 is a circuit diagram showing a detailed configuration example of a row redundancy driver in FIG. 5;
FIG. 9 is a timing chart showing an operation of the memory control circuit in FIG. 5;
FIG. 10 is a timing chart showing an operation of the address processing circuit in FIG. 5;
FIG. 11 is a flow chart of repairing defects in the semiconductor device of FIG. 1;
FIG. 12 is a block diagram showing a modification of the configuration of FIG. 5;
FIG. 13 is a timing chart showing the operation of the memory control circuit in FIG.
14 is a timing chart showing the operation of the address processing circuit in FIG.
FIG. 15 is a block diagram showing another modification of the configuration of FIG. 5;
16 is a timing chart showing the operation of the memory control circuit in FIG.
17 is a timing chart showing the operation of the address processing circuit in FIG.
[Explanation of symbols]
10. Logic chip
11 Chip connection electrode
12 SRAM
13. Memory control circuit for SRAM
14. Address signal supply circuit
15 Relief judgment circuit
18 Tester
20 DRAM chips
21 Chip connection electrode
22 Probe electrode
100 DRAM memory control circuit
101 Latch circuit
102 row redundancy control circuit
103 delay circuit
104 column redundancy control circuit
105 delay circuit
106 Timing control circuit
110 Relief address determination circuit
111 address program circuit
112 address comparison circuit
120 fuse circuit
125 fuse
200 address processing circuit
201 Input circuit (latch)
202 Normal row decoder
203 row redundancy driver
204 Normal column decoder
205 row redundant driver
206 delay circuit
207 delay circuit
300 memory cell array
301 Normal memory cell area
302 Redundant memory cell area
303 Normal memory cell
304 redundant memory cell
ADR memory address signal
CLK clock signal
DFX row redundancy control signal
DFY column redundancy control signal
DXA row address signal
DYA column address signal
F0 relief address determination signal
FEN fuse circuit enable signal
FX internal row redundancy control signal
FY Internal column redundancy control signal
NAS address strobe signal
NCAS column address strobe signal
NRAS row address strobe signal
PDFY delay column redundancy control signal
PDYA delay column address signal
PFY Internal delay train redundancy control signal
PYA internal delay column address signal
R0, NR0 complementary bit signal
RX relief row address signal
SX, SXm Row direction redundant memory selection signal
SY, SYn Column direction redundant memory selection signal
X, Xi row direction memory selection signal
XA internal row address signal
Y, Yj column direction memory selection signal
YA Internal column address signal

Claims (9)

A semiconductor device having a logic block and a memory block,
The memory block includes a memory cell array having a plurality of normal memory cells and a plurality of redundant memory cells for relieving defects in the plurality of normal memory cells,
The logic block includes an address signal supply circuit for supplying an address signal specifying a normal memory cell to be accessed among the plurality of normal memory cells, and a match between the programmed relief address and the address represented by the address signal. A memory control circuit having a relief determination circuit for generating a redundancy control signal indicating a mismatch, and a timing control circuit for supplying a strobe signal indicating valid timing of the address signal and the redundancy control signal;
A semiconductor device, wherein the strobe signal is supplied from the logic block to the memory block together with the address signal and the redundancy control signal. The semiconductor device according to claim 1,
The address signal supply circuit latches a given memory address signal to supply a row address signal and a column address signal, and a delayed column address obtained by delaying the column address signal by a predetermined time. A delay circuit for supplying a signal,
The rescue judging circuit includes a row redundancy control circuit for generating a row redundancy control signal indicating a match / mismatch between the programmed rescue row address and the address represented by the row address signal; a programmed rescue column address; A column redundancy control circuit for generating a column redundancy control signal indicating a match / mismatch with an address represented by a column address signal; and a delay column redundancy control signal obtained by delaying the column redundancy control signal by the predetermined time. And a delay circuit for supplying
The timing control circuit includes: a row address strobe signal indicating valid timing of the row address signal and the row redundancy control signal; and a column address strobe signal indicating valid timing of the delayed column address signal and the delayed column redundancy control signal. Has the function of supplying, and
The memory block includes:
Latching the row address signal and the row redundancy control signal in accordance with the row address strobe signal to convert an internal row address signal and an internal row redundancy control signal to the delayed column address signal and the delayed column redundancy control signal in accordance with the column address strobe signal An input circuit for latching and supplying an internal column address signal and an internal column redundancy control signal, respectively.
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A normal column decoder for decoding the internal column address signal and supplying a column direction memory selection signal to the memory cell array when the internal column redundancy control signal indicates an address mismatch;
And a column redundancy driver for supplying a column direction redundancy memory selection signal to the memory cell array in accordance with the internal column redundancy control signal. The semiconductor device according to claim 1,
The address signal supply circuit latches a given memory address signal to supply a row address signal and a column address signal, and a delayed column address obtained by delaying the column address signal by a predetermined time. A delay circuit for supplying a signal,
The rescue judging circuit includes a row redundancy control circuit for generating a row redundancy control signal indicating a match / mismatch between the programmed rescue row address and the address represented by the row address signal; a programmed rescue column address; A column redundancy control circuit for generating a column redundancy control signal indicating a match / mismatch with the address represented by the column address signal,
The timing control circuit supplies a row address strobe signal indicating valid timing of the row address signal, the row redundancy control signal and the column redundancy control signal, and a column address strobe signal indicating valid timing of the delayed column address signal. Have the function of
The memory block includes:
The row address signal, the row redundancy control signal and the column redundancy control signal are latched in accordance with the row address strobe signal, and an internal row address signal, an internal row redundancy control signal and an internal column redundancy control signal are latched in accordance with the column address strobe signal. An input circuit for latching the delayed column address signal and supplying an internal column address signal, respectively;
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A delay circuit for supplying an internal delay column redundancy control signal obtained by delaying the internal column redundancy control signal by the predetermined time;
A normal column decoder for decoding the internal column address signal and supplying a column direction memory selection signal to the memory cell array when the internal delay column redundancy control signal indicates an address mismatch;
A semiconductor device further comprising a column redundancy driver for supplying a column direction redundant memory selection signal to the memory cell array according to the internal delay column redundancy control signal. The semiconductor device according to claim 1,
The address signal supply circuit has a latch circuit for latching a given memory address signal and supplying a row address signal and a column address signal,
The rescue judging circuit includes a row redundancy control circuit for generating a row redundancy control signal indicating a match / mismatch between the programmed rescue row address and the address represented by the row address signal; a programmed rescue column address; A column redundancy control circuit for generating a column redundancy control signal indicating a match / mismatch with the address represented by the column address signal,
The timing control circuit has a function of supplying a single address strobe signal indicating an effective timing of the row address signal, the column address signal, the row redundancy control signal and the column redundancy control signal, and
The memory block includes:
The row address signal, the column address signal, the row redundancy control signal, and the column redundancy control signal are latched according to the address strobe signal to generate an internal row address signal, an internal column address signal, an internal row redundancy control signal, and an internal column redundancy control. An input circuit for supplying each signal,
A normal row decoder for decoding the internal row address signal and supplying a row direction memory selection signal to the memory cell array when the internal row redundancy control signal indicates an address mismatch;
A row redundancy driver for supplying a row direction redundancy memory selection signal to the memory cell array according to the internal row redundancy control signal;
A first delay circuit for supplying an internal delay column address signal obtained by delaying the internal column address signal by a predetermined time;
A second delay circuit for supplying an internal delay column redundancy control signal obtained by delaying the internal column redundancy control signal by the predetermined time;
A normal column decoder for decoding the internal delay column address signal and supplying a column direction memory selection signal to the memory cell array when the internal delay column redundancy control signal indicates an address mismatch;
A semiconductor device further comprising a column redundancy driver for supplying a column direction redundant memory selection signal to the memory cell array according to the internal delay column redundancy control signal. The semiconductor device according to claim 1,
A semiconductor device, wherein the logic block and the memory block are formed on separate semiconductor chips, respectively, and are connected to each other via chip connection electrodes. The semiconductor device according to claim 5,
A semiconductor device, wherein the semiconductor chip on which the memory block is formed includes a probe electrode for receiving test inputs of the address signal, the redundancy control signal, and the strobe signal from outside. The semiconductor device according to claim 5,
The semiconductor chip on which the logic block is formed includes a fuse circuit for programming a function of the logic block, and a fuse circuit for programming the relief address in the relief determination circuit. Semiconductor device. A method for repairing a defect in a semiconductor device according to claim 6,
Performing a defect inspection of the memory cell array using the probe electrodes on a single semiconductor chip on which the memory block is formed;
Performing a redundancy memory cell replacement confirmation test of the memory cell array using the probe electrodes on a single semiconductor chip on which the memory block is formed. A method for repairing a defect in a semiconductor device according to claim 7,
A method of repairing a semiconductor device, wherein a step of programming the two fuse circuits by a laser repair device is continuously performed on a single semiconductor chip on which the logic block is formed.

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