JPH09266219A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH09266219A
JPH09266219A JP8073357A JP7335796A JPH09266219A JP H09266219 A JPH09266219 A JP H09266219A JP 8073357 A JP8073357 A JP 8073357A JP 7335796 A JP7335796 A JP 7335796A JP H09266219 A JPH09266219 A JP H09266219A
Authority
JP
Japan
Prior art keywords
die pad
pad portion
semiconductor chip
die
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8073357A
Other languages
Japanese (ja)
Inventor
Seiichi Yatsugayo
聖一 八ケ代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8073357A priority Critical patent/JPH09266219A/en
Publication of JPH09266219A publication Critical patent/JPH09266219A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

PROBLEM TO BE SOLVED: To improve the yield of production in wire bonding process and to make it possible to uniformly apply Ag paste to a die pad part by improving the positional accuracy of a semiconductor chip when a die bonding operation is conducted. SOLUTION: A vacuum suction hole 12, where a die pad part 2a is held fast in evacuation, is formed on the bottom face of the recessed part 11a of a mounting plate 11. Consequently, as the die pad part 2a is fixed accurately in a horizontal state, the positional accuracy of a semiconductor chip can be improved when a die bonding operation is conducted. Accordingly, the yield of production in a wire bonding process can be improved, Ag paste can be applied uniformly on the die pad part, and the quality of finished goods can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
装置に関し、さらに詳しくは、マウントプレートに、リ
ードフレームのダイパッド部に対応する凹所を形成し、
該凹所に沿って上記リードフレームを間欠的に送りなが
ら、上記ダイパッド部表面に半導体チップを接合する接
合材料を塗布する工程、上記ダイパッド部表面に上記半
導体チップを接合する工程および上記半導体チップの接
続電極と上記リードフレームのリード部とをワイヤ接続
する工程のうち、少なくとも１つの工程を施すようにし
た半導体装置の製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing apparatus, and more particularly to a mount plate having a recess corresponding to a die pad portion of a lead frame.
A step of applying a bonding material for bonding a semiconductor chip to the surface of the die pad portion while intermittently feeding the lead frame along the recess, a step of bonding the semiconductor chip to the surface of the die pad portion, and The present invention relates to a semiconductor device manufacturing apparatus in which at least one of the steps of wire-connecting the connection electrode and the lead portion of the lead frame is performed.

【０００２】[0002]

【従来の技術】図７は従来の半導体装置の製造装置にお
けるマウントプレート１を示しており、その中央部には
凹所１ａが形成されている。これは図８に示すように、
ディプレスのあるリードフレーム２を載置することがで
きるようになっている。ディプレスとは、図９および図
１０に示すようにダイパッド部２ａを周囲のインナリー
ド部２ｂより一段低く凹ませた形状のことをいい、半導
体チップ５の表面の高さをインナリード部２ｂの高さに
近づけて、半導体チップ５の接続電極とインナリード部
２ｂとをワイヤ接続する工程、すなわちワイヤボンディ
ングを容易にするために行われる。また図１１および図
１２に示すように、このディプレスを行うことによりボ
ンディングワイヤ４とダイパッド部２ａとの間の距離ｓ
が大きくなるので、インナリード部２ｂとダイパッド部
２ａとのショート不良を起こしにくくしている。2. Description of the Related Art FIG. 7 shows a mount plate 1 in a conventional semiconductor device manufacturing apparatus, in which a recess 1a is formed in the center thereof. This is as shown in FIG.
It is possible to mount the lead frame 2 having a depression. The depression is a shape in which the die pad portion 2a is recessed one step lower than the surrounding inner lead portion 2b as shown in FIGS. 9 and 10, and the height of the surface of the semiconductor chip 5 is set to the inner lead portion 2b. This process is performed in order to facilitate wire bonding between the connection electrode of the semiconductor chip 5 and the inner lead portion 2b by approaching the height, that is, wire bonding. Further, as shown in FIGS. 11 and 12, by performing this depressing, the distance s between the bonding wire 4 and the die pad portion 2a is increased.
Therefore, the short circuit between the inner lead portion 2b and the die pad portion 2a is less likely to occur.

【０００３】一般に、リードフレーム２は厚さ２５〜２
５０μｍの金属製で、そのダイパッド部２ａの表面に半
導体チップ５を接合する工程、すなわちダイボンディン
グが自動ボンディング装置により行われる場合は、この
リードフレーム２を連続して送り、これを収納工具（マ
ガジン）に搬送し収納している。図１３にダイボンディ
ング工程の様子を模式的に示すが、リードフレーム２は
図において左右に延在してマウントプレート１に載置さ
れており、その凹所１ａに沿ってリードフレーム２を右
方へと間欠的に送りながら、ダイボンディングが行われ
る。これは、ダイパッド部２ａが所定位置に到達したと
きに一旦停止し、そこでリードフレーム押え部材（図８
参照）により固定された状態で、上方のコレット７によ
り一個ずつ吸着保持された半導体チップ５が下方のダイ
パッド部２ａに接合されるようになっている。これが繰
り返し行われることにより、下流側のリードフレームに
連続してダイボンディングが行われる。Generally, the lead frame 2 has a thickness of 25 to 2
When the step of bonding the semiconductor chip 5 to the surface of the die pad portion 2a made of metal of 50 μm, that is, die bonding is performed by an automatic bonding apparatus, this lead frame 2 is continuously fed and stored in a storage tool (magazine). ) And stores it. FIG. 13 schematically shows the state of the die bonding process. The lead frame 2 extends left and right in the figure and is mounted on the mount plate 1, and the lead frame 2 is placed rightward along the recess 1a. The die bonding is carried out while intermittently sending to. This is temporarily stopped when the die pad portion 2a reaches a predetermined position, where the lead frame pressing member (see FIG.
The semiconductor chips 5 suction-held one by one by the upper collet 7 are fixed to the lower die pad portion 2a. By repeating this, die bonding is continuously performed on the lead frame on the downstream side.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、従来の
マウントプレート１は、図８に示すようにリードフレー
ム押え部材３によりリードフレーム２を固定する形態で
あるために、ディプレスのあるリードフレーム２は構造
上、リード部は固定できてもダイパッド部２ａを確実に
固定することができず、ダイパッド部２ａがマウントプ
レート１の凹所１ａ内で動くという問題がある。However, the conventional mount plate 1 has a form in which the lead frame 2 is fixed by the lead frame pressing member 3 as shown in FIG. Due to the structure, although the lead portion can be fixed, the die pad portion 2a cannot be surely fixed, and there is a problem that the die pad portion 2a moves within the recess 1a of the mount plate 1.

【０００５】すなわち、ダイボンディングが行われる
際、ダイパッド部２ａに接合材料としてＡｇペースト
（エポキシ樹脂に銀（Ａｇ）粉などを混入したもの）６
を塗布するのであるが、このとき、図１４に示されるよ
うに、ダイパッド部２ａが凹所１ａ内で水平面に対して
傾いた状態の場合、Ａｇペースト塗布用マルチノズル８
のノズル部８ａ先端がダイパッド部２ａの表面に均等に
接触しないことにより、図１５に示すようにＡｇペース
ト６の量にバラツキが発生するという問題がある。That is, when die bonding is performed, an Ag paste (a mixture of epoxy resin with silver (Ag) powder or the like) 6 is used as a bonding material for the die pad portion 2a.
At this time, as shown in FIG. 14, when the die pad portion 2a is tilted with respect to the horizontal plane within the recess 1a, the multi-nozzle 8 for Ag paste application is applied.
Since the tip of the nozzle portion 8a does not evenly contact the surface of the die pad portion 2a, there is a problem that the amount of the Ag paste 6 varies as shown in FIG.

【０００６】またダイボンディング時にダイパッド部２
ａが水平面に対して傾いていた場合、図１６に示すよう
にダイパッド部２ａは傾いたままの状態であるが、半導
体チップ５は水平の状態で接合されることになる。これ
によりダイパッド部２ａが水平状態になったときには接
合された半導体チップ５は図１７に示すように傾いた状
態となって半導体チップ５の高さにバラツキが大きくな
ってしまい、ワイヤボンディング時にボール付かずとい
った接続不良が発生するという問題がある。The die pad portion 2 is used for die bonding.
When a is tilted with respect to the horizontal plane, the die pad portion 2a remains tilted as shown in FIG. 16, but the semiconductor chip 5 is bonded in a horizontal state. As a result, when the die pad portion 2a is in a horizontal state, the joined semiconductor chip 5 is inclined as shown in FIG. 17 and the height of the semiconductor chip 5 varies greatly. There is a problem that poor connection such as azu occurs.

【０００７】なお、特開昭６３−１２２２２６号および
特開昭６３−２４６８４０号公報には、半導体チップを
正しく位置決めしてダイボンディングを行うことができ
る装置を開示しているが、これらはコレットにより半導
体チップを正しく位置決めされた状態で吸着保持する装
置であり、ダイパッド部が上述したように水平面に対し
て傾いている場合においては、結局、半導体チップの位
置精度は崩れてしまうので、これら装置によって上記問
題を解決することはできない。また特開平４−２１５９
１０号公報には、真空吸着作用により半導体チップを所
定の姿勢に保持した状態で次工程に供給する装置が開示
されているが、これもまた同様な理由で上記問題を解決
することはできない。Incidentally, Japanese Patent Laid-Open Nos. 63-122226 and 63-246840 disclose a device capable of correctly positioning a semiconductor chip and performing die bonding. This is a device that suction-holds a semiconductor chip in a correctly positioned state, and in the case where the die pad portion is tilted with respect to the horizontal plane as described above, the position accuracy of the semiconductor chip will be destroyed in the end. The above problems cannot be solved. In addition, JP-A-4-2159
Japanese Unexamined Patent Application Publication No. 10 discloses an apparatus for supplying a semiconductor chip to a next step while holding it in a predetermined posture by a vacuum suction action, but this also cannot solve the above problem for the same reason.

【０００８】本発明は上述の問題に鑑みてなされ、ダイ
ボンディング時における半導体チップの位置精度を向上
させて、ワイヤボンディング工程の歩留りを向上させる
とともに、Ａｇペーストを均等にダイパッド部に塗布す
ることができる半導体装置の製造装置を提供することを
目的とする。The present invention has been made in view of the above problems, and it is possible to improve the positional accuracy of a semiconductor chip during die bonding, improve the yield of the wire bonding process, and evenly apply the Ag paste to the die pad portion. An object of the present invention is to provide a semiconductor device manufacturing apparatus capable of manufacturing the semiconductor device.

【０００９】[0009]

【課題を解決するための手段】以上の目的は、マウント
プレートに、リードフレームのダイパッド部に対応する
凹所を形成し、該凹所に沿って前記リードフレームを間
欠的に送りながら、前記ダイパッド部表面に半導体チッ
プを接合する接合材料を塗布する工程、前記ダイパッド
部表面に前記半導体チップを接合する工程および前記半
導体チップの接続電極と前記リードフレームのリード部
とをワイヤ接続する工程のうち、少なくとも１つの工程
を施すようにした半導体装置の製造装置において、前記
凹所の底面に真空吸着用孔を形成し、該真空吸着用孔に
排気装置を接続し、前記何れかの工程を施す際、前記排
気装置を駆動して前記真空吸着用孔で前記ダイパッド部
を真空固持するようにしたことを特徴とする半導体装置
の製造装置、によって達成される。The above object is to form a recess corresponding to a die pad portion of a lead frame on a mount plate, and to intermittently feed the lead frame along the recess while the die pad is being fed. Of the step of applying a bonding material for bonding the semiconductor chip to the surface of the part, the step of bonding the semiconductor chip to the surface of the die pad part, and the step of wire-connecting the connection electrode of the semiconductor chip and the lead part of the lead frame, In a semiconductor device manufacturing apparatus in which at least one step is performed, a vacuum suction hole is formed in the bottom surface of the recess, an exhaust device is connected to the vacuum suction hole, and any one of the steps is performed. According to another aspect of the present invention, there is provided a semiconductor device manufacturing apparatus, characterized in that the exhaust device is driven to hold the die pad portion in vacuum by the vacuum suction hole. It is achieved Te.

【００１０】上記構成により、ダイパッド部は排気装置
に接続される真空吸着用孔で真空固持されることになる
ので、排気装置の駆動中、ダイパッド部は常にマウント
プレートの凹所内で水平状態に保たれることになり、こ
れによりダイボンディング時には常に、半導体チップの
ダイパッド部に対する位置が正しい状態で接合される。
すなわち、半導体チップの高さのバラツキが抑えられ
る。よってワイヤボンディング時に、半導体チップの高
さのバラツキが大きいことによる接続不良の発生を防止
することができ、ワイヤボンディング工程の歩留りを向
上させることができる。さらに、ダイパッド部と半導体
チップとを接合する接合材料（Ａｇペースト）をダイパ
ッド部に均等に塗布することができる。With the above structure, since the die pad portion is vacuum-held in the vacuum suction hole connected to the exhaust device, the die pad portion is always kept horizontal in the recess of the mount plate while the exhaust device is driven. As a result, the semiconductor chip is always bonded in the correct position with respect to the die pad portion during die bonding.
That is, variations in height of the semiconductor chips can be suppressed. Therefore, at the time of wire bonding, it is possible to prevent the occurrence of connection failure due to large variations in the height of the semiconductor chip, and it is possible to improve the yield of the wire bonding process. Further, the bonding material (Ag paste) for bonding the die pad portion and the semiconductor chip can be evenly applied to the die pad portion.

【００１１】[0011]

【発明の実施の形態】マウントプレートの凹所の底面に
真空吸着用孔を形成し、この真空吸着用孔に真空ポンプ
等の排気装置を接続する。この排気装置は、ダイパッド
部表面に半導体チップを接合する接合材料（Ａｇペース
ト）を塗布する工程、ダイパッド部表面に半導体チップ
を接合する工程（ダイボンディング工程）および半導体
チップの接続電極とリードフレームのインナリード部と
をワイヤ接続する工程（ワイヤボンディング工程）のう
ち、何れかの工程を施す際に駆動して、上記真空吸着用
孔でダイパッド部を真空固持するように構成する。BEST MODE FOR CARRYING OUT THE INVENTION A vacuum suction hole is formed in the bottom surface of a recess of a mount plate, and an exhaust device such as a vacuum pump is connected to this vacuum suction hole. In this exhaust device, a step of applying a bonding material (Ag paste) for bonding a semiconductor chip to the surface of the die pad portion, a step of bonding a semiconductor chip to the surface of the die pad portion (die bonding step), a connection electrode of the semiconductor chip and a lead frame The die pad portion is configured to be vacuum-held in the vacuum suction hole by driving when any one of the steps of wire connection with the inner lead portion (wire bonding step) is performed.

【００１２】これにより、排気装置の駆動中、ダイパッ
ド部は常にマウントプレートの凹所内で水平状態に保た
れることになり、これによりダイボンディング時には常
に、半導体チップのダイパッド部に対する位置が正しい
状態で接合される。すなわち、半導体チップの高さのバ
ラツキが抑えられる。よってワイヤボンディング時に、
半導体チップの高さのバラツキが大きいことによるワイ
ヤの接続不良の発生を防止することができ、ワイヤボン
ディング工程の歩留りを向上させることができる。さら
に、Ａｇペーストをダイパッド部に均等に塗布すること
ができるので、Ａｇペースト厚が安定化し、製品の品質
を向上させることができる。As a result, the die pad portion is always kept in the horizontal state in the recess of the mount plate during driving of the exhaust device, so that the position of the semiconductor chip with respect to the die pad portion is always correct during die bonding. To be joined. That is, variations in height of the semiconductor chips can be suppressed. Therefore, at the time of wire bonding,
It is possible to prevent the occurrence of defective wire connection due to the large variation in the height of the semiconductor chip, and it is possible to improve the yield of the wire bonding process. Furthermore, since the Ag paste can be evenly applied to the die pad portion, the Ag paste thickness is stabilized and the product quality can be improved.

【００１３】[0013]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１４】図１は本発明の実施例による半導体装置の
製造装置におけるマウントプレート１１を示す。マウン
トプレート１１の中央部には凹所１１ａが形成されてお
り、この凹所１１ａの底面には真空吸着用孔１２が形成
されている。また、この真空吸着用孔１２には真空バル
ブ１３を介して真空ポンプ１４が接続されている。本発
明の構成要素である排気装置はこれら真空バルブ１３お
よび真空ポンプ１４により構成される。本実施例では、
Ａｇペースト塗布工程、ダイボンディング工程およびワ
イヤボンディング工程が行われる位置に上記マウントプ
レート１１が配設されており、これら３工程のうち何れ
かが施されるときに、真空バルブ１３が開弁するように
なっている。FIG. 1 shows a mount plate 11 in a semiconductor device manufacturing apparatus according to an embodiment of the present invention. A recess 11a is formed in the center of the mount plate 11, and a vacuum suction hole 12 is formed on the bottom surface of the recess 11a. A vacuum pump 14 is connected to the vacuum suction hole 12 via a vacuum valve 13. The exhaust device, which is a component of the present invention, is composed of these vacuum valve 13 and vacuum pump 14. In this embodiment,
The mount plate 11 is disposed at a position where the Ag paste applying process, the die bonding process and the wire bonding process are performed, and the vacuum valve 13 is opened when any of these three processes is performed. It has become.

【００１５】本実施例による半導体装置の製造装置は以
上のように構成されるのであるが、次のこの作用効果に
ついて説明する。The semiconductor device manufacturing apparatus according to the present embodiment is configured as described above, and the operation and effect thereof will be described below.

【００１６】Ａｇペースト塗布工程にダイパッド部２ａ
が到達すると、真空バルブ１３が開弁し、これにより真
空吸着用孔１２でダイパッド部２ａが真空固持される。
このときダイパッド部２ａが水平面に対して傾いていて
も、真空ポンプ１４の真空吸着作用によりこの傾きが強
制的に直され、ダイパッド部２ａは水平状態に真空固持
される。したがって、図２および図３に示すようにＡｇ
ペースト塗布用マルチノズル８のノズル部８ａの先端が
ダイパッド部２ａの表面に均一に接触することができる
ので、ダイパッド部２ａにＡｇペースト６を均等に塗布
することができる。これにより、Ａｇペースト厚を安定
化させることができ、製品の品質を向上させることがで
きる。In the Ag paste application process, the die pad portion 2a
When is reached, the vacuum valve 13 is opened, whereby the die pad portion 2a is vacuum-held in the vacuum suction hole 12.
At this time, even if the die pad portion 2a is inclined with respect to the horizontal plane, this inclination is forcibly corrected by the vacuum suction action of the vacuum pump 14, and the die pad portion 2a is vacuum-held in a horizontal state. Therefore, as shown in FIG. 2 and FIG.
Since the tip of the nozzle portion 8a of the paste applying multi-nozzle 8 can contact the surface of the die pad portion 2a uniformly, the Ag paste 6 can be evenly applied to the die pad portion 2a. Thereby, the Ag paste thickness can be stabilized and the quality of the product can be improved.

【００１７】そしてダイボンディング工程においても、
ダイパッド部２ａを真空吸着用孔１２で真空固持した状
態で半導体チップ５を接合する。これによりダイパッド
部２ａは水平状態で強固に固持された状態で半導体チッ
プ５を接合することができるので、図４に示すように半
導体チップ５を確実にダイパッド部２ａの所定の位置に
接合することができ、またダイボンディング後の半導体
チップ５の高さのバラツキを抑制することができる。Also in the die bonding process,
The semiconductor chip 5 is bonded while the die pad portion 2a is vacuum-held in the vacuum suction hole 12. As a result, the semiconductor chip 5 can be bonded while the die pad portion 2a is firmly held in the horizontal state. Therefore, as shown in FIG. 4, the semiconductor chip 5 must be securely bonded to a predetermined position of the die pad portion 2a. In addition, it is possible to suppress variations in height of the semiconductor chip 5 after die bonding.

【００１８】またワイヤボンディング工程においても同
様に、ダイパッド部２ａを真空吸着用孔１２で真空固持
した状態でワイヤボンディングを行う。これにより作業
中、常にダイパッド部２ａを水平状態に保つことがで
き、また前工程のダイボンディング時による半導体チッ
プ５のバラツキがないので、ボール付かずのような接続
不良を防止することができる。Also in the wire bonding step, wire bonding is similarly performed while the die pad portion 2a is vacuum-held in the vacuum suction holes 12. As a result, the die pad portion 2a can always be kept in a horizontal state during the work, and since there is no variation in the semiconductor chip 5 at the time of die bonding in the previous step, it is possible to prevent a connection failure such as a case where no ball is attached.

【００１９】以上、本発明の実施例について説明した
が、勿論、本発明はこれに限ることなく、本発明の技術
的思想に基づいて種々の変形が可能である。Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

【００２０】例えば以上の実施例では、製造を施すべき
リードフレーム２は単列としたが、複数列であってもよ
い。この場合マウントプレートは、図６に示すように列
数に応じて凹所１５ａ、１５ａおよび真空吸着用孔１
６、１６を形成（この場合は２列）すればよい。また一
個のリードフレーム中にダイパッド部が複数ある場合に
おいても、図６に示すようなマウントプレート１５を用
いることができる。すなわち、ダイパッド部間の距離に
応じて凹所１５ａ間の距離を適宜変更し、かつ凹所１５
ａ、１５ａの底面に真空吸着用孔１６、１６を形成すれ
ばよい。For example, in the above embodiments, the lead frame 2 to be manufactured has a single row, but it may have a plurality of rows. In this case, the mount plate has the recesses 15a, 15a and the vacuum suction holes 1 depending on the number of rows as shown in FIG.
6 and 16 may be formed (in this case, two rows). Further, even when there are a plurality of die pad portions in one lead frame, the mount plate 15 as shown in FIG. 6 can be used. That is, the distance between the recesses 15a is appropriately changed according to the distance between the die pad portions, and
The vacuum suction holes 16 and 16 may be formed on the bottom surfaces of a and 15a.

【００２１】また以上の実施例では、Ａｇペースト塗布
時、ダイボンディング時およびワイヤボンディング時に
ダイパッド部２ａを真空吸着用孔１２で真空固持するよ
うにしたが、Ａｇペースト塗布時およびダイボンディン
グ時のみダイパッド部２ａを真空固持するようにしても
よい。In the above embodiment, the die pad portion 2a is vacuum-held by the vacuum suction holes 12 during Ag paste application, die bonding and wire bonding. However, the die pad is applied only during Ag paste application and die bonding. The portion 2a may be vacuum-held.

【００２２】[0022]

【発明の効果】以上述べたように、本発明の半導体装置
の製造装置によれば、リードフレームのダイパッド部を
確実に固定することができるので、ダイボンディング時
の半導体チップの位置精度を向上させることができ、こ
れによりワイヤボンディング工程における製品の歩留り
を向上させることができる。また、Ａｇペースト厚の安
定化により半導体装置の品質を向上させることができ
る。As described above, according to the semiconductor device manufacturing apparatus of the present invention, since the die pad portion of the lead frame can be securely fixed, the positional accuracy of the semiconductor chip at the time of die bonding is improved. As a result, the yield of products in the wire bonding process can be improved. Further, the quality of the semiconductor device can be improved by stabilizing the Ag paste thickness.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例による半導体装置の製造装置に
おけるマウントプレートを示す斜視図である。FIG. 1 is a perspective view showing a mount plate in a semiconductor device manufacturing apparatus according to an embodiment of the present invention.

【図２】本発明の実施例による半導体装置の製造装置の
作用を説明するための図であり、Ａｇペースト塗布時を
示す拡大断面図である。FIG. 2 is a diagram for explaining the operation of the semiconductor device manufacturing apparatus according to the embodiment of the present invention, and is an enlarged cross-sectional view showing the time when Ag paste is applied.

【図３】図２におけるＡｇペースト塗布後を示す拡大断
面図である。FIG. 3 is an enlarged cross-sectional view showing a state after applying the Ag paste in FIG.

【図４】本発明の実施例による半導体装置の製造装置の
作用を説明するための図であり、ダイボンディング後を
示す拡大断面図である。FIG. 4 is a diagram for explaining the operation of the semiconductor device manufacturing apparatus according to the embodiment of the present invention, which is an enlarged cross-sectional view showing a state after die bonding.

【図５】本発明の実施例による半導体装置の製造装置の
作用を説明するための図であり、ワイヤボンディング後
を示す拡大断面図である。FIG. 5 is a diagram for explaining the operation of the semiconductor device manufacturing apparatus according to the embodiment of the present invention, and is an enlarged cross-sectional view showing a state after wire bonding.

【図６】図１の変形例を示す斜視図である。FIG. 6 is a perspective view showing a modified example of FIG.

【図７】従来例の半導体装置の製造装置におけるマウン
トプレートを示す斜視図である。FIG. 7 is a perspective view showing a mount plate in a conventional semiconductor device manufacturing apparatus.

【図８】従来例のマウントプレートにリードフレームを
載置させたときの状態を示す側面図である。FIG. 8 is a side view showing a state in which a lead frame is mounted on a mount plate of a conventional example.

【図９】図８における要部の斜視図である。9 is a perspective view of a main part in FIG.

【図１０】図９における［１０］−［１０］線方向の断
面図である。10 is a sectional view taken along line [10]-[10] in FIG.

【図１１】ディプレスのないリードフレームの作用を説
明するための拡大断面図である。FIG. 11 is an enlarged cross-sectional view for explaining the operation of the lead frame without depressing.

【図１２】ディプレスのあるリードフレームの作用を説
明するための拡大断面図である。FIG. 12 is an enlarged cross-sectional view for explaining the action of the lead frame with a depress.

【図１３】ダイボンディング工程を説明するための要部
の斜視図である。FIG. 13 is a perspective view of a main part for explaining a die bonding process.

【図１４】従来例の半導体装置の製造装置の作用を説明
するための図であり、Ａｇペースト塗布時を示す拡大断
面図である。FIG. 14 is a diagram for explaining the operation of the conventional semiconductor device manufacturing apparatus, and is an enlarged cross-sectional view showing the time when Ag paste is applied.

【図１５】図１４におけるＡｇペースト塗布後を示す拡
大断面図である。15 is an enlarged cross-sectional view showing a state after applying the Ag paste in FIG.

【図１６】従来例の半導体装置の製造装置の作用を説明
するための図であり、ダイパッド部が水平面に対して傾
いている場合のダイボンディング後を示す拡大断面図で
ある。FIG. 16 is a diagram for explaining the operation of the conventional semiconductor device manufacturing apparatus, and is an enlarged cross-sectional view showing a state after die bonding when the die pad portion is inclined with respect to the horizontal plane.

【図１７】従来例の半導体装置の製造装置の作用を説明
するための図であり、半導体チップが水平面に対して傾
いている場合のワイヤボンディング後を示す拡大断面図
である。FIG. 17 is a diagram for explaining the operation of the conventional semiconductor device manufacturing apparatus, which is an enlarged cross-sectional view showing a state after wire bonding when the semiconductor chip is tilted with respect to the horizontal plane.

【符号の説明】[Explanation of symbols]

２……リードフレーム、２ａ……ダイパッド部、２ｂ…
…インナリード部、５……半導体チップ、６……Ａｇペ
ースト、１１、１５……マウントプレート、１１ａ、１
５ａ……凹所、１２、１６……真空吸着用孔、１３……
真空バルブ、１４……真空ポンプ。2 ... Lead frame, 2a ... Die pad, 2b ...
… Inner lead part, 5 …… Semiconductor chip, 6 …… Ag paste, 11,15 …… Mount plate, 11a, 1
5a ... recess, 12, 16 ... vacuum suction hole, 13 ...
Vacuum valve, 14 ... Vacuum pump.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 マウントプレートに、リードフレームの
ダイパッド部に対応する凹所を形成し、該凹所に沿って
前記リードフレームを間欠的に送りながら、前記ダイパ
ッド部表面に半導体チップを接合する接合材料を塗布す
る工程、前記ダイパッド部表面に前記半導体チップを接
合する工程および前記半導体チップの接続電極と前記リ
ードフレームのリード部とをワイヤ接続する工程のう
ち、少なくとも１つの工程を施すようにした半導体装置
の製造装置において、前記凹所の底面に真空吸着用孔を
形成し、該真空吸着用孔に排気装置を接続し、前記何れ
かの工程を施す際、前記排気装置を駆動して前記真空吸
着用孔で前記ダイパッド部を真空固持するようにしたこ
とを特徴とする半導体装置の製造装置。1. A bonding method for forming a recess corresponding to a die pad portion of a lead frame on a mount plate, and bonding a semiconductor chip to the surface of the die pad portion while intermittently feeding the lead frame along the recess. At least one of the step of applying a material, the step of joining the semiconductor chip to the surface of the die pad portion, and the step of wire-connecting the connection electrode of the semiconductor chip and the lead portion of the lead frame is performed. In a semiconductor device manufacturing apparatus, a vacuum suction hole is formed in the bottom surface of the recess, an exhaust device is connected to the vacuum suction hole, and when performing any one of the steps, the exhaust device is driven to A semiconductor device manufacturing apparatus characterized in that the die pad portion is vacuum-held by a vacuum suction hole.
JP8073357A 1996-03-28 1996-03-28 Manufacture of semiconductor device Pending JPH09266219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8073357A JPH09266219A (en) 1996-03-28 1996-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8073357A JPH09266219A (en) 1996-03-28 1996-03-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH09266219A true JPH09266219A (en) 1997-10-07

Family

ID=13515847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8073357A Pending JPH09266219A (en) 1996-03-28 1996-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH09266219A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004077551A1 (en) * 2003-02-24 2004-09-10 Infineon Technologies Ag Improved method and apparatus for positioning integrated circuits on die pads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004077551A1 (en) * 2003-02-24 2004-09-10 Infineon Technologies Ag Improved method and apparatus for positioning integrated circuits on die pads

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