JPH10303355A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10303355A
JPH10303355A JP9124898A JP12489897A JPH10303355A JP H10303355 A JPH10303355 A JP H10303355A JP 9124898 A JP9124898 A JP 9124898A JP 12489897 A JP12489897 A JP 12489897A JP H10303355 A JPH10303355 A JP H10303355A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
element mounting
mounting portion
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9124898A
Other languages
Japanese (ja)
Inventor
Toshiya Matsubara
俊也 松原
Keiichi Tone
恵一 刀根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP9124898A priority Critical patent/JPH10303355A/en
Publication of JPH10303355A publication Critical patent/JPH10303355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To operate a semiconductor device stably without generating a failure such as cracks in a resin when packaging the resin in an element mounting part, by forming on the rear surface side of the element mounting part a first resin joint part consisting of a number of recessed parts having projections in the periphery. SOLUTION: A semiconductor device 10 is provided with a first resin joint part consisting of a plurality of recessed parts having projections in the periphery, on the rear surface side of an element mounting part 11 as a non-mounting surface 19. Then, in the resin packaging step for manufacture of the semiconductor device 10, a melted resin 17 is filled and cured around the element mounting part 11 on which a semiconductor circuit element 15 is placed and an inner lead 12, thereby forming a body. Further, the recessed parts 21 are formed as an area array on the non-mounting surface 19 of the element mounting part 11. Thus, the generation of cracks accompanied with curing shrinkage of the resin 17 and of failure due to lack of resistive factor against fluidity to the melted resin 17 can be prevented effectively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は集積回路素子が搭載
される素子搭載部と、該集積回路素子の周囲に配置され
る内部端子(インナーリード)とを樹脂封止して製造さ
れる半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufactured by resin sealing an element mounting portion on which an integrated circuit element is mounted and internal terminals (inner leads) arranged around the integrated circuit element. About.

【0002】[0002]

【従来の技術】樹脂封止されたパッケージからなる半導
体装置は機能付加、携帯性向上の要求から集積回路素子
の実装密度が高くなり、かつ小型化、薄型化の傾向にあ
る。これに伴って、樹脂が硬化収縮する際に、該樹脂と
素子搭載部との間に剪断力等を生じて、樹脂の部分に亀
裂を発生させたり、半導体装置の使用時の熱変動等によ
り樹脂を破損させたりする等の問題があった。このよう
な亀裂、損傷等を防止するための方法として、例えば特
公昭61−3100号公報には、半導体ペレット(集積
回路素子)を載置接着する面を平面とし、他方の面に複
数の窪みを形成したリードフレームのベッド(素子搭載
部)を有し、このリードフレームのベッドを複数の内部
端子(インナーリード)と共に、樹脂で一体的にモール
ドした半導体装置が記載されている。
2. Description of the Related Art A semiconductor device formed of a resin-sealed package tends to have a higher mounting density of integrated circuit elements and to be smaller and thinner due to a demand for additional functions and improved portability. Along with this, when the resin cures and contracts, a shearing force or the like is generated between the resin and the element mounting portion, thereby causing cracks in the resin portion or heat fluctuation during use of the semiconductor device. There were problems such as damaging the resin. As a method for preventing such cracks, damages, etc., for example, Japanese Patent Publication No. 61-3100 discloses a method in which a surface on which a semiconductor pellet (integrated circuit element) is placed and bonded is made flat, and a plurality of recesses are formed on the other surface. There is described a semiconductor device having a lead frame bed (element mounting portion) in which is formed a resin integrally with a plurality of internal terminals (inner leads).

【0003】[0003]

【発明が解決しようとする課題】しかしながら、前記特
公昭61−3100号公報に記載の半導体ペレットの非
搭載面に複数の窪みを設けてベッドとした半導体装置で
は以下の〜に示す問題点があった。 樹脂封止されるベッドと硬化収縮する樹脂との寸法差
が大きいために樹脂に過大な剪断力を生じて亀裂等を発
生し易い。そして、このような亀裂が一旦、生じると亀
裂内に湿分、不純物等が侵入してインナーリード、ある
いは素子搭載部等を腐食させ半導体装置の作動不良等を
引き起こすことがある。 硬化した樹脂とベッド間の、特に接合面に垂直な方向
の引張り力に対する抵抗力が小さいために、稼働中の温
度変動により樹脂とベッドの面とが剥離しやすく、ボン
ディングされた集積回路素子とインナーリードとの結線
部が損傷し、半導体装置の寿命低下等のトラブル要因と
なる。 前記窪みがエッチング処理によってリードフレームの
母材金属を溶解して形成されるか、単純なプレス加工に
よって形成されるので、凹凸の少ない滑らかな接合面が
形成され、樹脂とベッド面との接着強度が不足する。 前記窪みをエッチング処理により形成させる場合に
は、予備処理工程、洗浄工程等の化学処理工程が必要と
なり、生産コストが高くなる。 リードフレームに配置した樹脂型に溶融樹脂を充填し
て樹脂封止を行う際に、樹脂型内に形成される溶融樹脂
の流路に凹凸部分が少なく流動抵抗性に乏しいために、
樹脂型内に気泡が残存したり、樹脂の硬化が不均一とな
ったりして、樹脂内部に欠陥を生成し易い。本発明はこ
のような事情に鑑みてなされたもので、インナーリー
ド、素子搭載部の樹脂封止時に樹脂に亀裂等の欠陥を発
生させることなく、安定的に作動させることのできる半
導体装置を提供することを目的とする。
However, the semiconductor device described in the above-mentioned Japanese Patent Publication No. 61-3100, in which a plurality of depressions are provided on the non-mounting surface of the semiconductor pellet and formed as a bed, has the following problems. Was. Since the dimensional difference between the resin-sealed bed and the resin that cures and contracts is large, an excessive shear force is generated in the resin, and cracks and the like are easily generated. Once such cracks are formed, moisture, impurities, and the like may enter the cracks and corrode the inner leads or the element mounting portions and the like, causing malfunction of the semiconductor device. Since the resistance between the cured resin and the bed, especially the tensile force in the direction perpendicular to the joint surface, is small, the resin and the bed surface are liable to peel off due to temperature fluctuations during operation, and the bonded integrated circuit element The connection portion with the inner lead is damaged, which causes troubles such as shortening of the life of the semiconductor device. Since the recess is formed by dissolving the base metal of the lead frame by an etching process or formed by a simple press working, a smooth joint surface with less unevenness is formed, and the adhesive strength between the resin and the bed surface is formed. Run out. When the depression is formed by etching, a chemical treatment step such as a preliminary treatment step and a cleaning step is required, and the production cost is increased. When filling the molten resin into the resin mold placed in the lead frame and performing resin sealing, the flow path of the molten resin formed in the resin mold has few irregularities and poor flow resistance,
Bubbles remain in the resin mold, and the curing of the resin becomes uneven, so that defects are easily generated inside the resin. The present invention has been made in view of such circumstances, and provides a semiconductor device that can be operated stably without generating defects such as cracks in the resin when sealing the inner lead and the element mounting portion with the resin. The purpose is to do.

【0004】[0004]

【課題を解決するための手段】前記目的に沿う請求項1
記載の半導体装置は、素子搭載部の周囲に多数本のイン
ナーリードを備え、前記素子搭載部に搭載された集積回
路素子は、前記インナーリードの先部とワイヤボンディ
ングされた状態で、全体が樹脂封止される半導体装置に
おいて、前記素子搭載部の裏面側には、突起を周縁部に
有する多数の窪みからなる第1の樹脂係合部が設けられ
ている。請求項2記載の半導体装置は、請求項1記載の
半導体装置において、それぞれの前記突起は、前記窪み
内に突出したオーバーハング部を備えている。請求項3
記載の半導体装置は、請求項1又は2記載の半導体装置
において、前記窪みは、エリアアレイ状に配置されて、
しかも、超音波加工により形成されている。請求項4記
載の半導体装置は、請求項1〜3のいずれか1項に記載
の半導体装置において、前記インナーリードの中間部位
にも、突起を周縁部に有する窪みからなる第2の樹脂係
合部が設けられている。請求項5記載の半導体装置は、
請求項1〜4のいずれか1項に記載の半導体装置におい
て、前記素子搭載部は、前記インナーリードと別体に形
成されて、該インナーリードに接合されている。請求項
6記載の半導体装置は、請求項1〜4のいずれか1項に
記載の半導体装置において、前記素子搭載部は、前記イ
ンナーリードと一体に形成されている。エリアアレイ状
とは、複数の窪みを互いに間隔を有して略格子状に配列
した状態をいうが、窪みを各格子点に千鳥足状に配列す
る場合、あるいは不規則に配列する場合等も含まれる。
According to the present invention, there is provided a semiconductor device comprising:
The semiconductor device described above includes a number of inner leads around the element mounting portion, and the integrated circuit element mounted on the element mounting portion is entirely resin-bonded with the tip of the inner lead being wire-bonded. In the semiconductor device to be sealed, a first resin engaging portion is provided on the back surface side of the element mounting portion, the first resin engaging portion having a large number of depressions having a protrusion on a peripheral portion. According to a second aspect of the present invention, in the semiconductor device of the first aspect, each of the protrusions has an overhang portion projecting into the recess. Claim 3
The semiconductor device according to claim 1, wherein the depressions are arranged in an area array,
Moreover, it is formed by ultrasonic processing. A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein a second resin engagement is provided at an intermediate portion of the inner lead, the depression having a projection on a peripheral portion. Part is provided. The semiconductor device according to claim 5 is
5. The semiconductor device according to claim 1, wherein the element mounting portion is formed separately from the inner lead, and is joined to the inner lead. A semiconductor device according to a sixth aspect is the semiconductor device according to any one of the first to fourth aspects, wherein the element mounting portion is formed integrally with the inner lead. The area array shape refers to a state in which a plurality of depressions are arranged in a substantially lattice shape with an interval therebetween, but also includes a case where the depressions are arranged in a staggered manner at each lattice point, or a case where the depressions are irregularly arranged. It is.

【0005】[0005]

【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに図1(a)、(b)はそれぞ
れ本発明の第1の実施の形態に係る半導体装置の側断面
図及び要部拡大図、図2(a)、(b)、(c)はそれ
ぞれリードフレームの平面図、概略側面図、変形例の説
明図、図3(a)、(b)、(c)はそれぞれリードフ
レームの窪み形成方法の説明図、窪み整形方法の説明
図、窪みの種別を示す説明図、図4(a)、(b)は半
導体装置の製造方法を示す説明図、図5(a)、(b)
はそれぞれ本発明の第2の実施の形態に係る半導体装置
に適用するリードフレームの平面図及び概略側断面図で
ある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention. 1A and 1B are a side sectional view and an enlarged view of a main part of the semiconductor device according to the first embodiment of the present invention, and FIGS. 2A, 2B, and 2C are respectively. FIGS. 3A, 3B, and 3C are a plan view, a schematic side view, and an explanatory view of a modified example of the lead frame, respectively. FIGS. FIGS. 4A and 4B are explanatory views showing a method of manufacturing a semiconductor device, and FIGS. 5A and 5B.
3A and 3B are a plan view and a schematic side sectional view of a lead frame applied to a semiconductor device according to a second embodiment of the present invention.

【0006】以下、本発明の第1の実施の形態に係る半
導体装置について説明する。半導体装置10は図1に示
すように、素子搭載部11の素子搭載面18に搭載され
た集積回路素子15と、素子搭載部11の周囲に配置さ
れた多数本のインナーリード12と、集積回路素子15
とインナーリード12の先部を連結するボンディングワ
イヤ16と、これらを一体に封止する樹脂17と、前記
インナーリード12に一体的に続いて該樹脂17から引
き出されるアウターリード13とを有すると共に、前記
素子搭載部11の裏面側である非搭載面19には突起2
0を周縁部に有する多数の窪み21からなる第1の樹脂
係合部が設けられている。
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described. As shown in FIG. 1, a semiconductor device 10 includes an integrated circuit element 15 mounted on an element mounting surface 18 of an element mounting section 11, a plurality of inner leads 12 disposed around the element mounting section 11, and an integrated circuit. Element 15
And a bonding wire 16 for connecting the tip of the inner lead 12, a resin 17 for integrally sealing them, and an outer lead 13 integrally with the inner lead 12 and pulled out from the resin 17, The projection 2 is formed on the non-mounting surface 19 on the back side of the element mounting portion 11.
There is provided a first resin engaging portion composed of a number of depressions 21 having 0 in the peripheral portion.

【0007】半導体装置10の製造における樹脂封止工
程に際しては、集積回路素子15の載置された素子搭載
部11とインナーリード12との周囲に溶融した樹脂1
7を充填、硬化させて本体部を形成させる。そして、前
記窪み21をエリアアレイ状に素子搭載部11の非搭載
面19に形成させることによって、樹脂17の硬化収縮
に伴う亀裂の発生と、溶融した樹脂17に対する流動抵
抗性の不良等に基づく欠陥の発生とを効果的に防止でき
るようになっている。
In the resin sealing step in the manufacture of the semiconductor device 10, the molten resin 1 is formed around the element mounting portion 11 on which the integrated circuit element 15 is mounted and the inner lead 12.
7 is filled and cured to form a main body. By forming the depressions 21 in an area array on the non-mounting surface 19 of the element mounting portion 11, cracks due to curing shrinkage of the resin 17 and poor flow resistance to the molten resin 17 are caused. The generation of defects can be effectively prevented.

【0008】このような半導体装置の製造方法について
以下に説明する。前記素子搭載部11、インナーリード
12、アウターリード13を形成させるための素材とな
るリードフレーム14は以下のようにして製造する。ま
ず、銅、銅合金等の金属からなる帯状薄板材料にタンデ
ム加工方式等のプレス加工を行って図2(a)に示すよ
うなパターンの形成されたリードフレーム14を得る。
リードフレーム14には、帯状薄板の幅方向の両側に配
置された外枠部22、23と、外枠部22、23間にそ
れぞれ配置される素子搭載部11、インナーリード1
2、該インナーリード12に一体に形成されるアウター
リード13、素子搭載部11を外枠部22、23と結合
して支持するための吊りリード24及びアウターリード
13を外枠部22、23に結合させるためのタイバー2
5等が形成されている。そして、リードフレーム14に
形成される素子搭載面18の裏面(非搭載面)19に前
記窪み21の形成加工を行う。次に、集積回路素子15
を素子搭載部11に搭載して樹脂封止を行った後、外枠
部22、23、及び樹脂17の部分から引き出される各
アウターリード13間のタイバー25等を切り離して、
図1に示すような半導体装置10が製造されるようにな
っている。
A method for manufacturing such a semiconductor device will be described below. The lead frame 14, which is a material for forming the element mounting portion 11, the inner lead 12, and the outer lead 13, is manufactured as follows. First, a strip-shaped sheet material made of a metal such as copper or a copper alloy is subjected to press working such as tandem processing to obtain a lead frame 14 having a pattern as shown in FIG. 2A.
The lead frame 14 includes outer frame portions 22 and 23 disposed on both sides in the width direction of the strip-shaped thin plate, an element mounting portion 11 disposed between the outer frame portions 22 and 23, and the inner lead 1.
2. An outer lead 13 formed integrally with the inner lead 12, a suspension lead 24 for connecting and supporting the element mounting portion 11 with the outer frame portions 22 and 23, and the outer lead 13 on the outer frame portions 22 and 23. Tie bar 2 for joining
5 and the like are formed. Then, the recess 21 is formed on the back surface (non-mounting surface) 19 of the element mounting surface 18 formed on the lead frame 14. Next, the integrated circuit element 15
After mounting on the element mounting portion 11 and performing resin sealing, the outer frame portions 22 and 23 and the tie bar 25 and the like between the outer leads 13 pulled out from the portion of the resin 17 are separated.
A semiconductor device 10 as shown in FIG. 1 is manufactured.

【0009】素子搭載部11の素子搭載面18にはエポ
キシ樹脂等の接着剤等を介して集積回路素子15が載置
されるようになっており、素子搭載面18の裏面である
非搭載面19には周縁部に突起20を有する多数の窪み
21がエリアアレイ状に配置されて、第1の樹脂係合部
が形成されるようになっている。なお、図2(c)は窪
み21の形成された素子搭載部11aを別体に成形した
後、超音波溶接等の手段により吊りリード24aを介し
てリードフレーム14aの本体に結合した場合の変形例
を示しており、図2(b)のように予めリードフレーム
14の本体に一体に成形された素子搭載部11の場合と
同様に、以下に示す窪み21の形成方法を適用すること
もできる。
The integrated circuit element 15 is mounted on the element mounting surface 18 of the element mounting portion 11 via an adhesive such as epoxy resin or the like. 19, a large number of depressions 21 having projections 20 on the peripheral edge are arranged in an area array so that a first resin engaging portion is formed. FIG. 2 (c) shows the deformation when the element mounting portion 11a having the depression 21 formed thereon is separately formed and then connected to the main body of the lead frame 14a via the suspension lead 24a by means of ultrasonic welding or the like. An example is shown, and the following method of forming the recess 21 can be applied in the same manner as in the case of the element mounting portion 11 integrally formed in advance with the main body of the lead frame 14 as shown in FIG. .

【0010】以下、このような窪み21の形成方法につ
いて詳述する。まず、図3(a)に示すように素子搭載
面18を下にして、加工用基板29上に素子搭載部11
を載置し、該素子搭載面18の裏面(非搭載面)19に
超音波振動させる穿孔加工具26の先端を押圧する。穿
孔加工具26の側部には穿孔加工具26を超音波振動さ
せるためのトランスジューサ27が穿孔加工具26の押
圧方向に対して略直角な方向の振動力を伝えるように配
置されていて、高周波発振器28を介して高周波電圧を
トランスジューサ27に付加することにより必要な振動
数と、振動強度(振幅)とで穿孔加工具26を横振動さ
せることができるようになっている。なお、必要に応じ
て穿孔加工具23と穿孔加工面となる非搭載面19との
間に研削用の砥粒を介在させることもでき、この場合に
はより効率的に研削を行うことができる。本実施の形態
においては、穿孔加工具26の先端を非搭載面19に所
定の圧力で押圧すると共に、穿孔加工具26を超音波振
動させて、リードフレーム14の厚みL(0.15〜
0.2mm)に対して約1/5〜2/3の深さDで、一
辺の長さが1〜2mmの四角形状となる窪み21をエリ
アアレイ状に形成させる。これによって、図3(a)に
示すように穿孔加工具26の外周部、即ち窪み21の周
縁部が、横方向の超音波振動によって切削された金属の
切り粉が堆積、融合し、あるいは金属の塑性変形によっ
て盛り上がって、元の非搭載面19より高さHとなるよ
うに突出した突起20を効果的に形成させることができ
る。
Hereinafter, a method of forming such a depression 21 will be described in detail. First, as shown in FIG. 3A, the element mounting portion 11 is placed on the processing substrate 29 with the element mounting surface 18 facing down.
Is placed, and the back end (non-mounting surface) 19 of the element mounting surface 18 is pressed against the tip end of a piercing tool 26 to be ultrasonically vibrated. A transducer 27 for ultrasonically oscillating the piercing tool 26 is disposed on a side portion of the piercing tool 26 so as to transmit a vibration force in a direction substantially perpendicular to the pressing direction of the piercing tool 26. By applying a high frequency voltage to the transducer 27 via the oscillator 28, the drilling tool 26 can be laterally vibrated at a required frequency and vibration intensity (amplitude). Note that, if necessary, abrasive grains for grinding can be interposed between the drilling tool 23 and the non-mounting surface 19 that is the drilling surface, and in this case, grinding can be performed more efficiently. . In the present embodiment, the tip of the drilling tool 26 is pressed against the non-mounting surface 19 with a predetermined pressure, and the punching tool 26 is ultrasonically vibrated, so that the thickness L of the lead frame 14 (0.15 to 0.15).
0.2 mm), a square-shaped depression 21 having a depth D of about 1/5 to 2/3 and a side length of 1 to 2 mm is formed in an area array. As a result, as shown in FIG. 3A, the outer peripheral portion of the piercing tool 26, that is, the peripheral edge of the recess 21 is deposited with metal chips cut by the ultrasonic vibration in the lateral direction, and the metal chips are deposited or fused. And the protrusions 20 protruding to have a height H from the original non-mounting surface 19 can be effectively formed.

【0011】次に、図3(b)に示すように、この突起
20の形成された素子搭載部11を加工用基板29に載
置した状態で、必要に応じてプレス加工機の押圧型30
を用いて上方から押圧して、突起20を塑性変形させ必
要な形状に整える。図3(c)はこのようにして整形さ
れる突起20及び窪み21の形状パターン、、を
示すものであり、プレス加工機の押圧面の形状、押圧方
法等によって、適宜必要な形状パターンに調整すること
が可能である。形状パターンは、プレス加工機で押圧
しないで突起20とした例を示しており、窪み21の成
形にかかる工程を少なくできる利点がある。形状パター
ンは、突起20の上部を平らに塑性変形させて成形し
た例であり、樹脂封止の際の樹脂の寸法を適正に管理で
きる利点がある。形状パターンは、突起20の一部を
窪み21の側に押圧してオーバーハング部31を形成さ
せて、樹脂封止される際の樹脂と非搭載面19との機械
的締結による結合力を付与できる。なお、図3において
は、窪み21を一つずつ形成させる場合について示して
いるが、複数あるいは全部の窪みを複数の穿孔加工具2
6を有する超音波加工機と複数の突起を同時に押圧する
プレス加工機を用いて処理してもよい。また、前記穿孔
加工具26の先端の押圧面における形状は、四角形以外
の形状とすることも可能であり、三角形、五角形、六角
形、七角形、八角形、及び円形等の形状の中から適宜選
択できる。
Next, as shown in FIG. 3 (b), in a state where the element mounting portion 11 on which the projections 20 are formed is mounted on a processing substrate 29, if necessary, a pressing die 30 of a press machine is used.
The protrusion 20 is plastically deformed to adjust it to a required shape by pressing from above. FIG. 3 (c) shows the shape pattern of the projections 20 and the depressions 21 shaped in this way, and is adjusted to the necessary shape pattern as appropriate according to the shape of the pressing surface of the press machine, the pressing method, and the like. It is possible to The shape pattern shows an example in which the projection 20 is formed without being pressed by a press machine, and there is an advantage that the number of steps for forming the depression 21 can be reduced. The shape pattern is an example in which the upper portion of the protrusion 20 is formed by plastically deforming the protrusion flatly, and has an advantage that the dimensions of the resin at the time of resin sealing can be appropriately controlled. The shape pattern presses a part of the projection 20 toward the recess 21 to form the overhang portion 31 and imparts a coupling force by mechanical fastening between the resin and the non-mounting surface 19 when the resin is sealed. it can. Although FIG. 3 shows a case where the depressions 21 are formed one by one, a plurality or all of the depressions may be formed by a plurality of drilling tools 2.
Alternatively, the processing may be performed using an ultrasonic processing machine having 6 and a press processing machine that simultaneously presses a plurality of protrusions. Further, the shape of the tip of the drilling tool 26 on the pressing surface may be a shape other than a square, and may be appropriately selected from shapes such as a triangle, a pentagon, a hexagon, a heptagon, an octagon, and a circle. You can choose.

【0012】続いて、図4を参照しながら前記リードフ
レーム14を用いて半導体装置10を製造する手順につ
いて説明する。まず、図4(a)に示すように集積回路
素子15をリードフレーム14の素子搭載部11に固定
した後、集積回路素子15とインナーリード12とをボ
ンディングワイヤ16で結線する。次に、図4(b)に
示すように樹脂型32をリードフレーム14の上下面か
ら挟み込むように配置し、樹脂型32に設けられた樹脂
供給孔33を介して溶融した樹脂17を樹脂型32内に
供給する。この時、高流動性の溶融した樹脂17が素子
搭載面18の裏面側に形成された窪み21上を流動する
が、窪み21の周縁部には突起20を有しているので、
この部分での樹脂17の流動抵抗が大きくなる。このた
め、溶融した樹脂17が均一に分散されると共に、樹脂
17の供給速度が抑制され、気泡等の巻き込みを少なく
することが可能であり、過剰の樹脂17が気泡と共に、
樹脂供給孔33の反対位置等に設けられた排出孔34か
ら排出される。この溶融した樹脂17が硬化する際に、
樹脂17の収縮が起こるが、窪み21の周縁部に形成さ
れた突起20によって、硬化した樹脂17が確実に保持
されるために、樹脂17の収縮に伴う亀裂あるいは樹脂
17と非搭載面19との剥離を抑制することができる。
こうして、図1に示すように、内部欠陥の少ない樹脂1
7を有した半導体装置10を得ることができ、その耐久
性が保持されると共に、突起20によって樹脂17と非
搭載面19間の機械的接合度合いを高めることができる
ので、稼働時における温度変動等に対しても抵抗性の高
い半導体装置10を得ることができる。
Next, a procedure for manufacturing the semiconductor device 10 using the lead frame 14 will be described with reference to FIG. First, as shown in FIG. 4A, after the integrated circuit element 15 is fixed to the element mounting portion 11 of the lead frame 14, the integrated circuit element 15 and the inner leads 12 are connected by bonding wires 16. Next, as shown in FIG. 4B, the resin mold 32 is disposed so as to be sandwiched from the upper and lower surfaces of the lead frame 14, and the resin 17 melted through the resin supply holes 33 provided in the resin mold 32 is removed. 32. At this time, the molten resin 17 having high fluidity flows on the depression 21 formed on the back surface side of the element mounting surface 18, but since the depression 21 has the protrusion 20 on the peripheral edge thereof,
The flow resistance of the resin 17 at this portion increases. For this reason, while the molten resin 17 is uniformly dispersed, the supply speed of the resin 17 is suppressed, and it is possible to reduce the entrapment of air bubbles and the like.
The resin is discharged from a discharge hole 34 provided at a position opposite to the resin supply hole 33. When the molten resin 17 is cured,
Although the resin 17 shrinks, the cured resin 17 is securely held by the projections 20 formed on the peripheral edge of the depression 21. Can be suppressed.
Thus, as shown in FIG.
7 can be obtained, the durability of the semiconductor device 10 can be maintained, and the degree of mechanical joining between the resin 17 and the non-mounting surface 19 can be increased by the projections 20. Thus, the semiconductor device 10 having high resistance to such factors can be obtained.

【0013】続いて、本発明の第2の実施の形態に係る
半導体装置について説明する。なお、前記第1の実施の
形態で説明した半導体装置10と同様の機能を有する部
分については同一の符号を付してその詳しい説明を省略
する。半導体装置に使用するリードフレーム40は、図
5に示すように帯状薄板材料の幅方向の両端部に配置さ
れた外枠部41、42と、該外枠部41、42間に吊り
リード47によって支持される素子搭載部43と、該素
子搭載部43の集積回路素子15にボンディングワイヤ
16で結線されるインナーリード44と、該インナーリ
ード44に続くアウターリード45とが形成されてい
る。そして、素子搭載部43の非搭載面19には非搭載
面19より突出する突起20を周縁部に有した窪み21
が複数配置されて第1の樹脂係合部が形成されており、
かつ、インナーリード44の中間部位である斜線で示す
ディンプル形成領域46にも突起20を周縁部に有した
窪み21からなる第2の樹脂係合部が形成されている。
なお、図5においては、窪み21をインナーリード44
の非搭載面19の側に形成させている場合について示し
ているが、窪み21を素子搭載面18の側にも形成させ
て、硬化する樹脂17とインナーリード12との接着性
をさらに強固にすることも可能である。
Next, a semiconductor device according to a second embodiment of the present invention will be described. Parts having the same functions as those of the semiconductor device 10 described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 5, a lead frame 40 used for a semiconductor device is provided with outer frames 41 and 42 arranged at both ends in the width direction of a strip-shaped sheet material, and hanging leads 47 between the outer frames 41 and 42. An element mounting portion 43 to be supported, an inner lead 44 connected to the integrated circuit element 15 of the element mounting portion 43 by a bonding wire 16, and an outer lead 45 following the inner lead 44 are formed. A recess 21 having a projection 20 protruding from the non-mounting surface 19 on the non-mounting surface 19 of the element mounting portion 43 in the peripheral edge portion.
Are arranged to form a first resin engaging portion,
In addition, a second resin engaging portion composed of a depression 21 having a projection 20 on the periphery is also formed in a dimple forming region 46 indicated by oblique lines, which is an intermediate portion of the inner lead 44.
In addition, in FIG.
Is shown on the side of the non-mounting surface 19, but the depression 21 is also formed on the side of the element mounting surface 18 to further strengthen the adhesiveness between the hardening resin 17 and the inner lead 12. It is also possible.

【0014】このようなエリアアレイ状に配置された窪
み21からなる第1、及び第2の樹脂係合部を形成させ
ることによって、集積回路素子15の載置された素子搭
載部11とインナーリード12との周囲に溶融した樹脂
17を充填させて半導体装置を形成させる際における、
樹脂の硬化収縮に伴う亀裂の発生と、溶融した樹脂に対
する流動抵抗性の不良に基づく欠陥の発生とを効果的に
防止するようになっている。なお、窪み21の形成方法
は、第1の実施の形態に示した超音波加工を用いる方法
と略同様であるので、以下では前記図3を再度引用し、
前記超音波加工法を具現化する操作内容について説明す
る。
By forming the first and second resin engaging portions including the recesses 21 arranged in the area array, the element mounting portion 11 on which the integrated circuit element 15 is mounted and the inner lead are formed. When the semiconductor device is formed by filling the molten resin 17 around the substrate 12 and
Cracks due to curing shrinkage of the resin and defects due to poor flow resistance to the molten resin are effectively prevented. Since the method of forming the depression 21 is substantially the same as the method using the ultrasonic processing shown in the first embodiment, FIG.
An operation content for realizing the ultrasonic processing method will be described.

【0015】第2の実施の形態においては、図3(a)
に示すような穿孔加工具26に付与する超音波振動の振
動数、振幅等を押圧する深さD毎に制御することによ
り、窪み21の内面における表面粗さ、及び窪み21の
内面の傾斜角度θ等を調整することが可能である。例え
ば、深さDが浅い時には、高周波発振器28により振動
数及び振幅を大きくし、深さDの増加に伴って振動数等
を小さくしていくことにより、窪み21の内面に所定の
傾斜角度θを付与すると共に、切削の際に生じる切り
粉、塑性変形物等で形成される突起20の高さHを調整
できる。また、穿孔加工具26の先端を窪み21から引
き上げる際に振動数、振幅を穿孔加工具26の押圧時よ
り大きく設定することにより、窪み21の内面の表面粗
さを大きくすることもできる。これによって、素子搭載
部43の非搭載面19、及びインナーリード44の部分
が樹脂封止される際の流動抵抗性、及び樹脂封止後の樹
脂17とインナーリード44の面間の接着性、剥離抵抗
性等を制御して、半導体装置に発生する作動不良等のト
ラブルを未然に防ぐことができる。
In the second embodiment, FIG.
By controlling the frequency, amplitude, etc. of the ultrasonic vibration applied to the drilling tool 26 for each depth D to be pressed, the surface roughness on the inner surface of the depression 21 and the inclination angle of the inner surface of the depression 21 It is possible to adjust θ and the like. For example, when the depth D is shallow, the frequency and amplitude are increased by the high-frequency oscillator 28, and the frequency and the like are decreased as the depth D increases. And the height H of the projections 20 formed by cuttings, plastic deformations, and the like generated during cutting can be adjusted. In addition, by setting the vibration frequency and amplitude at the time of lifting the tip of the piercing tool 26 from the recess 21 to be larger than those at the time of pressing the piercing tool 26, it is possible to increase the surface roughness of the inner surface of the recess 21. Thereby, the flow resistance when the non-mounting surface 19 of the element mounting portion 43 and the portion of the inner lead 44 are sealed with resin, and the adhesiveness between the surface of the resin 17 and the inner lead 44 after resin sealing, By controlling the peeling resistance and the like, troubles such as malfunctions occurring in the semiconductor device can be prevented.

【0016】以上、本発明の実施の形態を説明したが、
本発明はこれらの実施の形態に限定されるものではな
く、要旨を逸脱しない条件の変更等は全て本発明の適用
範囲である。例えば、本実施の形態においては、窪みを
素子搭載部の非搭載面側にのみ形成させる場合について
示したが、必要に応じて素子搭載面側にも配置させるこ
とができる。また、超音波振動させる穿孔加工具の先端
形状及び寸法等を適宜変更して、リードフレームと樹脂
の間の密着性をさらに適正に維持させることができる。
The embodiments of the present invention have been described above.
The present invention is not limited to these embodiments, and all changes in conditions without departing from the gist are within the scope of the present invention. For example, in the present embodiment, the case where the depression is formed only on the non-mounting surface side of the element mounting portion has been described. However, the depression can be arranged on the element mounting surface side as needed. In addition, by appropriately changing the shape, size, and the like of the drilling tool to be ultrasonically vibrated, the adhesion between the lead frame and the resin can be maintained more appropriately.

【0017】[0017]

【発明の効果】請求項1〜6記載の半導体装置において
は、素子搭載部の周囲に多数本のインナーリードを備
え、素子搭載部に搭載された集積回路素子は、インナー
リードの先部とワイヤボンディングされた状態で、全体
が樹脂封止される半導体装置において、素子搭載部の裏
面側には、突起を周縁部に有する多数の窪みからなる第
1の樹脂係合部が設けられているので、樹脂封止される
際の樹脂の硬化収縮に伴う亀裂の発生を防止することが
できる。また、樹脂の充填時における流動抵抗性が付与
されるので、樹脂内部に発生する欠陥を抑制し、半導体
装置の使用時の作動不良等のトラブルを防止できる。特
に、請求項2記載の半導体装置においては、それぞれの
突起は、窪み内に突出したオーバーハング部を備えてい
るので、樹脂と素子搭載部、及びインナーリード間の機
械的結合度が増大して、樹脂封止時の樹脂の硬化収縮、
及び使用時の温度変動に伴う亀裂の発生をさらに効果的
に防止できる。
According to the semiconductor device of the present invention, a plurality of inner leads are provided around the element mounting portion, and the integrated circuit element mounted on the element mounting portion is connected to the tip of the inner lead by a wire. In a semiconductor device which is entirely resin-sealed in a bonded state, the first resin engaging portion composed of a number of depressions having projections on the periphery is provided on the back surface side of the element mounting portion. Further, it is possible to prevent the occurrence of cracks due to the curing shrinkage of the resin when the resin is sealed. In addition, since flow resistance at the time of filling the resin is provided, defects generated inside the resin can be suppressed, and troubles such as malfunction of the semiconductor device during use can be prevented. In particular, in the semiconductor device according to the second aspect, since each of the protrusions has an overhang portion projecting into the recess, the degree of mechanical coupling between the resin, the element mounting portion, and the inner lead increases. , Curing shrinkage of resin during resin sealing,
Further, generation of cracks due to temperature fluctuation during use can be more effectively prevented.

【0018】請求項3記載の半導体装置においては、窪
みは、エリアアレイ状に配置されて、しかも、超音波加
工により形成されているので、簡単な操作で周縁部に突
起を有する窪みを効率的に形成させることができる。こ
れによって、欠陥の少ない樹脂封止された半導体装置を
製造でき、その信頼性を高めることができる。請求項4
記載の半導体装置においては、インナーリードの中間部
位にも、突起を周縁部に有する窪みからなる第2の樹脂
係合部が設けられているので、樹脂封止されるインナー
リードと樹脂との接着をより強固にすると共に、半導体
装置としての信頼性をさらに向上できる。請求項5記載
の半導体装置においては、素子搭載部は、インナーリー
ドと別体に形成されて、インナーリードに接合されるの
で、樹脂係合部を形成させるための窪みをより精密に、
かつ、効率良く形成させることができる。請求項6記載
の半導体装置においては、素子搭載部は、インナーリー
ドと一体に形成されているので、金型を用いたプレス成
形により素子搭載部とインナーリード間の位置決めを正
確に行うことができる。
In the semiconductor device according to the third aspect, since the depressions are arranged in an area array and formed by ultrasonic processing, the depressions having projections on the peripheral edge can be efficiently formed by a simple operation. Can be formed. As a result, a resin-sealed semiconductor device with few defects can be manufactured, and its reliability can be improved. Claim 4
In the semiconductor device described above, since the second resin engaging portion composed of a recess having a protrusion on the peripheral portion is also provided in the middle portion of the inner lead, the bonding between the resin and the inner lead to be resin-sealed is performed. And the reliability as a semiconductor device can be further improved. In the semiconductor device according to the fifth aspect, the element mounting portion is formed separately from the inner lead and is joined to the inner lead, so that the recess for forming the resin engaging portion is more precisely formed.
And it can be formed efficiently. In the semiconductor device according to the sixth aspect, since the element mounting portion is formed integrally with the inner lead, positioning between the element mounting portion and the inner lead can be accurately performed by press molding using a mold. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)、(b)はそれぞれ本発明の第1の実施
の形態に係る半導体装置の側断面図及び要部拡大図であ
る。
FIGS. 1A and 1B are a side sectional view and a main part enlarged view of a semiconductor device according to a first embodiment of the present invention, respectively.

【図2】(a)、(b)、(c)はそれぞれリードフレ
ームの平面図、概略側断面図、変形例の説明図である。
FIGS. 2A, 2B, and 2C are a plan view, a schematic side sectional view, and an explanatory view of a modified example of a lead frame, respectively.

【図3】(a)、(b)、(c)はそれぞれリードフレ
ームの窪み形成方法の説明図、窪み整形方法の説明図、
窪みの種別を示す説明図である。
FIGS. 3A, 3B, and 3C are explanatory diagrams of a method of forming a depression in a lead frame, and explanatory diagrams of a method of forming a depression, respectively;
It is explanatory drawing which shows the kind of depression.

【図4】(a)、(b)は半導体装置の製造方法を示す
説明図である。
FIGS. 4A and 4B are explanatory diagrams illustrating a method for manufacturing a semiconductor device.

【図5】(a)、(b)はそれぞれ本発明の第2の実施
の形態に係る半導体装置に適用するリードフレームの平
面図及び概略側断面図である。
FIGS. 5A and 5B are a plan view and a schematic side sectional view, respectively, of a lead frame applied to a semiconductor device according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 半導体装置 11 素子搭載
部 11a 素子搭載部 12 インナー
リード 13 アウターリード 14 リードフ
レーム 14a リードフレーム 15 集積回路
素子 16 ボンディングワイヤ 17 樹脂 18 素子搭載面 19 非搭載面
(裏面) 20 突起 21 窪み 22 外枠部 23 外枠部 24 吊りリード 24a 吊りリ
ード 25 タイバー 26 穿孔加工
具 27 トランスジューサ 28 高周波発
振器 29 加工用基板 30 押圧型 31 オーバーハング部 32 樹脂型 33 樹脂供給孔 34 排出孔 40 リードフレーム 41 外枠部 42 外枠部 43 素子搭載
部 44 インナーリード 45 アウター
リード 46 ディンプル形成領域 47 吊りリー
DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Element mounting part 11a Element mounting part 12 Inner lead 13 Outer lead 14 Lead frame 14a Lead frame 15 Integrated circuit element 16 Bonding wire 17 Resin 18 Element mounting surface 19 Non-mounting surface (back surface) 20 Projection 21 Depression 22 Outer frame Part 23 Outer frame part 24 Suspended lead 24a Suspended lead 25 Tie bar 26 Drilling tool 27 Transducer 28 High frequency oscillator 29 Processing board 30 Pressing type 31 Overhang part 32 Resin type 33 Resin supply hole 34 Discharge hole 40 Lead frame 41 Outer frame part 42 Outer frame part 43 Element mounting part 44 Inner lead 45 Outer lead 46 Dimple formation area 47 Suspension lead

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 素子搭載部の周囲に多数本のインナーリ
ードを備え、前記素子搭載部に搭載された集積回路素子
は、前記インナーリードの先部とワイヤボンディングさ
れた状態で、全体が樹脂封止される半導体装置におい
て、 前記素子搭載部の裏面側には、突起を周縁部に有する多
数の窪みからなる第1の樹脂係合部が設けられているこ
とを特徴とする半導体装置。
An integrated circuit device mounted on the element mounting portion is provided with a plurality of inner leads around the element mounting portion, and the whole of the integrated circuit element is wire-bonded to a tip portion of the inner lead. In the semiconductor device to be stopped, a first resin engaging portion including a large number of depressions having a protrusion on a peripheral portion is provided on a back surface side of the element mounting portion.
【請求項2】 それぞれの前記突起は、前記窪み内に突
出したオーバーハング部を備えていることを特徴とする
請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein each of said projections has an overhang portion projecting into said recess.
【請求項3】 前記窪みは、エリアアレイ状に配置され
て、しかも、超音波加工により形成されていることを特
徴とする請求項1又は2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the depressions are arranged in an area array and formed by ultrasonic processing.
【請求項4】 前記インナーリードの中間部位にも、突
起を周縁部に有する窪みからなる第2の樹脂係合部が設
けられていることを特徴とする請求項1〜3のいずれか
1項に記載の半導体装置。
4. The method according to claim 1, wherein a second resin engaging portion formed of a recess having a protrusion on a peripheral portion is provided also at an intermediate portion of the inner lead. 3. The semiconductor device according to claim 1.
【請求項5】 前記素子搭載部は、前記インナーリード
と別体に形成されて、該インナーリードに接合されてい
ることを特徴とする請求項1〜4のいずれか1項に記載
の半導体装置。
5. The semiconductor device according to claim 1, wherein said element mounting portion is formed separately from said inner lead and is joined to said inner lead. .
【請求項6】 前記素子搭載部は、前記インナーリード
と一体に形成されていることを特徴とする請求項1〜4
のいずれか1項に記載の半導体装置。
6. The device according to claim 1, wherein the element mounting portion is formed integrally with the inner lead.
The semiconductor device according to claim 1.
JP9124898A 1997-04-28 1997-04-28 Semiconductor device Pending JPH10303355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9124898A JPH10303355A (en) 1997-04-28 1997-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9124898A JPH10303355A (en) 1997-04-28 1997-04-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10303355A true JPH10303355A (en) 1998-11-13

Family

ID=14896844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9124898A Pending JPH10303355A (en) 1997-04-28 1997-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10303355A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583364B1 (en) 1999-08-26 2003-06-24 Sony Chemicals Corp. Ultrasonic manufacturing apparatuses, multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards
EP1202347A3 (en) * 2000-10-31 2004-03-31 W.C. Heraeus GmbH & Co. KG Method of manufacturing a metal frame, metal frame and using the same
JP2015072991A (en) * 2013-10-02 2015-04-16 株式会社三井ハイテック Lead frame and manufacturing method thereof, and semiconductor device using the same
WO2017077966A1 (en) * 2015-11-05 2017-05-11 株式会社神戸製鋼所 Manufacturing method for microporous plate
US11367666B2 (en) 2017-09-29 2022-06-21 Jmj Korea Co., Ltd. Clip, lead frame, and substrate used in semiconductor package having engraved pattern formed thereon and the semiconductor package comprising the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583364B1 (en) 1999-08-26 2003-06-24 Sony Chemicals Corp. Ultrasonic manufacturing apparatuses, multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards
US6926187B2 (en) 1999-08-26 2005-08-09 Sony Chemicals Corp. Ultrasonic manufacturing apparatus
US6991148B2 (en) 1999-08-26 2006-01-31 Sony Corporation Process for manufacturing multilayer flexible wiring boards
EP1202347A3 (en) * 2000-10-31 2004-03-31 W.C. Heraeus GmbH & Co. KG Method of manufacturing a metal frame, metal frame and using the same
JP2015072991A (en) * 2013-10-02 2015-04-16 株式会社三井ハイテック Lead frame and manufacturing method thereof, and semiconductor device using the same
WO2017077966A1 (en) * 2015-11-05 2017-05-11 株式会社神戸製鋼所 Manufacturing method for microporous plate
JP2017090556A (en) * 2015-11-05 2017-05-25 株式会社神戸製鋼所 Method for manufacturing finely perforated plate
US11367666B2 (en) 2017-09-29 2022-06-21 Jmj Korea Co., Ltd. Clip, lead frame, and substrate used in semiconductor package having engraved pattern formed thereon and the semiconductor package comprising the same

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