JPH09244902A - Download circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To externally download a program contents without turning off a power supply nor exchanging a program ROM even when a program change occurs in an operation mode, etc., by providing a specific memory, a specific processor and a specific program supply means and a specific control means respectively. SOLUTION: This circuit is provided with a processor 11 which is connected to a program reloadable memory via a bus and processes the program stored in the memory, a host CPU 14 which serves as a supply means to externally supply a program, and a control means 20. The means 20 is composed of a control circuit 15, a bidirectional buffer 16 and buffers 17 and 18. Then the means 20 connects the output line of the CPU 14 to the memory bus in a program rewrite mode to download the program of the CPU 14 to the processor 11 and then to transfer the downloaded program to the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a download circuit for downloading a program to a processor.

[0002]

2. Description of the Related Art A single-chip microcomputer is mainly a microprocessor in which ROM and RAM for storing programs and data and various peripheral control functions are integrated as a single chip by an internal bus. Various specifications can be arbitrarily changed by changing the program written in the ROM.

Recently, in order to avoid the time loss of changing the mask ROM for each debugging of system development, the program ROM is replaced with a non-volatile memory such as EPROM (eras).
ableprogrammable ROM), EEPROM (electrically
erasable programmable ROM) and program development
We are working to significantly reduce the time required for modification.

FIG. 7 shows an example of the configuration of a single processor, and the processor 1 performs processing according to the program in the EPROM 2. Further, as shown in FIG. 8, a plurality of processors (# 0, #N) 3 and 4 and processors # 0 and # are provided on one board.
EPROM (# 0, #N) that supplies programs to N
There is a device equipped with 5, and 6. As shown in FIG. 8, as a processor using a plurality of processors # 0 and #N, there is, for example, a processor for communication, and the processors 3 and 4 have individual EPROMs 5 and 6, respectively. The processors 3 and 4 perform their respective processes according to the programs in the individual EPROMs 5 and 6.

When a program is changed, the program ROM is replaced or the program is rewritten.

[0006]

However, in such a conventional apparatus, the program ROM is provided for each processor, so that the program ROM is increased each time the number of processors is increased, and the cost is increased. was there.

Further, for the same reason, if the program is changed during operation, the program ROM must be replaced and the power must be turned off.

The present invention provides a download circuit capable of externally downloading the change of the program content without powering off or replacing the program ROM even if the program is changed during operation. To aim.

Further, the present invention eliminates the need to prepare a separate program ROM for each processor in an apparatus in which multiple processors are connected, and enables downloading of each program from a common program ROM. It is an object of the present invention to provide a download circuit that enables download to each processor by externally downloading changes in program content.

[0010]

A download circuit according to the present invention includes a memory in which a program can be rewritten, a processor which is connected to the memory via a bus, and which processes the program stored in the memory, and an external processor. A supply means for supplying the program and an output line of the supply means are connected to the bus of the memory at the time of rewriting the program, the program of the supply means is downloaded to the processor, and after the download is completed, the downloaded program is transferred to the memory. And a control means for controlling so as to do so.

Further, in the download circuit, a plurality of processors are connected to the memory, and the control means connects the output line of the supply means to the bus of the memory to rewrite the program of the supply means when the program is rewritten. The program is downloaded to the processor, and after the download is completed, the program downloaded to the first processor is transferred to the memory, and the program transferred to the memory is controlled to be downloaded to another processor.

Further, the download circuit is provided with a monitoring means for monitoring the download state, a plurality of processors are connected to the memory, and the control means connects the output line of the supply means to the bus of the memory when rewriting the program. Download the program of the supply means to the first processor, transfer the program downloaded to the first processor to the memory after the download is completed, and further transfer the program transferred to the memory to other processors all at once. The download control is performed, and the monitoring unit is configured to monitor that all the processors are normally downloading at the time of download.

Further, the supply means may be a microcomputer connected to the control means.

[0014]

The download circuit according to the present invention can be applied to a download circuit such as a communication processor.

FIG. 1 is a block diagram of a download circuit according to the first embodiment of the present invention. The download circuit shown in FIG. 1 is an example applied to a download circuit when the processor is single.

In FIG. 1, 11 is a processor, 12 is an EPROM, 13 is an EEPROM, and 14 is an upper CPU.
(Supply means), 15 is a control circuit, 16 is a bidirectional buffer, 17 and 18 are buffers, and 19 is a RAM.

The control circuit 15, the bidirectional buffer 16 and the buffers 17 and 18 constitute a control means 20 for switching the bus as a whole and controlling so as to download the change of the program content from the outside to the processor.

The processor 11 performs processing in accordance with a program stored in the EPROM 12 or the EEPROM 13, and has a data input terminal D, a system reset input terminal RST, a download signal (hereinafter referred to as DONE signal) output terminal DONE, and a write enable ( W
E: Write Enable) signal output terminal WE, output enable
(OE: Output Enable) A signal output terminal OE is provided.

The data input terminal D has an EPROM 12,
A program or data is input from the EEPROM 13 or the upper CPU 14, and a DONE signal is output from the output terminal DONE when the download is completed.
6 is output. Further, the write enable signal output terminal WE and the output enable signal output terminal OE output the WE signal and the OE signal for controlling the writing / reading of data to the RAM 19 or the EEPROM 13. Further, when a reset signal is input to the system reset input terminal RST in positive logic, the system is reset and the processor 11 starts downloading.

The EPROM 12 is a rewritable ROM that stores programs and data used by the processor 11, and a boot program and an operation application program are written in advance. If there is no program change, EPROM12
The application program for operation and the data stored in are always output to the processor 11, and the processor 11 executes the program of the EPROM 12.

The EEPROM 13 is an electrically rewritable ROM that supplies the program and data to the processor 11 in place of the EPROM 12 after the program is changed.
It is. Specifically, the contents of the EPROM 12 and the download program from the upper CPU 14 are stored in the processor 11 and the RAM according to the processing shown in FIG.
Written from 19. Therefore, after the program is changed, the program and data stored in the EEPROM 13 are output to the processor 11, and the processor 11 executes the program in the EEPROM 13.

The upper CPU 14 is a device for controlling the entire download circuit, outputs a program content change request to the control circuit 15 when the program content is changed, controls the control circuit 15, and downloads the download program to the processor 11.

The control circuit 15 has a bidirectional buffer 16 in accordance with a program content change request from the host CPU 14.
And the buffers 17 and 18 are controlled. That is, the control circuit 15 outputs a DIR signal to the bidirectional buffer 16 and switches the bus of the bidirectional buffer 16 from the EPROM 12 side to the processor 11 direction or vice versa according to the program content change request from the upper CPU 14. And outputs a control signal to the buffers 17 and 18 to turn on one of the buffers 17 and 18,
From the PROM 12 side to the processor 11 direction, or upper C
Control is performed to switch the bus from the PU 14 to the processor 11.

The bidirectional buffer 16 is a gate circuit for switching buses, and the DONE from the processor 11 is used.
Signal to Gate terminal and DIR from control circuit 15
The signal is received by the DIR terminal to connect / disconnect the bus. For example, the DONE signal “H” from the processor 11 is set to Gat
When it is received as an e signal, it is asserted, and the DIR signal from the control circuit 15 switches the bus so that the bus passes from the EPROM 12 side toward the processor 11.

The buffers 17 and 18 are provided in the control circuit 15
One of them is turned on / off by a control signal from the CPU to switch the bus from the EPROM 12 side to the processor 11 direction or from the host CPU 14 to the processor 11 direction.

The RAM 19 is a memory for temporarily storing the downloaded program, and writing / reading is controlled by the WE signal and the OE signal from the processor 11. If the capacity of the internal RAM of the processor 11 is such that the downloaded program can be temporarily stored, the external RAM 19 is unnecessary.

As described above, the processor 11 has the upper CP.
U14 side and R of EPROM12 and EEPROM13
It is connected to two buses on the OM side.

Next, the operation of the download circuit configured as described above will be described.

As shown in FIG. 1, the processor 11 includes a higher CPU 14 side, an EPROM 12 and an EEPROM 1.
It is connected to two buses on the ROM side of 3 and is usually E
Although the process is performed according to the program stored in the PROM 12 or the EEPROM 13, when there is a program content change request from the upper CPU 14, the process downloaded from the upper CPU 14 is stored in the EEPROM 13. And after changing the program content, EEP
The processing is performed according to the program downloaded to the ROM 13.

First, the control circuit 15 outputs the DIR signal and the control signal to the bidirectional buffer 16 and the buffers 17 and 18 during the normal time when there is no program content change request, and controls as follows. That is, normally, the DIR signal is output to the bidirectional buffer 16, the control signal is output to the buffers 17 and 18, and the buffer 18 is turned on so that the signal passes from the ROM side to the processor 11. As a result, the buses of the bidirectional buffer 16 and the buffers 17 and 18 are switched so that the signal can pass from the ROM side to the processor 11. Also, a signal is allowed to flow from the ROM side to the processor 11 even when the system is reset.

When there is a program content change request from the host CPU 14, the control circuit 15 outputs the DIR signal and the control signal to the bidirectional buffer 16 and the buffers 17 and 18, and the processor 11 to the ROM side (EEPROM 13).
The bus of the bidirectional buffer 16 is switched so that the signal passes through, and the buffer 17 is turned on (the buffer 18 is turned off). As a result, the bidirectional buffer 16 and the buffer 1
7 and 18 buses are switched, and processor 11 sends EEP
A signal comes to pass through the ROM 13.

When the bus switching is performed by the program content change request, the processor 11 outputs the DONE signal "H" to the Gate terminal of the bidirectional buffer 16 to assert the bidirectional buffer 16. Here, the processor 11 outputs the DONE signal “H” after the system reset, and outputs the DONE signal “L” after the download is completed. The bidirectional buffer 16 receives the DONE signal from the processor 11 at the Gate terminal as a Gate signal and asserts it while the signal is "H" to put the bus in the connected state. The DONE signal also serves to disconnect the bus on the ROM side after the processor 11 finishes downloading.

When the processor 11 does not have such an output signal, it is set / exposed by an external register or the like.
You may make it reset.

Next, the program downloaded from the upper CPU 14 is stored in the RA connected to the processor 11.
It is temporarily stored in M19. If the capacity of the internal RAM of the processor 11 is such that the downloaded program can be temporarily stored, it is stored in the internal RAM.

The operation of the download circuit will be described in more detail below with reference to the processing flow of FIG.

FIG. 2 is a flow chart showing the download operation of the download circuit having the single processor 11, and ST in the figure shows each step of the flow.

First, in step ST1, the system reset of the processor 11 is turned on, and the bus is connected to the ROM side. Next, in step ST2, reading of the program from the EPROM 12 is started, and when downloading of the program is completed in step ST3, normal operation is started based on the program downloaded in step ST4.

That is, the processor 11 at the time of inputting the reset
Signal becomes "H", and the Gate signal of the bidirectional buffer 16 is asserted. The DIR signal of the bidirectional buffer 16 is controlled by the control circuit 15, and the EPROM
A signal passes from 12 to the processor 11. Therefore, at startup, the EPROM 12
The bus is connected to the
Read the contents of and download.

When the download is completed, the processor 11 negates the DONE signal, disconnects the EPROM 12 from the bus, and starts normal operation.

When the control circuit 15 receives the program change request from the upper CPU 14 in step ST5, the control circuit 15 switches the bus so that the signal passes from the upper CPU 14 side to the processor 11 in step ST6. Specifically, the control circuit 15 stores the DI in the bidirectional buffer 16 according to the program content change request from the upper CPU 14.
R signal is output and the bus of the bidirectional buffer 16 is EPRO
Control is performed to switch from the M12 side to the processor 11 direction, and a control signal is output to the buffers 17 and 18 to turn on the buffer 17 and control to switch the bus from the upper CPU 14 to the processor 11 direction.

Next, in step ST7, the upper CPU 14
Is downloaded to the RAM 19 connected to the processor 11, and when the download is completed in step ST8, the program stored in the RAM 19 is copied to the EEPROM 13 in step ST9 and the process returns to step ST4 to start normal operation. Where the top CP
Downloading from U14 to the RAM 19 connected to the processor 11 has already been described.

The processor 11 retains the program downloaded from the upper CPU 14 in the external RAM 19 or the internal RAM, and after receiving the downloaded program, copies the program from the RAM 19 to the EEPROM 13 to change the program content, and the EEPROM 13
Transition to normal operation state with the new program updated to.

As described above, the download circuit according to the present embodiment has a program rewritable EPR.
OM12 and EEPROM13, and this EPROM12
And EEPROM 13 via a bus, and EPR
The processor 11 (processor # 0) that processes the program stored in the OM 12 or the EEPROM 13, the upper CPU 14 that supplies the update program from the outside, and the output line of the upper CPU 14 when the program is rewritten is EPRO.
It connects to the bus of M12, downloads the program from the upper CPU 14 to the processor 11, and after downloading is completed, the downloaded program is stored in the EEPROM.
Since the control means 20 for controlling the transfer to the device 13 is provided, even if the program is changed during operation, the contents of the program can be changed externally without shutting down the power supply or replacing the program ROM. It can be downloaded.

FIG. 3 is a circuit diagram showing the configuration of the download circuit according to the second embodiment of the present invention, which is an example applied to the download circuit when the processors are multi-connected. In practice, it is particularly effective in a device in which processors are multi-connected as in the second embodiment.
In the description of the download circuit according to the present embodiment, the same components as those of the download circuit shown in FIG. 1 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 3, 11, 12, and 22 are multi-connected processors, 12 is an EPROM, and 13 is an EE.
PROM, 14 is a high-order CPU, 15 is a control circuit, 16 is a bidirectional buffer, 17, 18, 23 and 24 are buffers,
19, 25 and 26 are RAM, 27, 28 and 29 are AND
Gates 30 and 31 are OR gates.

Processors 11, 21, 22 and EPR
OM 12, EEPROM 13, control circuit 15, bidirectional buffer 16, buffers 17, 18, 23, 24, RAM
19, 25, 26, AND gates 27, 28, 29, O
The R gates 30 and 31 are mounted on, for example, one board.

The control circuit 15, the bidirectional buffer 16 and the buffers 17, 18, 23 and 24 are controlled so as to switch the buses as a whole and download changes in the program content from the outside to the processors 11, 21 and 22. The control means 40 is configured.

The processors 11, 21 and 22 are EP
The normal operation process or the download process is performed according to the program stored in the ROM 12 or the EEPROM 13. The data input terminal D, the system reset input terminal RST, the start signal input terminal STAR.
T, DONE signal output terminal DONE, write enable signal output terminal WE for controlling various memories, and output enable signal output terminal OE. Note that, for convenience of explanation, the processors 11, 21, and 22 are represented as processors # 0, # 1, and #N, respectively.

The data input terminal D has an EPROM 12,
Program or data is input from the EEPROM 13 or the host CPU 14, and the output terminal DONE is AN.
Bidirectional buffer 1 via D gates 27, 28, 29
6, connected to buffers 17 and 18. A signal obtained by inverting a positive logic system reset signal is input to the other input terminals of the AND gates 27, 28, 29, and
The D gates 27, 28 and 29 take the AND logic of the DONE signal and the inverted signal of the reset signal, and the bidirectional buffer 1
6, output to buffers 23 and 24, respectively.

As described above, the DONE signal is a signal for asserting the Gate signals of the bidirectional buffer 16, the buffers 23 and 24 in the processors # 0, # 1 and #N, and the processors # 0, # 1 and #. N is “H” after reset
Is output, and “L” is output after the download is completed. In this embodiment, multi-connected processors # 0, # 1, #
To ensure that N can assert the bidirectional buffer 16 and the buffers 23 and 24, the processor # 0, # is activated after the reset is completed and the system reset signal becomes “L”.
The DONE signals from 1 and #N are output to the bidirectional buffer 16 and the buffers 23 and 24.

In this case, the DONE signal is input to the reset signal of the processor of the next stage, and the reset is held for the processor # 1 of the next stage until, for example, the download of the processor # 0 is completed.

As described above, when the processor in the previous stage finishes the download, the processor in the next stage starts the download.

Further, DON of the processor #N at the final stage
The E signal is distributed to all the processors connected as a start signal to notify that the download of all the processors is completed.

Further, the write enable signal output terminal W
E, WE signal and OE signal for controlling writing / reading of data are output from the output enable signal output terminal OE to R
AM19 or EPRO via OR gates 30 and 31
It is output to M12 or EEPROM 13.

The EPROM 12 includes processor # 0,
It is a rewritable ROM that stores programs and data used in # 1 and #N, and has a boot program and an operation application program written in advance. If there is no program change, E
The operation application programs and data stored in the PROM 12 are constantly processed by the processors # 0, #.
1 and #N, and the processors # 0, # 1 and #N execute the program of the EPROM 12.

The EEPROM 13 is an electrically rewritable ROM that supplies programs and data to the processors # 0, # 1, #N in place of the EPROM 12 after the program is changed. Used for storing change program. Specifically, according to the processing shown in FIG.
The contents of the PROM 12 and the download program from the upper CPU 14 are written from the processors # 0, # 1, #N and the RAM 19. Therefore, after the program change, the program and data stored in the EEPROM 13 are output to the processors # 0, # 1, #N,
The processors # 0, # 1 and #N execute the program of the EEPROM 13.

The upper CPU 14 is a device for controlling the entire download circuit, outputs a program content change request to the control circuit 15 to change the program content, controls the control circuit 15, and downloads the download program to the processors # 0, # 1. , #N to download.

The control circuit 15 has a bidirectional buffer 16 in accordance with a program content change request from the host CPU 14.
And the buffers 17 and 18 are controlled. That is, the control circuit 15 outputs a DIR signal to the bidirectional buffer 16 in accordance with a program content change request from the upper CPU 14 to direct the bus of the bidirectional buffer 16 from the EPROM 12 side to the processors # 0, # 1, and #N. Alternatively, control is performed to switch to the opposite direction, and a control signal is output to the buffers 17 and 18 to turn on one of the buffers 17 and 18, and the processor # 0, # from the EPROM 12 side.
1, #N direction or from the upper CPU 14 to processor #
Control is performed to switch the bus in the 0, # 1, and #N directions.

The bidirectional buffer 16 is a gate circuit for switching the bus, and the DONE from the processor 11 is used.
Signal to Gate terminal and DIR from control circuit 15
The signal is received by the DIR terminal to connect / disconnect the bus. For example, when the DONE signal “H” from the processors # 0, # 1, and #N is received as a Gate signal, it is asserted, and the DIR signal from the control circuit 15 asserts the bus to the EPROM 12
The bus is switched so as to pass from the side toward the processor 11.

The buffers 23 and 24 are gate circuits for switching buses, and D from the processors # 1 and #N.
The gate terminal receives the ONE signal to connect / disconnect the bus. In the present embodiment, the EEPR except the processor # 0 is used.
Since the transfer (writing) to the OM 13 is not performed, the bidirectional buffer is used instead of the bidirectional buffer. The buffers 23 and 24 assert when receiving the DONE signal “H” from the processors # 1 and #N as the Gate signal.

The RAMs 19, 25 and 26 are memories for temporarily storing the downloaded programs, and the WE signals from the processors # 0, # 1 and #N, OE.
Writing / reading is controlled by a signal. The external RAMs 19, 25, and 26 are unnecessary if the internal RAMs of the processors # 0, # 1, and #N have a capacity capable of temporarily storing the downloaded program.

As described above, the multi-connected processors # 0, # 1 and #N are connected to the upper CPU 14 side and the EPROM.
12 and EEPROM 13 are connected to two buses on the ROM side.

Next, the operation of the download circuit configured as described above will be described.

At the time of resetting, the processor # 0 supplies the DONE signal "H" to the Gate terminal of the bidirectional buffer 16.
Is output and the bidirectional buffer 16 is asserted. Here, processor # 0 is set to DONE after system reset.
The signal "H" is output, and after the download is completed, the DONE signal "L" is output. The bidirectional buffer 16 receives the DONE signal from the processor # 0 as a Gate signal at the Gate terminal and asserts it while the signal is "H" to make the EPROM.
The signal passes from 12 to the processor.

At this time, the processor # 0 holds the reset signal of the next stage (that is, the processor # 1) until the download of its own processor is completed.

The processor # 1 starts the download when the download of the processor # 0 is completed.

In this way, the download is performed step by step up to the processor #N.

When the download is completed, the processor #N at the final stage notifies all the processors that the download of all the processors is completed. The processor receiving this shifts to the normal operation.

The operation of the download circuit will be described in detail below with reference to the processing flow of FIG.

FIG. 4 shows multi-connected processors # 0 to # 0.
It is a flowchart which shows operation | movement of the download circuit which has #N.

First, in step ST11, processor # 0
Turn on the system reset and connect the bus to the ROM side. Then, in step ST12, the processor # 0 makes an EP.
Starting to read the program from the ROM 12 and resetting the processors # 1 to #N, step ST
At 13, the program download is completed.

That is, processor # 0 at reset input
Signal becomes "H", and the Gate signal of the bidirectional buffer 16 is asserted. The DIR signal of the bidirectional buffer 16 is controlled by the control circuit 15, and the EPROM
The signal is passing from 12 toward processor # 0. Therefore, at startup, the EPROM 12
Side is connected to the bus, processor # 0 is EPROM12
Read the contents of and download.

At this time, the processor # 0 holds the reset signal of the next stage (that is, the processor # 1) until the download of its own processor is completed.

Next, at step ST14, the processor #x at the next stage (here, processor # 1) (where 1≤x
≦ N) reads the program from the EPROM 12, determines whether x has become N (x = N) in step ST15, and if x = N, increments x (x = x + 1) in step ST16. It returns to step ST14.

In this way, steps ST14-
In step ST16, the download is performed for the processors # 1 to #N. For example, the processor # 1 starts the download when the download of the processor # 0 is completed, and sequentially downloads to the processor #N step by step.

When the download of all the processors is completed (step ST17), normal operation is started based on the program downloaded in step ST18.

That is, when the download is completed, the processor #N at the final stage distributes the DONE signal to all the processors connected as a start signal, and notifies all the processors that the download of all the processors is completed. Receiving this, the processors # 1 to #N shift to normal operation.

When the control circuit 15 receives the program change request from the upper CPU 14 in step ST19, the control circuit 15 switches the bus so that the signal passes from the upper CPU 14 side to the processor # 0 in step ST20.
Specifically, the control circuit 15 outputs a DIR signal to the bidirectional buffer 16 in response to a program content change request from the upper CPU 14 and sets the bus of the bidirectional buffer 16 to EP.
The control for switching from the ROM 12 side to the processor # 0 direction is performed, and a control signal is output to the buffers 17 and 18 to turn on the buffer 17 and control for switching the bus from the upper CPU 14 to the processor # 0 direction.

Then, in step ST21, the upper CPU 1
4 is downloaded to the RAM 19 connected to the processor # 0, and when the download is completed in step ST22, the program stored in the RAM 19 is copied to the EEPROM 13 in step ST9.

The processor # 0 changes the program content by holding the program downloaded from the upper CPU 14 in the external RAM 19 or the internal RAM and copying it from the RAM 19 to the EEPROM 13 after receiving the download program.

Then, in step ST24, the processor #
0 is reset and input to the processors # 1 to #N. That is, the processor # 0 reboots the processor # 1 by asserting the DONE signal when the download of its own processor is completed.

In step ST24, the processors # 1 to # 1
When reset and input to #N, the processor #x at the next stage (here, the processor # 1) reads the program from the EEPROM 13 to which the latest program is copied in step ST25, and x becomes N in step ST26 (x = Whether N) or not, and when x = N is not satisfied, x is incremented (x = x + 1) in step ST27 and the process returns to step ST25. When x becomes N in step ST26, the process proceeds to step ST28, and when the download of all the processors is completed, the process returns to step ST18 and the normal operation is started based on the downloaded program.

In this way, in steps ST25 to ST27, the processor #N is rebooted step by step, and when all the processors finish the reboot, the normal operation is started.

As described above, the download circuit according to the second embodiment has a program rewritable E
PROM 12 and EEPROM 13, and this EPROM
12 and EEPROM 13 through a bus,
Multi-connected processors # 0, # for processing programs stored in the PROM 12 or the EEPROM 13
1, #N and upper C that supplies update program from outside
When the program is rewritten, the PU 14 and the output line of the upper CPU 14 are connected to the bus of the EPROM 12 so that the upper CPU
The program from 14 is downloaded to the processor 11, and after the download is completed, the program downloaded to the processor # 0 is transferred to the EEPROM 13, and the program transferred to the EEPROM 13 is downloaded to the other processors # 1 and #N in sequence. Since the control means 40 for controlling the above is provided, the EPROM 12 and the EEPROM 13 can be shared by performing the download control for each of the processors # 0 to #N, and further the program change during operation can be changed. It is possible to obtain the effect of enabling.

Therefore, it is sufficient to use the EPROM 12 and the EEPROM 13 common to the processors # 0 to #N, so that the cost does not increase even if the number of processors is increased. Further, even when a program is changed during operation, the download control described above has an excellent effect that it is not necessary to turn off the power supply or replace the program ROM or the like.

In the download circuit according to the second embodiment, since the download is performed for each processor, it is possible that the boot time becomes longer as the number of processors connected in multiple increases. Therefore, a download circuit that can be downloaded at a time even if the number of processors increases will be shown in a third embodiment below.

FIG. 5 is a circuit diagram showing a configuration of a download circuit according to the third embodiment of the present invention, which is an example applied to the download circuit when the processors are multi-connected. In the description of the download circuit according to the present embodiment, the same components as those of the download circuit shown in FIG. 3 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 5, 11, 12, and 22 are multi-connected processors, 12 is an EPROM, and 13 is an EE.
PROM, 14 is a high-order CPU, 15 is a control circuit, 16 is a bidirectional buffer, 17, 18, 23 are buffers, 19,
25 and 26 are RAMs, 41 is an arbitration circuit (monitoring means), 4
Reference numerals 2 and 43 are AND gates, and 44, 45 and 46 are OR gates.

The processors 11, 21, and 22 have data input terminals D, system reset input terminals RST, start signal input terminals STARTN, and load monitoring terminals AC.
K, DONE signal output terminal DONE, write enable signal output terminal WE for controlling various memories, and output enable signal output terminal OE.

The data input terminal D has an EPROM 12,
A program or data is input from the EEPROM 13 or the host CPU 14, and the output terminal DONE of the processor 11 is connected to the bidirectional buffer 16 via the AND gate 42. Further, the output terminal D of the processor 21
The ONE is connected to the processors 11 and 2 via the OR gate 44.
1, 22 are connected to the start signal input terminals STARTN, the output terminal DONE of the processor 22 is connected to the buffer 23 via the AND gate 43, and OR
It is connected to the other input terminal of the gate 44. Also, AN
A signal obtained by inverting a positive logic system reset signal is input to the other input terminals of the D gates 42 and 43, and AND
The gates 42 and 43 take the AND logic of the DONE signal and the inversion signal of the reset signal and output them to the bidirectional buffer 16 and the buffer 23, respectively.

The output side of the buffer 23 is connected to the data input terminals D of the processors # 1 to #N.

EPROMs of the processors 21 and 22
Output enable signal output terminal EPROMOE1 to 12
To N, output enable signal output terminals to EEPROM 13, EEPROMOE1 to N, and load monitoring terminal ACK
1 to N are input to the arbitration circuit 41.

The output enable signal output terminal EPROMOE0 of the arbitration circuit 41 is connected to the OE terminal of the EPROM 12 via the OR gate 45, and the output enable signal output terminal EEPROMROME0 is connected to the OE terminal of the EPROM 12 via the OR gate 46. Connected.

The output enable signal output terminal EPROMOE0 to the EPROM 12 of the processor 11 is O
The OE terminal of the EPROM 12 is connected via the R gate 45, and the output enable signal output terminal EEPROMOE0 to the EEPROM 13 is connected to the EP terminal via the OR gate 46.
It is connected to the OE terminal of the ROM 12.

The arbitration circuit 41 includes processors 21, 2
A from each terminal of the load monitoring terminals ACK1 to N
Based on CK signal input, ROM (EPROM12, EEP
This is a circuit for monitoring whether or not all the processors 21 and 22 are normally loaded at the same timing during address generation and download for the ROM 13).

As described above, the DONE signal is a signal for asserting the Gate signal of the bidirectional buffer 16 and the buffer 23 in the processors # 0, # 1 and #N, and the processors # 0, # 1 and #N are , "H" is output after reset, and "L" is output after completion of download. In this embodiment, the DONE signal of the processor # 0 is set to the processor # 1,
The reset signal RST of #N is output. As a result, when the DONE signal of the processor # 0 is negated, the processors # 1 and #N start downloading all at once.

As described above, when the processor # 0 finishes downloading, the processors # 1 and #N can download at once.

Furthermore, when the processors # 1 and #N have normally completed the download, "0" is detected, and this is set to ST.
It has a function of notifying all processors as an ARTN signal.

The operation of the download circuit will be described in detail below with reference to the processing flow of FIG. In describing the processing flow of FIG. 6, the same processing steps as those of the processing flow of FIG. 4 are denoted by the same reference numerals.

First, at step ST11, processor # 0
Turn on the system reset and connect the bus to the ROM side. Then, in step ST12, the processor # 0 makes an EP.
Starting to read the program from the ROM 12 and resetting the processors # 1 to #N, step ST
At 13, the program download is completed.

That is, processor # 0 at reset input
Signal becomes "H", and the Gate signal of the bidirectional buffer 16 is asserted. The DIR signal of the bidirectional buffer 16 is controlled by the control circuit 15, and the EPROM
The signal is passing from 12 toward processor # 0. Therefore, at startup, the EPROM 12
Side is connected to the bus, processor # 0 is EPROM12
Read the contents of and download.

When the DONE signal of the processor # 0 is negated, the processors # 1 and #N start downloading all at once in step ST31.

At this time, the arbitration circuit 15 monitors all the ACK signals ACK1 to ACK output from the processors # 1 and #N so that all the processors do not miss the reading, and controls them so that they can be downloaded normally. .

When the download of all processors is completed (step ST17), the DONE signals of the processors # 1 and #N are negated in step ST32 to shift to normal operation, and normal operation is performed based on the program downloaded in step ST18. Start.

As described above, the download circuit according to the third embodiment has the arbitration circuit 4 for monitoring the download state.
Since it has 1, the EEPRO is monitored by monitoring that all the processors are downloading normally.
The program transferred to M13 can be simultaneously downloaded to all the other processors # 1 and #N, and the download time can be greatly shortened.

In each of the above embodiments, the download circuit is applied to the multi-connected processors, but the type and connection form of the connected processors may be any. For example, several processors may be mounted on one board, and the boards may be separated as long as they operate under the same program. In addition, some or all of the processor
For example, it may be configured by a DSP.

Further, in each of the above-mentioned embodiments, the EEPROM is used for storing the change program, but of course the invention is not limited to this, and a flash memory or the like can be used. Further, although the host CPU is used as the supply means for supplying the program from the outside, it is not limited to the CPU as long as the program can be supplied.

Furthermore, it goes without saying that the number of memories, buffers, gate circuits, etc. constituting the download circuit, the type connection state, etc. are not limited to those in the above-described embodiment.

[0109]

In the download circuit according to the present invention, a program rewritable memory, a processor connected to the memory via a bus for processing the program stored in the memory, and a program supplied from the outside Control so that the supply means and the output line of the supply means are connected to the bus of the memory when the program is rewritten, the program of the supply means is downloaded to the processor, and the downloaded program is transferred to the memory after the download is completed. Therefore, even if a program change occurs during operation, the change in the program content can be downloaded from the outside without powering off or replacing the program ROM.

Further, the download circuit according to the present invention is
A plurality of processors are connected to the memory, and the control means connects the output line of the supply means to the bus of the memory when the program is rewritten, downloads the program of the supply means to the first processor, and after the download is completed, Since the program downloaded to the first processor is transferred to the memory and the program transferred to the memory is controlled to be downloaded to another processor, it is possible to control each processor individually. By eliminating the need to prepare a program ROM, each program can be downloaded from a common program ROM, and changes to the program contents can be downloaded from the outside to enable downloading to each processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a download circuit according to a first embodiment to which the present invention is applied.

FIG. 2 is a flowchart for explaining a download operation of the download circuit.

FIG. 3 is a block diagram showing a configuration of a download circuit according to a second embodiment to which the present invention is applied.

FIG. 4 is a flowchart for explaining a download operation of the download circuit.

FIG. 5 is a block diagram showing a configuration of a download circuit according to a third embodiment of the present invention.

FIG. 6 is a flowchart for explaining a download operation of the download circuit.

FIG. 7 is a diagram for explaining a relationship between a conventional processor and a memory.

FIG. 8 is a diagram for explaining a relationship between a conventional processor and a memory.

[Explanation of symbols]

11,12,22 processor, 12 EPROM, 1
3 EEPROM, 14 upper CPU (supply means), 1
5 control circuits, 16 bidirectional buffers, 17, 18, 2
3,24 buffer, 19,25,26 RAM, 2
0,40 control means, 41 arbitration circuit (monitoring means)

 ─────────────────────────────────────────────────── --Continued front page (72) Inventor Jiro Aso 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. A program rewritable memory, a processor connected to the memory via a bus to process the program stored in the memory, a supply means for supplying the program from the outside, and a program rewriting time. The output line of the supply means is connected to the bus of the memory, the program of the supply means is downloaded to the processor, and the control means for controlling the transfer of the downloaded program to the memory after the download is completed. Download circuit characterized by having. 2. The download circuit according to claim 1, wherein a plurality of processors are connected to the memory, and the control unit connects an output line of the supply unit to a bus of the memory when rewriting a program. Then, the program of the supply means is downloaded to the first processor, after the download is completed, the program downloaded to the first processor is transferred to the memory, and the program transferred to the memory is transferred to another processor. A download circuit characterized by controlling to download. 3. The download circuit according to claim 1, further comprising a monitoring unit for monitoring a download state, wherein the plurality of processors are connected to the memory, and the control unit controls the supply unit when rewriting a program. Is connected to the bus of the memory to download the program of the supply means to the first processor, and after the download is completed, the program downloaded to the first processor is transferred to the memory, and further the memory The download circuit is characterized in that the programs transferred to the CPU are controlled to be downloaded to other processors all at once, and the monitoring means monitors that all the processors are normally downloading at the time of downloading. 4. The download circuit according to claim 1, wherein the supply means is a microcomputer connected to the control means.