JPH11338687A - Program rewriting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily rewrite a program of an extension unit without exerting influences on the operations of a host system and of other extension units. SOLUTION: This system easily rewrites memory contents without exerting influences on the operations of a host system and of other extension units by such manners that the operation of a CPU is stopped from a host system 10 through a bus interface 24 and in the meantime, a nonvolatile flash ROM 22 is directly accessed and program contents stored in the ROM 22 are rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program rewriting system, and more particularly, to a program rewriting system for rewriting a program stored in a memory in an extension unit connected to a host system via an extension bus. About.

[0002]

2. Description of the Related Art Conventionally, an arbitrary extension unit is connected to a host system including a personal computer (hereinafter, abbreviated as a personal computer), a workstation, and the like via an extension bus. The functions to be extended were realized.

For example, FIG. 9 shows a conventional system configuration diagram in which a plurality of expansion units are connected to a host system. In FIG. 9, a host system 100 includes an expansion bus 102 for supplying data, power and the like. A plurality of extension units 104 and 106 are connected via the extension unit, and each extension unit realizes a function to be extended to the host system 100.

[0006] The expansion unit 106 shown in FIG. 9 has a bus interface 116 that operates according to the expansion bus standard, and communicates with the host system 100 via the expansion bus 102. . As other configurations, the CPU 110 that performs control as the center of the operation of the extension unit 106, and the CPU 110
The ROM 110 includes a non-volatile memory for storing a program to be supplied to the CPU 110, a RAM 114 used as a work memory of the CPU 110, and the like.

The program (firmware) in the expansion unit 106 is generally stored in the ROM 112 in the unit. However, it is necessary to change the program contents due to an error in the contents of the program, a change in function, or an upgrade. May be. For this reason, a rewritable nonvolatile memory such as a flash EEPROM is used as the ROM 112 in the extension unit 106.

FIG. 10 shows a system configuration diagram used when the host system rewrites the memory contents of the ROM in the expansion unit connected via the expansion bus. ROM via a ROM writing connector 134 provided in the unit 130
ROM writing external device 1 for writing data to 112
32 is connected, and the data in the ROM 112 is rewritten. The ROM 112 can obtain a power supply, an address signal, a data signal, a write signal, and the like from the ROM write external device 132 via the ROM write connector 134.

When the data in the ROM 112 is rewritten, the R of the CPU 110 is used to avoid signal collision.
Although access to the OM 112 must be prohibited, in the case of a simple circuit in which the ROM 112 is directly connected to the CPU 110, a method of turning off the power of the extension unit 116 is used to float the bus of the ROM 112. That is, in the system as shown in FIG. 10 in which the power to the expansion unit 116 is supplied from the host system 100, the power of the host system 100 must also be turned off in order to turn off the power of the expansion unit 116. Stops functioning.

As described above, when the power of the entire system is turned off, the expansion unit 104
The power supply from the power supply is lost, and all the internal circuits stop operating. However, in the extension unit 130,
The power supplied from the ROM writing external device 132 is
Since the circuit configuration is such that no current flows into the power supply of the extension unit, it is supplied only to the ROM 112, but other circuits inside the extension unit 130 are not operated.

The address bus and the data bus used by the ROM writing external device 132 are shared with those used by the CPU 110, but the circuits other than the ROM writing external device 132 and the ROM 112 are powered off. Therefore, circuits other than the ROM writing external device 132 do not output signals. As a result, the content of the memory of the ROM 112 is rewritten while avoiding signal collision.

Further, as a method of rewriting a program in a state of being connected to the host system without turning off the power of the host system and the extension unit, for example, a download apparatus as disclosed in Japanese Patent Application Laid-Open No. 8-194621 is disclosed. is there.

FIG. 11 is a block diagram of a download apparatus disclosed in Japanese Patent Application Laid-Open No. 8-194621. In FIG. 11, a CPU 140 is a circuit device that performs a central function of the system.
Various devices are connected to each other through 4. ROM1
Reference numeral 48 denotes a memory for storing a system startup program and various fixed data. Bank memory circuit 150
As shown in FIG. 12, the entire storage area is divided into two areas, bank 1 and bank 2, and these address arrangements constitute a memory that can be interchanged by the bank switching circuit 152. I have.

The two memory areas of the bank memory circuit 150 are respectively programmed memory (firm area 1).
68) and a work memory (work area 166). The bank switching circuit 152 switches the address arrangement of the bank 1 and the bank 2 in the bank memory circuit 150 in accordance with a predetermined bank select signal output from the output port of the CPU 140.

The higher-level interface unit 142 is a circuit device that interfaces with a higher-level device (not shown) that is a supply source of a program to be downloaded.
The flash EEPROM 146 is a writable nonvolatile memory and stores a program downloaded from a higher-level device (not shown). Also, the bank memory circuit 150 and the flash EEPROM 146
Are connected by a local bus 156, and transfer a program stored in the bank memory circuit 150 to the flash EEPROM 146 by the transfer control circuit 144 without affecting the operation of the CPU 140.

FIG. 12 shows the above-mentioned JP-A-8-19462.
1 shows an arrangement of an address space in a download device disclosed in Japanese Patent Application Publication No. JP-A-2005-11095. In this address space, the ROM 148 and the bank memory circuit 15 shown in FIG.
0, and the bank memory is allocated to the work area 166.
And a firmware area 168. The work area 166 is an area for temporarily storing data necessary for executing the firmware.
Is an area for storing firmware referred to by the CPU 140 during execution.

The bank memory circuit 150 can instantaneously exchange the contents of the work area 166 and the firmware area 168 by exchanging the address arrangement of the bank 1 and the bank 2 by the bank switching circuit 152.

Then, the CPU 140 stores the firmware downloaded from the higher-level device in the bank currently arranged in the work area 166. After all data download is completed, the CPU 140 activates the transfer control circuit 144 and copies the firmware stored in the work area 166 to the flash EEPROM 146. Since this data transfer is performed through the local bus 156, the CPU 140
To execute other processing. When the data transfer by the transfer control circuit 144 ends, the CPU 1
Reference numeral 40 outputs a select signal to the bank switching circuit 152 to switch bank memories. Thereby, work area 1
66 and the contents of the firmware area 168 are switched, and the CP
In U140, the process proceeds based on the updated firmware.

A conventional example of this type of program rewriting system is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-21878.
No. 1, Japanese Patent Application Laid-Open No. 9-218788, and the like.

[0018]

However, in such a conventional program rewriting system, FIG.
When the contents of the ROM 112 of the expansion unit 130 connected to the expansion bus 102 are rewritten as shown in FIG. 1, it is necessary to turn off the power supplied from the host system 100 and perform writing by using a separately prepared external device 132 for ROM writing. Therefore, the operation of the host system 100,
The operation of all the other extension units connected to the extension bus 102 must be stopped, which causes a problem that the whole system is down and the ROM writing external device 132 is additionally required.

As shown in FIG. 11, in the method of rewriting the contents of the program stored in the memory without turning off the power of the host system and the power of the extension unit, the program executed by the CPU 140 during the rewriting of the program is executed. It is necessary to prepare a separate memory area for storing. Therefore, a mechanism for switching between an original program memory and a work memory for temporarily storing a program, a plurality of memories, and a transfer control circuit 144 for transferring the contents of the work memory to the flash EEPROM 146 are required. Was complicated.

In the case of the prior art shown in FIG. 11, when a program is downloaded from a host system, the CPU 140 needs to interrupt the original work and perform the download work, and the memory capacity is not large enough to store the program. More than twice the capacity required for
However, there is a problem that even if it is necessary to rewrite, it cannot be rewritten.

Further, the above-mentioned Japanese Patent Application Laid-Open No. 9-218781
In Japanese Unexamined Patent Application Publication No. 9-218788 and the like, the loaded program is temporarily stored in another storage unit or written in a spare memory, so that an extra storage area or memory is separately prepared. There was a problem that must be.

The present invention has been made in view of the above,
The program contents of the expansion unit can be easily rewritten without affecting the operation of the host system or the operation of other expansion units connected to the expansion bus, reducing the downtime of the host system or the expansion unit It is an object to obtain a program rewriting system that can perform the program.

[0023]

In order to achieve the above object, in a program rewriting system according to the present invention, a program stored in an extension unit connected to a host system via an extension bus is provided. In the program rewriting system for rewriting a program, the extension unit includes a CPU for controlling the inside of the extension unit,
A rewritable nonvolatile memory for storing a program to be executed by a PU, and an interface circuit capable of accessing the nonvolatile memory from the host system and performing a reset output from the host system to the CPU, The host system directly accesses the non-volatile memory while the CPU is in an operation stop state, and rewrites a program stored in the non-volatile memory.

According to this, the host system puts the CPU of the extension unit, which rewrites the program, into an operation halt state, during which the non-volatile memory is directly accessed to rewrite the program contents stored in the non-volatile memory. This makes it possible to easily rewrite the program contents of the expansion unit without affecting the operation of the host system and other expansion units connected to the expansion bus, and to reduce the time to stop the host system and the expansion unit can do.

In the program rewriting system according to the next invention, the interface circuit according to the invention includes a signal processing circuit for generating an interrupt to the host system by an interrupt signal, and the signal processing circuit based on a request from the host system. A reset sequence circuit that causes the CPU to stop operating, and a bus selector that switches a bus connected to the nonvolatile memory to one of the host system or the CPU by a select signal from the reset sequence circuit, The host system operates the CP by the reset sequence circuit.
U is brought into an operation stop state, the bus connected to the nonvolatile memory by the bus selector is connected to the host system, and the contents of the program stored in the nonvolatile memory are rewritten.

According to this, the host system stops the operation of the CPU by the reset sequence circuit, connects the bus connected to the nonvolatile memory by the bus selector to the host system, and stores the bus in the nonvolatile memory. The contents of the non-volatile memory can be easily rewritten without affecting the operation of the host system and other expansion units, thereby reducing the time for stopping the host system and the expansion units. be able to.

In a program rewriting system according to the next invention, in a program rewriting system for rewriting a program stored in an expansion unit connected to a host system via an expansion bus, Is a CPU that controls the inside of the expansion unit
A rewritable nonvolatile memory for storing a program to be executed by the CPU, an execution memory for transferring and executing program contents stored in the nonvolatile memory when the unit body operates, And an interface circuit capable of accessing the nonvolatile memory from the host system and capable of outputting a reset from the host system to the CPU, wherein the host system directly accesses the nonvolatile memory and is stored in the nonvolatile memory. It rewrites the contents of the program.

According to this, since the host system directly accesses the non-volatile memory and rewrites the program contents stored in the non-volatile memory, the host system, other expansion units connected to the expansion bus, and The program contents of the extension unit can be easily rewritten without affecting the operation of the extension unit that is rewriting the program, and the time for stopping the host system and the extension unit can be reduced.

In the program rewriting system according to the next invention, the interface circuit according to the invention comprises a signal processing circuit for generating an interrupt to the host system by an interrupt signal, and the signal processing circuit based on a request from the host system. A reset sequence circuit for stopping a CPU, a bus selector for switching a bus connected to the nonvolatile memory to one of the host system and the CPU, and a bus switching control circuit for performing switching control of the bus selector. After the transfer of the program stored in the nonvolatile memory to the execution memory is completed, the bus switching control circuit switches a bus selector to connect the bus connected to the nonvolatile memory to the host system. , Program contents stored in the non-volatile memory It is intended to be rewritten.

According to this, the contents of the non-volatile memory can be easily rewritten without affecting the operation of the host system, other extension units, and the extension units that are rewriting the program. The time for stopping the extension unit can be reduced.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a program rewriting system according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a diagram for explaining a program rewriting system of an extension unit according to the first embodiment, and shows a configuration diagram of an entire system in which a plurality of extension units are connected to a host system. The first embodiment is characterized by the configuration of the expansion unit 16 in FIG. 1, but the other parts of the host system 10, the expansion bus 12, and the other expansion units 14 are the same as those of the conventional example (the corresponding configuration shown in FIG. 9). ) Is the same as that of FIG.

The extension unit 16 is a flash ROM 2
When the flash ROM 22 is viewed from the CPU 20, the flash ROM 22 can be viewed as a read-only memory (ROM). The bus interface 24 is a circuit that performs an interface function between the host system 10 and the extension unit, and can communicate with the host system 10 via the extension bus 12. Further, the bus interface 24 has a function of resetting the CPU 20 in response to a request from the host system 10.

FIG. 2 shows the bus interface 24 of FIG.
FIG. 2 is a diagram illustrating a detailed circuit configuration in FIG. 2, the bus interface 24 includes an extended bus signal processing circuit 30, a bus selector 32, and a reset sequence circuit 3.
4, I / O ports 36, 38, etc. The expansion bus signal processing circuit 30 is a flash ROM 2
2 is a signal processing circuit that maps the I / O port 36 to the address space of the host system 10 and generates an interrupt to the host system 10 by the interrupt signal 42.
The bus selector 32 connects the bus 40 connected to the flash ROM 22 to the host system 10 or the CPU 20.
The operation is performed to switch to one of them.

The reset sequence circuit 34 is a sequence circuit for performing a reset process of the CPU 20 when there is a request from the host system 10. / O port 38, R for host system 10
The reset processing of the CPU 20 and the rewriting timing of the program in the ROM 22 are adjusted using the OM write permission interrupt 42 and the reset notification interrupt 44 for the CPU, respectively. Reference numeral 48 denotes a bus select signal described later.

FIG. 3 shows a flash RO according to the first embodiment.
It is a flowchart explaining the flow of the program rewriting process in M22. First, in the host system 10, when the rewriting process of the flash ROM 22 of the extension unit 16 is started, the operation of the CPU 20 is stopped, and
In order to switch the bus 40 of the flash ROM 22 to the host system side, the I / O port 36 is set, and the bus interface 24 is requested to reset the CPU 20 (step S100).

In the bus interface 24, the CPU 2
When a reset request of 0 is received (step S200), the reset sequence circuit 34 generates an interrupt to the CPU 20 (step S202) and notifies the CPU 20 of a reset (step S202). When the CPU 20 detects the reset notification interrupt (step S300), it interrupts the process currently being executed and sets a state where no data inconsistency occurs even if the reset is applied (step S302).
I / O port 38 is set and bus interface 2
4 is notified of reset permission (step S30).
4).

When the reset sequence circuit 34 of the bus interface 24 detects the reset permission by accessing the I / O port 38 (step S204),
A reset (operation stop) is generated for the CPU 20 (step S310), and the bus select signal 48
The bus selector 32 is controlled by the
The connection of the bus 40 of the M22 is switched from the CPU 20 to the host system 10 (step S206). Also,
Reset sequence circuit 3 of bus interface 24
In step S4, an interrupt to the host system 10 is generated to notify the ROM rewrite permission (step S20).
8), reset of CPU 20 is completed (step S2)
10).

On the other hand, in the host system 10,
When rewriting permission of the flash ROM 22 is detected, an interrupt process is performed (step S110), and the flash RO
M22 is accessed to perform write, read, compare, and other processing to rewrite the program contents stored in ROM 22 (step S112). RO
When the rewriting of the program content of M22 is completed, the host system 10 resets the I / O port 36 to
A request for reset release is issued to the PU 20 (step S11).
4), end the ROM rewriting process (step S11)
6).

In the bus interface 24, the CP
Upon receiving a reset release request to U20 (step S2)
20), the reset sequence circuit 34 controls the bus selector 32 with the bus select signal 48 to connect the bus 40 to the flash ROM 22 with the host system 10.
At the same time as switching from the side to the CPU 20 side, the reset of the CPU 20 is released (step S222), and the reset release of the CPU 20 is completed (step S224).

In this way, the reset C is released.
The PU 20 refers to the flash ROM 22 of the updated program contents and reads the initial program (IP
L: Initial program loader) (Step S320).

FIG. 4 shows a comparison between the configuration of the first embodiment shown in FIG. 1 and the configuration of the conventional example shown in FIG. The transfer control circuit, the ROM, the bank memory circuit, the bank switching circuit, and the like shown by the dotted lines in FIG. 4 are necessary for the conventional system, but are unnecessary circuits in the first embodiment. The configuration is simplified, and the program rewriting operation can be performed with simple software.

As described above, according to the first embodiment, it is not necessary to turn off the power or the like when rewriting the program of the extension unit, so that the operation of the host system and other extension devices connected to the extension bus are not required. It can be performed without affecting the operation of the unit.

The rewriting of the program in the extension unit can be achieved by rewriting the program of the extension unit with simple software and hardware. Further, the time for stopping the system is only the time for memory access for rewriting the program, and the time for stopping the extension unit can be reduced.

Embodiment 2 FIG. 5 is a diagram for explaining a program rewriting system for an extension unit according to the second embodiment, and shows a configuration diagram of an entire system in which a plurality of extension units are connected to a host system. The second embodiment is characterized by the configuration of the extension unit 50 in FIG. 5, but the other parts of the host system 10, the extension bus 12, and the other extension units 14 are the same as those in the conventional example, and therefore the description is omitted. I do.

As shown in FIG. 5, the extension unit 50
Is a unit composed of a CPU 20, a RAM 52, a ROM 22, a bus interface 54, and the like, in which the CPU 20 operates by referring to the contents of the RAM 52. The ROM 22 is a flash ROM for storing a program to be executed by the CPU 20, and transfers the program to the RAM 52 when the CPU 20 is initialized, and executes the program. After the transfer of the program, the CPU 20 does not access the flash ROM 22, so that the host system 10 can freely access the flash ROM 22.

The bus interface 54 is a circuit that functions as an interface between the host system 10 and the extension unit 50. Communication is performed between the host system 10 and the CPU 20 via the extension bus 12. The bus interface 54 is connected to the host system 10.
Has a function of resetting the CPU 20 in response to a request from the user.

FIG. 6 shows the bus interface 54 of FIG.
FIG. 2 is a diagram illustrating a detailed circuit configuration in FIG. In FIG. 6, the bus interface 54 includes the same extended bus signal processing circuit 30 and bus selector 3 as in the first embodiment.
2, reset sequence circuit 34, I / O port 36,
In addition to the reset sequence circuit 34, the bus switching control circuit 56 for switching the bus 40 connected to the ROM 22 and the CPU 20
The I / O port 60 notifies the end of the transfer of the contents of the program 2 to the RAM 52, which is an execution memory, and the I / O port 58, which allows the host system 10 to confirm the write permission to the ROM 22. In FIG. 6,
The same components as those in the first embodiment are denoted by the same reference numerals, and the description of the configuration will be omitted.

FIG. 7 shows a flash RO according to the second embodiment.
It is a flowchart explaining the flow of the program rewriting process in M22. First, when the power is turned on, the bus 40 to the flash ROM 22 is switched to the CPU 20 side, and the CPU 20 performs an initial process (step S600). That is, the CPU 20 transfers the contents of the program in the flash ROM 22 to the RAM 104, which is an execution memory (step S602). Then, after transferring the program contents to the RAM 52, the CPU 20 notifies the bus interface 54 of the completion of the transfer by setting the I / O port 60 (step S606), and the program is executed (step S610). .

When the above-described program transfer end notification is sent to the bus interface 54 (step S50).
0), the bus switching control circuit 5 of the bus interface 54
6, the flash ROM is selected by the bus select signal 62.
The bus 40 to the I / O port 5 is switched so that the bus 40 to the I / O port 22 becomes effective on the host system 10 side (step S502).
By setting “8”, R is set on the host system 10 side.
Notification of OM rewriting permission is given (step S504).
The switching of the bus 40 to the flash ROM 22 ends (step S506).

When the host system 10 needs to rewrite the flash ROM 22, the host system 10 accesses the I / O port 58 of the bus switching control circuit 56 of the bus interface 54 to rewrite the flash ROM 22. It is determined whether or not is permitted (step S400). If rewriting is not permitted, confirmation is repeated and waiting until rewriting is permitted. If the rewriting of the ROM is permitted, the host system 10 accesses the flash ROM 22 by writing, reading, comparing, etc., and rewrites the contents of the flash ROM 22 (step S40).
2). During that time, the CPU 20 can continue the operation while referring to the program in the RAM 52 without being affected by the rewriting operation of the ROM 22 at all.

The host system 10 has a flash ROM
22 is rewritten, the I / O port 36 is set, and the CPU 20
Is requested (step S404), and the ROM rewriting process ends (step S406). The bus interface 54 generates an interrupt to the CPU 20 upon receiving a reset request to the CPU 20,
A reset notification is sent to the CPU 20 (step S51).
2).

When the CPU 20 detects a reset notification interrupt (step S620), it interrupts the process currently being executed (step S622), and sets a state where data inconsistency does not occur even if a reset is applied.
The I / O port 38 is set, and the reset permission is notified to the bus interface 54 (step S62).
4).

The bus interface 54 accesses the I / O port 38 to confirm whether or not reset is permitted, and if not, waits until reset is permitted (step S514). Here, the CPU 20
From the reset sequence circuit 3
4 is notified of reset permission. When reset permission is detected in the reset sequence circuit 34, C
The reset is generated / released for the PU 20 (step S516), and the reset process of the CPU 20 is completed (step S518). Although the operation of the CPU 20 is temporarily stopped by the reset, it is immediately canceled, the updated content of the flash ROM 22 is transferred to the RAM 52 again, and the operation is started based on the rewritten program.

Further, similarly to the first embodiment, C
It is of course possible to rewrite the contents of the flash ROM 22 by resetting the PU 20 to set the operation stop state (step S630).

FIG. 8 is a comparison between the configuration of the second embodiment shown in FIG. 5 and the configuration of the conventional example shown in FIG. The transfer control circuit, the ROM, the bank memory circuit, the bank switching circuit, and the like indicated by the dotted lines in FIG. 5 are necessary in the conventional system, but are unnecessary in the first embodiment. Is simplified, and the program rewriting operation can be performed with simple software.

As described above, according to the second embodiment, the power supply and the like do not need to be turned off when rewriting the program of the extension unit. Therefore, the operation of the host system and the connection to the extension bus of the host system are not required. It no longer affects the operation of other expansion units.

The rewriting of the program in the extension unit can be done by simple software and hardware. Further, when the program is operated with the updated content, the extension unit is only stopped for a few milliseconds at which a reset occurs, and the stop time can be further reduced.

[0059]

As described above, according to the program rewriting system of the present invention, the program contents of the extension unit can be stored without affecting the operation of the host system and other extension units connected to the extension bus. Rewriting can be easily performed, and the time for stopping the host system or the extension unit can be reduced.

According to the program rewriting system of the next invention, the contents of the non-volatile memory can be easily rewritten without affecting the operation of the host system and other extension units. The time to stop can be reduced.

According to the program rewriting system of the next invention, the operation of the host system, the other extension units connected to the extension bus, and the extension unit that rewrites the program is not affected. The contents of the program can be easily rewritten, and the time for stopping the host system and the extension unit can be reduced.

According to the program rewriting system of the next invention, the contents of the nonvolatile memory can be easily rewritten without affecting the operations of the host system, other extension units, and the extension units which rewrite the program. Therefore, the time for stopping the host system and the extension unit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a program rewriting system for an extension unit according to a first embodiment.

FIG. 2 is a diagram illustrating a detailed circuit configuration in a bus interface of FIG. 1;

FIG. 3 is a flowchart illustrating a flow of a flash ROM program rewriting process according to the first embodiment;

FIG. 4 shows the configuration of the first embodiment shown in FIG. 1 and FIG.
3 is compared with the configuration of the conventional example shown in FIG.

FIG. 5 is a diagram illustrating a program rewriting system for an extension unit according to the second embodiment.

FIG. 6 is a diagram illustrating a detailed circuit configuration in the bus interface of FIG. 5;

FIG. 7 is a flowchart illustrating the flow of a flash ROM program rewriting process according to the second embodiment;

8 shows the configuration of the second embodiment shown in FIG. 5 and FIG.
3 is compared with the configuration of the conventional example shown in FIG.

FIG. 9 is a conventional system configuration diagram in which a plurality of extension units are connected to a host system.

FIG. 10 is a system configuration diagram in a case where an external device is connected to the extension unit to rewrite a memory content of a ROM inside the extension unit.

FIG. 11 is a block diagram illustrating a configuration of a conventional download device.

FIG. 12 is a diagram showing an address space arrangement in the download device of FIG. 11;

[Explanation of symbols]

10 host system, 12 expansion bus, 14, 16
Extension unit, 20 CPU, 22 ROM (flash ROM), 24 bus interface, 30 extension bus signal processing circuit, 32 bus selector, 34 reset sequence circuit, 36, 38 I / O port, 40 bus, 50 extension unit, 52 RAM, 54 bus interface, 56 bus switching control circuit, 58, 60
I / O port.

Claims (4)

[Claims] 1. A program rewriting system for rewriting a program stored in an extension unit connected to a host system via an extension bus, wherein the extension unit includes: a CPU controlling the inside of the extension unit; A rewritable nonvolatile memory for storing a program to be executed by the CPU; and an interface circuit capable of accessing the nonvolatile memory from the host system and outputting a reset from the host system to the CPU. And a program rewriting system for directly accessing the non-volatile memory while the host system keeps the CPU in an operation stopped state and rewriting a program content stored in the non-volatile memory. A signal processing circuit for generating an interrupt to the host system by an interrupt signal; a reset sequence circuit for stopping the CPU based on a request from the host system; A bus selector that switches a bus connected to the nonvolatile memory to one of the host system and the CPU according to a select signal from a reset sequence circuit, wherein the host system controls the CPU by the reset sequence circuit. 2. The program according to claim 1, wherein the operation is stopped, and a bus connected to the non-volatile memory by the bus selector is connected to a host system to rewrite a program stored in the non-volatile memory. Program rewriting system. 3. A program rewriting system for rewriting a program stored in an expansion unit connected to a host system via an expansion bus, wherein the expansion unit includes: a CPU controlling the inside of the expansion unit; A rewritable nonvolatile memory for storing a program to be executed by the CPU; an execution memory for transferring and executing program contents stored in the nonvolatile memory when the unit body is operating; An interface circuit for accessing the non-volatile memory and capable of outputting a reset from the host system to the CPU; and wherein the host system directly accesses the non-volatile memory and is stored in the non-volatile memory. The feature is that the contents of the program Program rewrite system that. A signal processing circuit for generating an interrupt to the host system by an interrupt signal; a reset sequence circuit for stopping the CPU based on a request from the host system; A bus selector for switching a bus connected to the nonvolatile memory to one of the host system and the CPU, and a bus switching control circuit for performing switching control of the bus selector. After the transfer of the program to the execution memory is completed, a bus selector is switched by the bus switching control circuit to connect the bus connected to the nonvolatile memory to the host system, and the contents of the program stored in the nonvolatile memory are transferred. 4. The program rewriting system according to claim 3, wherein the program rewriting is performed. Temu.