JPH09232316A - Intermediate metal dielectric layer flattening method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a dielectric layer having a uniform thickness with which an air gap between patterns of a metal conducting layer is completely filled, on a dielectric layer bottom layer, by depositing an intermediate metal dielectric bottom layer by a plasma enhanced chemical vapor deposition method. SOLUTION: On a silicon semiconductor substrate 10, an insulating layer 20 is formed, on which a metal conducting layer pattern 30 is formed by photoresist or plasma etching. On the insulating layer 20 and the metal conducting layer pattern 30, reaction material of tetraethoxysilane with ozone is deposited by a plasma enhanced chemical vapor deposition method, and a dielectric layer bottom layer 40 is formed. In this case, the deposition efficiency is made about 100 watt. On the dielectric layer bottom layer 40, a dielectric layer 50 of silicon dioxide having fluidity of tetraethoxysilane with oxone is formed by a thermal decomposition chemical vapor deposition method. Thereby a dielectric layer having a uniform thickness with which gaps between patterns of the metal conducting layer are completely filled can be formed on the dielectric bottom layer, so that intermediate metal dielectric layer flattening effect can be excellently achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terrain with undulations (SeverTopo) during a manufacturing process of a very large scale integrated circuit.
and a method of forming a planarization dielectric layer on the
In particular, plasma enhanced chemical vapor deposition (PECVD: P
lasma-Enhanced Chemical V
aor Deposition) Tetraethoxysilane (TEOS: Tetraethoxysilane)
s), displaying the deposit as a PE-TEOS dielectric bottom layer, and utilizing its different deposition conditions, an inter-metal-dielectric layer (inter-metal-dielectric).
c) Relating to achieving the purpose of flattening.

[0002]

2. Description of the Related Art Due to high integration of integrated circuits, multi-level metallization
n) During the integrated circuit manufacturing process, the uneven topography was easily formed by the alternate deposition and etching of the multilayer metal and the insulating layer. In particular, stack DRAM (Stack DRA)
M) In the manufacturing process, high and low stepped terrains are likely to be formed as a result of the alternating deposition and etching of the four layers of polysilicon required for manufacturing the capacitor, and this rugged terrain has a bad influence on the subsequent manufacturing process. It is easy to give, in which the filtered image is too deep and the photoresist image is distorted,
Alternatively, the adverse effect of short-circuiting the metal wire due to the generation of etching residue is the most serious.

At present, a technique for leveling uneven terrain is bias sputtered silicon dioxide (Bias).
Sputted Silicon Dioxide)
And silicon dioxide flow (Flow), both planarization methods are time consuming and costly. Separately, as a flattening method with a simple manufacturing process and low cost, a spin coating glass film flattening method [SOG (S
pin-On-Glass) planarizati
on Process]. An intermediate dielectric layer between two traditional metal layers (intermediate metal dielectric layer: IMD: inter).
-Inetal-dielectric) planarization method is that PE-TEOS is first deposited on a metal layer to form a dielectric layer underlayer, and PE-TEOS is used.
To display the bottom layer of the dielectric layer and further deposit a reactant of tetraethoxysilane (O ₃ / TEOS) with ozone to form one silicon dioxide dielectric layer, followed by
Further, by using the SOG planarization method, the intermediate metal dielectric layer (I
MD) The purpose of flattening was achieved. See US Pat. No. 5,393,708).

The key points of the conventional IMD planarization process are: 1. First, a dielectric layer pattern is prepared. 2. One PE-TEOS on the dielectric layer
Deposit the bottom layer of the dielectric layer. 3. On top of the PE-TEOS dielectric bottom layer, further O ₃ / TEOS reactant is deposited to form a silicon dioxide dielectric layer to achieve the planarization purpose. However,
Since the surface of the O ₃ / TEOS reactant has an extremely high sensitivity, when the O ₃ / TEOS reactant is deposited on the PE-TEOS dielectric bottom layer, the material of the PE-TEOS dielectric bottom layer and the concentration of its carrier are used. Sensitive O due to factors such as
_The interaction between the surface of the ₃ / TEOS reactant and the material of the bottom layer of the PE-TEOS dielectric layer may affect the thickness of the deposited dielectric layer, resulting in a phenomenon in which the thickness of the dielectric layer becomes uneven. In addition, the gap between the patterns on the chip before cutting has a large difference in the distribution of the ratio value with respect to the width of its height. Further, due to the problem of the surface sensitivity of the O ₃ / TEOS reactant, O ₃ / The TEOS reactant deposited silicon dioxide dielectric layer was not completely embedded in the intermetallic voids, and the IM
D caused a flattening effect failure. FIG. 1 illustrates a conventional intermediate metal dielectric layer (IMD).
(lectric) A flattening method is shown. It comprises a conductive layer pattern 1, a dielectric bottom layer 2, a dielectric layer 3 formed by deposition of O ₃ / TEOS reactant. In this method, voids 4 not filled with the dielectric layer between the two metal patterns, and non-uniform film thicknesses 5 and 6 of the dielectric layer were likely to occur. In the method, first, one dielectric layer bottom layer 2 is formed on a metal conductive layer 1, and a reactant is further deposited on the dielectric layer bottom layer 2 to form a dielectric layer 3 (generally a flow layer) of an O ₃ / TEOS reactant. Silicon dioxide having a property is formed), and the purpose of planarization is achieved. However, since the surface sensitivity of the O ₃ / TEOS reaction deposit is extremely high, the dielectric layer 3 becomes the bottom layer of the dielectric layer 2.
When deposited on top, the difference in the material used for the bottom layer 2 of the dielectric layer and its carrier concentration leads to non-uniformity of the film thickness 5, 6 of the dielectric layer 3 with the O ₃ / TEOS reactant deposited. Furthermore, if there is a large difference in the distribution of the height to width ratio of the voids between the conductive layer patterns on the circular chip, then O ₃ / T
The dielectric layer 3 on which the EOS reactant is deposited cannot completely fill the voids between the metals, and voids 4 are likely to remain between the dielectric layer 3 and the bottom layer 2 of the dielectric layer. That is, this conventional technique is
A sufficient effect could not be exhibited for D flattening.

[0005]

SUMMARY OF THE INVENTION The present invention provides an intermediate metal dielectric layer (IMD: inter-m) in the prior art described above.
a kind of new dielectric bottom layer that solves the problem of poor planarization effect.
providing a simple manufacturing process of the dielectric bottom layer, that is, in its key point step, the deposition conditions of the dielectric bottom layer are changed, and thereby the dielectric bottom layer and the O ₃ / TEO
It is an object to solve the problem that occurs during the interaction of the sensitive surface of the dielectric layer due to the deposition of the S reactant and achieve a good IMD planarization effect.

[0006]

According to a first aspect of the present invention, there is provided a method of forming a planarization dielectric layer on a semiconductor substrate having a kind of an intermediate-metal conductive layer pattern. A semiconductor device and a metal conductive layer pattern are formed on the substrate, and then one intermediate metal dielectric layer (IM
D: inter-metal-dielectric)
A bottom layer is formed on the metal conductive layer pattern described above and on other areas of the semiconductor substrate described above, wherein the middle metal dielectric layer bottom layer is formed by plasma enhanced chemical vapor deposition (PECVD: Pl).
asma-Enhanced Chemical Va
Por Deposition), the reactant is ozone tetraethoxysilane (TEOS: T).
and the deposition is represented by PE-TEOS, and the deposition efficiency is about 100 watts and the PE-TEOS dielectric layer bottom layer (underlayer).
r) is completed to complete the manufacture of the intermediate metal dielectric bottom layer, and then a silicon oxide dielectric layer having fluidity with tetraethoxysilane with ozone is further formed on the intermediate metal dielectric bottom layer. It is characterized in that it is formed and completely fills the voids between the above-mentioned metal conductive layer patterns to make the thickness of the intermediate metal dielectric layer uniform and to have an excellent flattening effect on the intermediate metal dielectric layer.

According to the second aspect of the present invention, during the manufacturing process and conditions of the bottom layer of the intermediate metal dielectric layer, PE is deposited with a high efficiency of about 400 to 900 watts and then with a low efficiency of about 100 watts.
-Depositing the TEOS dielectric bottom layer.

According to the third aspect of the present invention, the deposition thickness of the intermediate metal dielectric layer bottom layer is between 1000 angstroms and 3000 angstroms.

In the invention of claim 4, the silicon dioxide dielectric layer deposited by the reactant tetraethoxysilane and ozone is pyrolyzed by chemical vapor deposition (THCVD).
icChemical Vapor Depositi
on) and its thickness is 3000 to 10000
It is between Angstroms.

According to the invention of claim 5, P which is deposited with high efficiency
The E-TEOS dielectric bottom layer thickness is between 1000 and 2000 angstroms, and the PE-TEOS dielectric bottom layer thickness is about 500 watts with a low efficiency deposition of about 100 watts.
It is set between 2000 angstroms.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The intermediate metal dielectric layer planarization method provided by the present invention includes the following steps. 1. An insulating layer is formed on a silicon semiconductor substrate, a metal conductive layer is subsequently formed, and a metal conductive pattern is formed by a well-known lithography technique and plasma etching technique. 2. Plasma enhanced chemical vapor deposition (P
ECVD: Plasma-Enhanced Chem
The IMD planarization effect is increased by using a method of depositing a bottom layer of a dielectric layer having different efficiencies by using an ionic vapor deposition method. 3. Pyrolysis chemical vapor deposition (THCVD)
tic Chemical Vapor Deposi
reaction is used to deposit an O ₃ / TEOS reactant on the bottom of the dielectric layer to form a dielectric layer (generally fluid silicon dioxide is formed) to achieve the IMD planarization effect.

The method of the present invention solves the problem of poor IMD planarization effect caused by the factor of the surface sensitivity of the O ₃ / TEOS reactant, resulting in a very uniform and perfectly uniform thickness on the bottom layer of the dielectric layer. A good IMD planarization effect can be obtained by forming another dielectric layer that fills the gap between the patterns of the metal conductive layer.

The intermediate metal dielectric layer planarization method of the present invention selectively utilizes the technique of depositing a bottom layer of a dielectric layer to achieve the purpose of planarizing a dielectric layer on a metal conductive layer pattern, and In that embodiment, it is applied to a slightly single layer of metal conductive layer, however, as will be readily appreciated by those familiar with integrated circuits, the method disclosed in the present invention is a multi-layer metal interconnect integrated circuit. It is also used in the formation of multiple planarized dielectric layers.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Illustrated in FIG. 2 is an intermediate metal dielectric layer planarization method of the present invention, which comprises a silicon semiconductor substrate 1
0, the insulating layer 20, the metal conductive layer pattern 30, the dielectric bottom layer 40, and the O ₃ / TEOS reactant-deposited dielectric layer 50.
Inclusive. In the manufacturing process, first, one insulating layer 20 is formed on the silicon semiconductor substrate 10, and then one metal conductive layer is further formed on the insulating layer 20, and the conventional photoresist or plasma etching is used to perform the above-mentioned process. The metal conductive layer pattern 30 is formed (FIG. 2). Then, as shown in FIG. 3, plasma enhanced chemical vapor deposition (PECVD) is formed on the metal conductive layer.
ed Chemical Vapor Depositi
ON), PE-TEOS dielectric layer bottom layer (under)
layer 40 to the metal conductive layer pattern 30 and the insulating layer 2
Form on 0. PE-TEOS by this PECVD
The conditions for forming the dielectric layer bottom layer 40 of (Plazma Enhanced TEOS) are as follows. 1. The reaction substance is tetraethoxysilane in oxygen gas (O ₂ + TEOS: tetraethoxysil).
anes), the vacuum condition of the reaction is about 8 to 10 Tor
r, reaction temperature is about 380 ° C. to 400 ° C., deposition efficiency is about 100 watts, deposition rate is about 4285 Å / min) Deposition thickness is about 1000 Å to 3000 Å, that is, PE-TEOS dielectric is used for low-efficiency deposition. The bottom layer 40 is formed. 2. The reaction material was tetraethoxysilane in oxygen gas, and (O ₂ + TEOS: tetraethoxysi)
lanes), the vacuum condition of the reaction is approximately 8 to 10 Tor
r) Reaction temperature is about 380 ° C to 400 ° C, deposition efficiency is about 400 to 900 watts, deposition rate is about 4285 angstrom / minN deposition thickness is about 500 to 200.
The PE-TEOS dielectric bottom layer 40 is formed with a thickness of about 0 Å, that is, with high efficiency and then with low efficiency.

The PE-TEOS dielectric bottom layer bottom layer 40 manufactured by one of the above-described two manufacturing process methods is the surface sensitivity of the dielectric layer 50 on which the O ₃ / TEOS reactant is deposited. Effectively improve.

As shown in FIG. 4, after the dielectric layer bottom layer 40 completed by using one of the above two methods is deposited,
In addition, a thermal decomposition chemical vapor deposition (THCVD) method is used to deposit the O ₃ / TEOS reactant, and a dielectric layer 50 of silicon dioxide having fluidity is provided.
In this way, the IMD flattening action is achieved. Among them, the reactant is tetraethoxysilane (TEOS: Tetraethoxysila) with ozone.
and the vacuum condition of the reaction is about 200 to 760
Torr, the reaction temperature is about 380 ° C. to 440 ° C., and the deposited film thickness is about 3000 to 10000 Å.

The IMD flattening operation is completed by the three steps shown in FIGS.
Is a key point step. Utilizing the manufacturing method of the present invention, the planarization effect of the dielectric layer is further perfected.

[0018]

INDUSTRIAL APPLICABILITY The method of the present invention not only solves the surface sensitivity factor of the O ₃ / TEOS reactant, but also solves the problem of IMD flattening effect caused thereby, and the thermal decomposition chemistry. In a vapor deposition method, tetraethoxysilane (TEOS) and ozone gas are used to deposit a reactant on another dielectric layer on the bottom layer of the dielectric layer, the dielectric layer having a very uniform thickness and completely formed. Since it fills the voids between the metal conductive layer patterns described above, it achieves a good IMD flattening effect, and is superior in terms of low manufacturing cost required for product competition, ease of manufacturing, and product excellence. Show.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a conventional IMD flattening method.

FIG. 2 is a cross-sectional view showing a process in the IMD flattening method of the present invention.

FIG. 3 is a cross-sectional view showing a process in the IMD flattening method of the present invention subsequent to FIG.

FIG. 4 is a cross-sectional view showing a process in the IMD planarization method of the present invention subsequent to FIG.

[Explanation of symbols]

1 ... Conductive layer pattern 2 ... Dielectric layer bottom layer 3 ...
-Dielectric layer 4 ... Voids 5, 6 ... Film thickness 10 ... Silicon semiconductor substrate 20 ... Insulating layer 30 ... Metal conductive layer pattern 4
0 ... Dielectric layer bottom layer 50 ... Dielectric layer

Claims (5)

[Claims] 1. A kind of inter-meta
l) A method of forming a planarization dielectric layer on a semiconductor substrate having a conductive layer pattern, in which a semiconductor device and a metal conductive layer pattern are formed on one semiconductor substrate, and then one intermediate metal dielectric layer (IMD: i
An inter-metal-dielectric) bottom layer is formed on the metal conductive layer pattern described above and on other areas of the semiconductor substrate described above, wherein the middle metal dielectric layer bottom layer is formed by plasma enhanced chemical vapor deposition (PECVD).
-Enhanced Chemical Vapor
Depositron), whose reactant is ozone tetraethoxysilane (TEOS: Tetra).
Ethoxysilanes) and the deposit is PE-T
Displayed by EOS, the deposition efficiency is about 100 watts and PE
-Completion of the TEOS dielectric layer underlayer deposition to complete the manufacture of the intermediate metal dielectric layer bottom layer, and then on the intermediate metal dielectric layer bottom layer, with a flowability of tetraethoxysilane with further ozone. Forming two silicon oxide dielectric layers, completely filling the voids between the metal conductive layer patterns described above, making the thickness of the intermediate metal dielectric layer uniform, and providing an excellent intermediate metal dielectric layer flattening effect. Method for planarizing a dielectric layer. 2. The PE-TEOS dielectric bottom layer is deposited at a high efficiency of about 400-900 Watts and then at a low efficiency of about 100 Watts during the manufacturing process and conditions of the intermediate metal dielectric bottom layer. A method of planarizing an intermediate metal dielectric layer according to claim 1. 3. The intermediate metal dielectric layer bottom layer has a deposited thickness of 100.
The method for planarizing an intermediate metal dielectric layer according to claim 1 or 2, wherein the thickness is between 0 Å and 3000 Å. 4. The silicon dioxide dielectric layer deposited with the reactants tetraethoxysilane and ozone is pyrolysis chemical vapor deposition (THCVD).
3. A method of planarizing an intermediate metal dielectric layer according to claim 1 or claim 2, wherein the intermediate metal dielectric layer is deposited by Al Vapor Deposition) and its thickness is between 3000 and 10000 angstroms. 5. A highly efficient PE-TEOS dielectric bottom layer having a thickness between 1000 and 2000 angstroms, and a low efficient PE-TEOS deposition rate of about 100 watts.
The method of claim 2, wherein the TEOS dielectric bottom layer has a thickness between 500 and 2000 angstroms.