CN1049764C

CN1049764C - Method for making dielectric layer of integrated circuit

Info

Publication number: CN1049764C
Application number: CN96101197A
Authority: CN
Inventors: 陈光钊; 涂玉堂
Original assignee: Promos Technologies Inc
Current assignee: Maode Science and Technology Co., Ltd.
Priority date: 1996-02-14
Filing date: 1996-02-14
Publication date: 2000-02-23
Anticipated expiration: 2016-02-14
Also published as: CN1157483A

Abstract

The present invention relates to a manufacturing method of a dielectric layer in an integrated circuit. The method comprises the following main steps: firstly, depositing a metal conducting layer, and making patterns of the metal conducting layer by using an active ion type plasma etching technology to cause the patterns of the metal conducting layer to be in electric contact with a semiconductor element; then, depositing a dielectric layer by using a plasma enhancement type chemical deposition method to be used as a bottom layer of the dielectric layer; finally, depositing another dielectric layer on the bottom layer of the dielectric layer by using tetraethyl orthosilicate and ozone through a thermolysis chemical vapor deposition method. The thickness of the dielectric layer is uniform, and the dielectric layer can completely fill up gaps among the patterns of the metal conducting layer to achieve the effect of flatness.

Description

The manufacture method of dielectric layer in the integrated circuit

The present invention relates to the manufacture method of dielectric layer in a kind of integrated circuit, it is a kind of method that makes up-and-down (Severe Topography) dielectric layer flatening, particularly relevant for depositing tetraethoxysilane (TEOS with plasma enhanced chemical vapor deposition method (PECVD); Tetraethoxysilanes), its deposit is represented it with PE-TEOS dielectric layer bottom, utilizes its different sedimentary conditions, reaches the purpose of dielectric layer (inter-metal-dielectric) planarization of metal interlevel.

Because integrated circuit height is integrated, make in having the manufacturing of multiple layer metal (Multi-Level Metallization) integrated circuit, because the mutual deposition of multiple layer metal and insulating barrier, etching, easily form the out-of-flatness surface, particularly in stack dynamic random access memory (Stack DRAM) is made, make capacitor institute must four layers of polysilicon (Polysilicon) deposit alternately, etched result, easily form towering ladder physical features, because these uneven landform can cause image fault to successive process, or the generation etch residue, and make metal line bridging.

At present, the dielectric layer technology that solves the surface undulation injustice has bias voltage sputtering type silicon dioxide (Bias Sputtered Silicon Dioxide) and flowable silicon dioxide, this two planarization is consuming time and cost is high, and the planarization that another kind of processing procedure is simple and easy and cost is low is spin cloth of coating-type glass-film planarization [(SOG; Spin-On-Glass) planarization Process]; The planarization manufacturing technology of the dielectric layer in the conventional art in the middle of two metal levels, generally be that deposition PE-TEOS becomes the dielectric layer bottom on metal level earlier, represent it with PE-TEOS dielectric layer bottom, then, on it again deposition reactant be a tetraethoxysilane (O with ozone gas ₃/ TEOS),, next, re-use the SOG planarization to form silicon dioxide dielectric layers, reach the purpose of intermediate dielectric layer IMD planarization, see also people's such as Hsia United States Patent (USP) (patent number: 5,393,708).

The committed step of conventional I MD planarization processing procedure is as follows: (1) is ready to conductive layer pattern earlier; (2) deposition one PE-TEOS dielectric layer bottom on conductive layer; (3) on PE-TEOS dielectric layer bottom, deposit O again ₃/ TEOS to form silicon dioxide dielectric layers, reaches the planarization purpose; But because O ₃/ TEOS surface has the extremely strong responsive end, so as deposition O ₃/ TEOS is on PE-TEOS dielectric layer bottom the time, can be because of factors such as the material of PE-TEOS dielectric layer bottom and its carrier concentrations, make the O of sensitivity ₃/ TEOS surface has influence on the medium thickness that is deposited with the reciprocation of PE-TEOS material, and produce the uneven phenomenon of medium thickness, and in addition, the space between the conductive layer pattern on the script wafer, it highly is distributed with great difference to the ratio of width, adds O ₃Problems such as the surface-sensitive degree of/TEOS easily make by O ₃/ TEOS deposits the silicon dioxide dielectric layers that forms and can't insert fully in the intermetallic space, makes IMD planarization poor effect.

In order to improve the shortcoming of conventional I MD planarization, the present invention has disclosed the metal intermetallic dielectric layer planarization, is meant the manufacture of different dielectric layer bottom (underlayer) especially, in order to solve from O ₃The surface-sensitive degree factor of/TEOS and the problems such as IMD planarization poor effect that cause, when increasing the commodity competition desired cost of manufacture low, make simplification and commodity than advantages such as dominance.

Because the shortcomings such as intermetallic metal dielectric layer flatening poor effect of above-mentioned located by prior art, the present invention proposes a kind of processing procedure mode of new dielectric layer bottom (underlayer), overcome O ₃Problems such as the extremely strong caused IMD planarization of surface-sensitive degree of/TEOS is not good, its manufacturing method thereof is very simple, and its committed step is exactly the sedimentary condition that changes the dielectric layer bottom, improves dielectric bottom and O with this ₃The problem that the sensing surface reciprocation of the dielectric layer that/TEOS deposited is produced is to reach better IMD planarization effect.

Main purpose of the present invention is to provide a kind of method of improving the metal intermetallic dielectric layer planarization, and for achieving the above object, the present invention takes following measure:

Method of the present invention, its step comprises: (1) forms a layer insulating on silicon semiconductor substrate, then, forms the layer of metal conductive layer, and utilizes conventional lithographic techniques and plasma etching technology to formulate described metallic conduction layer pattern; (2) on metal conducting layer with plasma enhanced chemical deposition (PECVD; Plasma-Enhanced Chemical VaporDeposition) increases the planarization effect of favourable IMD in different capacity dielectric layer bottom mode; (3) utilize pyrolysis chemical vapour deposition technique (THCVD; Pyrolytic Chemical Vapor Deposition) deposition reactant is O on the dielectric layer bottom ₃The dielectric layer of/TEOS (generally being the silicon dioxide that is formed with flowable matter).

In conjunction with the embodiments 1 and description of drawings characteristics of the present invention as follows:

Brief Description Of Drawings:

Fig. 1 is a cross sectional representation of commonly using the metal intermetallic dielectric layer planarization.

Fig. 2 is the cross sectional representation of embodiment of the invention metal intermetallic dielectric layer planarization.

The disclosed metal intermetallic dielectric layer flattening method of the present invention, be to utilize optionally dielectric layer bottom technology, to reach the dielectric layer purpose on the planar metal conductive layer pattern, though embodiment only is applied to the single-layer metal conductive layer, but the personage who is familiar with integrated circuit skill all can think easily and, the disclosed method of the present invention also can be extended and is applied to the integrated circuit with multiple layer metal, to form the smooth dielectric layer of multilayer.

Please refer to Fig. 1, the diagram of dielectric layer flatening technology between conventional metals, wherein conductive layer pattern 1, dielectric layer bottom 2, by reactant O ₃The dielectric layer 3 that/TEOS deposited wherein easily produces dielectric layer and fails to insert the inhomogeneous thickness 5 of space 4, dielectric layer and 6 etc. between two metal patterns; Its manufacturing step comprises: at first, deposition one dielectric layer bottom 2 on metal conducting layer 1, deposition reactant is O again ₃The dielectric layer 3 of/TEOS (generally be form with flowable matter silicon dioxide) is on dielectric layer bottom 2, reaching the planarization purpose, but because deposition reactant O ₃Therefore the surface-sensitive degree of/TEOS is high, and when dielectric layer 3 is deposited on the dielectric layer bottom 2, regular meeting has influence on by O because of the difference of used material of dielectric layer bottom 2 and carrier concentration thereof ₃Dielectric layer 3 film thicknesses 5 or 6 that/TEOS deposited are inhomogeneous; Further, if it is big to the ratio distributional difference of width to add on the crystal between the conductive layer pattern space height, be easy to form by O ₃The dielectric layer 3 that/TEOS deposited can't be inserted intermetallic space fully and have space 4 to exist in the middle of forming dielectric layer 3 and electricity layer bottom 2, and unfavorable IMD's is smooth.

Please refer to Fig. 2, it is a metal intermetallic dielectric layer of the present invention) diagram of planarization, its manufacture process comprises: at first, on silicon semiconductor substrate 10, form a layer insulating 20, then, on insulating barrier 20, form a metal conducting layer again, and utilize conventional lithographic techniques and plasma etch techniques to make described metallic conduction layer pattern 30, shown in Fig. 2 A; Next see also Fig. 2 B, on metal conducting layer, form PE-TEOS dielectric layer bottom with plasma enhanced chemical deposition (PECVD) deposition) 40, on metallic conduction layer pattern 30 and insulating barrier 20, the condition of PE-TEOS (Plasma Enhanced TEOS) the dielectric layer bottom 40 that its PECVD deposition forms is as follows:

(1) its reactive material is that oxygen adds tetraethoxysilane (O ₂+ TEOS; Tetraethoxysilanes), the vacuum condition of reaction is greatly about 8 to 10Torr, reaction temperature is about about 380 ℃ to 400 ℃, deposition power is about about 100 watts (W), the about 4285A/min of deposition rate, deposit thickness is about 1000 dust to the 3000 Izod right sides, that is, and and with the PE-TEOS dielectric layer bottom 40 of low-power deposition formation; Or

(2) its reactive material is that oxygen adds tetraethoxysilane (O ₂+ TEOS; Tetraethoxysilanes), about 8 to 10Torr, reaction temperature is about about 380 ℃ to 400 ℃ the vacuum condition of reaction greatly, and deposition power is about about the 400-900 watt, and deposition rate is about 7500A/min, and deposit thickness is about the 1000-2000 Izod right side; Next, be about low-power dielectric layer bottom 40 about 100 watts, the about 4285A/min of its deposition rate, the dielectric layer bottom 40 on the about 500-2000 Izod of the deposit thickness right side with deposition power again, that is the PE-TEOS dielectric layer bottom 40 that forms with the low-power deposition again with high power earlier;

By the PE-TEOS dielectric layer bottom 40 that one of above two kinds of processing procedure modes are made, all can effectively improve and deposition reactant to be (O ₂/ TEOS) the surface-sensitive of the dielectric layer 50 on its dielectric layer bottom 40;

Please refer to Fig. 2 C, utilize one of above method, finish the deposition of dielectric layer bottom 40 after, next step utilizes pyrolysis chemical vapour deposition technique (THCVD) deposition (O again ₃/ TEOS has silicon dioxide (silicon oxide) dielectric substance layer 50 of flowable with formation, to reach IMD planarization effect; Wherein reactive material is with ozone O ₃Tetraethoxysilane (the TEOS of gas; Tetraethoxysilanes), the vacuum condition of reaction is about 200 to 760 Torr, and reaction temperature is about 380 ℃ to 440 ℃, and the deposition thickness is about 3000 to the 10000 Izod right sides.

By above Fig. 2 A, 2B and 2C three steps, promptly finish the dielectric layer flatening effect, wherein Fig. 2 B is key step, utilizes manufacture method of the present invention, can make that the planarization effect of dielectric layer is more complete.

Claims

1, the manufacture method of dielectric layer in a kind of integrated circuit may further comprise the steps:

On a Semiconductor substrate, form semiconductor element and metallic conduction layer pattern;

Then, on the metallic conduction layer pattern, form a dielectric layer bottom with other zone of Semiconductor substrate;

The dielectric layer bottom create conditions and step as follows:

Utilize plasma enhanced chemical vapor deposition method, its reactive material is that oxygen adds tetraethoxysilane, deposition PE-TEOS dielectric layer bottom;

On the dielectric layer bottom, deposit one again and form the silicon dioxide dielectric layers of flowable with the TEOS of ozone, by pyrolysis chemical vapour deposition technique deposition, fill up the space between described metallic conduction layer pattern fully;

It is characterized in that: in deposition PE-TEOS dielectric layer bottom step, utilize first power to carry out the PE-TEOS deposition earlier after, carry out the PE-TEOS deposition of second power again, first power is higher than second power; Behind two kinds of power deposition PE-TEOS dielectric layers, just finish the making of dielectric layer bottom.

2, method according to claim 1 is characterized in that, in described deposition PE-TEOS dielectric layer bottom step, first power is between 400～900 watts.

3, method according to claim 1 is characterized in that, in described deposition PE-TEOS dielectric layer bottom step, second power is about 100 watts.

4, method according to claim 1 is characterized in that, in described deposition PE-TEOS dielectric layer bottom step, the deposit thickness of dielectric layer bottom is between 1000 dusts～3000 dusts.

5, method according to claim 1 and 2 is characterized in that, forms by reactant TEOS and O at the described pyrolysis chemical vapour deposition technique that utilizes ₃In the silicon dioxide dielectric layers step of deposition, its vacuum condition is between 200～760Torr.

6, method according to claim 1 and 2 is characterized in that, in the silicon dioxide dielectric layers step of described deposition, the thickness of silicon dioxide dielectric layers is between 1000 dusts～3000 dusts.

7, according to claim 1 or 2 or 3 described methods, it is characterized in that, the described utilization in the first power deposition PE-TEOS dielectric layer bottom step, the thickness of the sedimentary deposit that forms with first power is between 1000 dusts～2000 dusts, with the second power deposition PE-TEOS dielectric layer bottom, thickness is between 500 dusts～2000 dusts again.