KR100253355B1 - Method for fabricating contact of semiconductor device - Google Patents

Method for fabricating contact of semiconductor device Download PDF

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Publication number
KR100253355B1
KR100253355B1 KR1019970061758A KR19970061758A KR100253355B1 KR 100253355 B1 KR100253355 B1 KR 100253355B1 KR 1019970061758 A KR1019970061758 A KR 1019970061758A KR 19970061758 A KR19970061758 A KR 19970061758A KR 100253355 B1 KR100253355 B1 KR 100253355B1
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South Korea
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film
tungsten
contact
thiose
metal wiring
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KR1019970061758A
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Korean (ko)
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KR19990041201A (en
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오승언
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided to improve reliability of the contact by preventing the formation of a key hole on a top surface of the contact. CONSTITUTION: In the method, a lower metallization layer(12) is formed on a semiconductor wafer(11), and the first TEOS layer(13) is deposited over the semiconductor wafer(11) and the lower metallization layer(12). The first TEOS layer(13) is then selectively etched to expose a portion of the lower metallization layer(12), and a tungsten(14) to be used for the contact is selectively grown on the exposed portion of the lower metallization layer(12). Next, the second TEOS layer(15) is deposited over the tungsten(14) and the first TEOS layer(13), and then planarized by chemical mechanical polishing until a planar top portion of the tungsten(14) is exposed.

Description

반도체소자의 콘택 제조방법Contact manufacturing method of semiconductor device

본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 특히 다층 금속배선을 선택적으로 접속시키는 콘택(contact)의 특성을 향상시키기에 적당하도록 한 반도체소자의 콘택 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device, and more particularly, to a method for manufacturing a contact for a semiconductor device, which is suitable for improving the characteristics of a contact for selectively connecting a multilayer metal wiring.

일반적으로, 반도체소자는 반도체기판상에 각종 소자를 형성한 후, 소자들을 접속시키거나 또는 전류를 공급하기 위한 금속배선이 제조되는데, 현재는 2층∼4층의 다층 금속배선이 주로 사용된다. 이러한 다층 금속배선구조는 하부 금속배선의 상부에 절연막을 증착하고, 콘택을 형성하여 선택적으로 상부 금속배선을 접속시키게 되며, 이와같은 종래 반도체소자의 콘택 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a semiconductor device is formed with various devices on a semiconductor substrate, and then a metal wiring for connecting the devices or supplying current is manufactured. Currently, two to four layers of multilayer metal wiring are mainly used. The multi-layered metal wiring structure deposits an insulating film on top of the lower metal wiring, forms a contact, and selectively connects the upper metal wiring, and this method will be described in detail with reference to the accompanying drawings. As follows.

도1a 내지 도1f는 종래 반도체소자의 콘택 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체소자들이 형성된 반도체웨이퍼(1)의 상부에 하부 금속배선(2)을 형성하는 단계(도1a)와; 그 금속배선(2)이 형성된 반도체웨이퍼(1)상에 제1티오스막(TEOS : tetra ethyl orthosilicate,3)을 증착하는 단계(도1b)와; 그 제1티오스막(3)의 상부에 에스오지막(SOG : silicon on glass,4)을 증착한 후, 에치백(etch-back)하여 평탄화하는 단계(도1c)와; 그 제1티오스막(3)과 에스오지막(4)의 상부에 제2티오스막(5)을 증착한 후, 사진식각공정을 통해 상기 금속배선(2)의 상부에 형성된 제2,제1티오스막(5),(3)을 식각하여 콘택홀을 형성하는 단계(도1d)와; 그 콘택홀의 내부 및 제2티오스막(5)의 상부에 보조배선(6)을 형성하는 단계(도1e)와; 그 보조배선(6)의 상부에 텅스텐(7)을 증착한 후, 에치백하여 그 텅스텐(7)을 콘택홀의 내부에 매립하는 단계(도1f)로 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 콘택 제조방법을 좀더 상세히 설명한다.1A to 1F are cross-sectional views showing a conventional method for manufacturing a contact of a semiconductor device, and as shown therein, forming a lower metal wiring 2 on an upper portion of a semiconductor wafer 1 on which semiconductor devices are formed (FIG. 1A). Wow; Depositing a first thiose film (TEOS: tetra ethyl orthosilicate, 3) on the semiconductor wafer 1 on which the metal wiring 2 is formed (FIG. 1B); Depositing an SG film (SOG: silicon on glass, 4) on top of the first thios film (3), and then etching back to planarize (FIG. 1C); After depositing the second thiose film 5 on the first thios film 3 and the SOH film 4, the second agent is formed on the metal wiring 2 through a photolithography process. Etching the one-thiose films 5 and 3 to form contact holes (FIG. 1D); Forming auxiliary wirings 6 in the contact holes and on the second thios film 5 (Fig. 1E); After depositing tungsten 7 on the auxiliary wiring 6, it is etched back and the tungsten 7 is embedded in the contact hole (FIG. 1F). Hereinafter, a method for manufacturing a contact of a conventional semiconductor device as described above will be described in more detail.

먼저, 도1a에 도시한 바와같이 반도체소자들이 형성된 반도체웨이퍼(1)의 상부에 하부 금속배선(2)을 형성한다. 이때, 하부 금속배선(2)은 반도체소자들의 전극이 될 수도 있다.First, as shown in FIG. 1A, a lower metal wiring 2 is formed on the semiconductor wafer 1 on which semiconductor devices are formed. In this case, the lower metal wiring 2 may be an electrode of semiconductor devices.

그리고, 도1b에 도시한 바와같이 금속배선(2)이 형성된 반도체웨이퍼(1)상에 제1티오스막(3)을 증착한다. 이때, 제1티오스막(3)은 배선간을 절연시키는 절연막이다.As shown in FIG. 1B, the first thiose film 3 is deposited on the semiconductor wafer 1 on which the metal wiring 2 is formed. At this time, the first thiose film 3 is an insulating film which insulates the wirings.

그리고, 도1c에 도시한 바와같이 제1티오스막(3)의 상부에 에스오지막(4)을 증착한 후, 에치백하여 평탄화한다. 이때, 에스오지막(4)은 평탄하지 않은 제1티오스막(3)을 평탄화하기 위해 증착하며, 에치백은 제1티오스막(3)이 노출될때까지 실시한다.Then, as shown in Fig. 1C, the SOH film 4 is deposited on the first TOS film 3, and then etched back to planarize it. At this time, the SOH film 4 is deposited to planarize the uneven first thios film 3, and the etch back is performed until the first thios film 3 is exposed.

그리고, 도1d에 도시한 바와같이 제1티오스막(3)과 에스오지막(4)의 상부에 제2티오스막(5)을 증착한 후, 사진식각공정을 통해 상기 금속배선(2)의 상부에 형성된 제2,제1티오스막(5),(3)을 식각하여 콘택홀을 형성한다.Then, as shown in FIG. 1D, the second thiose film 5 is deposited on the first thios film 3 and the SOH film 4, and then the metal wiring 2 is formed through a photolithography process. The contact holes are formed by etching the second and first thiose layers 5 and 3 formed on the upper portions of the substrates.

그리고, 도1e에 도시한 바와같이 콘택홀의 내부 및 제2티오스막(5)의 상부에 보조배선(6)을 형성한다. 이때, 보조배선(6)은 TiN막을 스퍼터링공정을 이용하여 형성하는데, 이 TiN막은 이후에 콘택홀에 매립되는 텅스텐(7)의 접착특성을 향상시키기 위하여 박막으로 형성한다.As shown in FIG. 1E, auxiliary wirings 6 are formed in the contact holes and on the second thios film 5. At this time, the auxiliary wiring 6 is formed by using a sputtering process, the TiN film is formed of a thin film to improve the adhesive properties of the tungsten (7) embedded in the contact hole later.

그리고, 도1f에 도시한 바와같이 보조배선(6)의 상부에 텅스텐(7)을 증착한 후, 에치백하여 그 텅스텐(7)을 콘택홀의 내부에 매립한다. 이때, 콘택홀의 내부에 매립되는 텅스텐(7)은 그 상부의 중앙에서 콘택홀의 급격한 단차로 인해 구멍(key hole)이 발생한다.Then, as shown in Fig. 1F, after the tungsten 7 is deposited on the auxiliary wiring 6, it is etched back and the tungsten 7 is embedded in the contact hole. At this time, the tungsten 7 embedded in the contact hole generates a key hole due to the sharp step of the contact hole in the center of the upper portion thereof.

그러나, 상기한 바와같은 종래 반도체소자의 콘택 제조방법은 콘택의 상부 중앙에서 형성되는 구멍으로 인해 상부 금속배선과 접촉불량이 발생하여 콘택의 신뢰성이 저하되는 문제점과; 공정이 복잡한 문제점이 있었다.However, the contact manufacturing method of the conventional semiconductor device as described above has a problem that the contact reliability is lowered due to poor contact with the upper metal wiring due to a hole formed in the upper center of the contact; The process was complicated.

본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 단순한 공정을 통해 콘택의 상부 중앙에 구멍이 형성되는 것을 방지하여 콘택의 신뢰성을 향상시킬 수 있는 반도체소자의 콘택 제조방법을 제공하는데 있다.The present invention has been made to solve the above problems, an object of the present invention is to prevent the formation of a hole in the upper center of the contact through a simple process to manufacture a contact of a semiconductor device that can improve the reliability of the contact To provide a method.

도1은 종래 반도체소자의 콘택 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a contact of a semiconductor device.

도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

11:반도체웨이퍼 12:금속배선11: Semiconductor wafer 12: Metal wiring

13,15:제1,제2티오스막 14:텅스텐13,15: 1st, 2nd thiose film 14: tungsten

상기한 바와같은 본 발명의 목적은 하부 금속배선이 형성된 반도체웨이퍼상에 제1티오스막을 증착하는 단계와; 사진식각공정을 통해 제1티오스막을 부분적으로 식각하여 상기 하부 금속배선의 일부를 노출시키는 단계와; 상기 노출된 금속배선상에 소정높이로 텅스텐을 선택성장시켜 기둥모양으로 텅스텐을 형성하는 단계와; 상기 텅스텐 및 제1티오스막의 상부에 제2티오스막을 증착한 후, 화학기계적연마법을 통해 상기 텅스텐의 상부가 평평하게 노출될때까지 평탄화하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 콘택 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above comprises the steps of depositing a first thiose film on a semiconductor wafer on which a lower metal wiring is formed; Partially etching the first thios film through a photolithography process to expose a portion of the lower metal wiring; Selectively growing tungsten at a predetermined height on the exposed metal wiring to form tungsten in a pillar shape; A semiconductor according to the present invention is achieved by depositing a second thiose film on top of the tungsten and first thiose film, and then planarizing it until the top of the tungsten is flatly exposed by chemical mechanical polishing. A method of manufacturing a contact of an element will be described in detail with reference to the accompanying drawings.

도2a 내지 도2f는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 반도체소자들이 형성된 반도체웨이퍼(11)의 상부에 하부 금속배선(12)을 형성하는 단계(도2a)와; 그 금속배선(12)이 형성된 반도체웨이퍼(11)상에 제1티오스막(13)을 증착하는 단계(도2b)와; 사진식각공정을 이용하여 금속배선(12)의 일부가 노출되도록 제1티오스막(13)의 일부를 식각하는 단계(도2c)와; 그 노출된 금속배선(12)상에 소정높이로 텅스텐(14)을 선택성장시키는 단계(도2d)와; 그 텅스텐(14) 및 제1티오스막(13)의 상부에 제2티오스막(15)을 증착하는 단계(도2e)와; 화학기계적연마(chemical mechanical polishing : CMP)공정을 통해 텅스텐(14)의 상부가 평평하게 노출될때까지 평탄화하는 단계(도2f)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A through 2F are cross-sectional views showing an embodiment of the present invention, as shown in the drawing, forming a lower metal wiring 12 on an upper portion of a semiconductor wafer 11 on which semiconductor elements are formed (FIG. 2A) and FIG. ; Depositing a first thiose film 13 on the semiconductor wafer 11 on which the metal wiring 12 is formed (FIG. 2B); Etching a portion of the first thiose film 13 to expose a portion of the metal wiring 12 using a photolithography process (FIG. 2C); Selectively growing tungsten 14 at a predetermined height on the exposed metal wiring 12 (FIG. 2D); Depositing a second thiose film 15 on the tungsten 14 and the first thiose film 13 (FIG. 2E); The chemical mechanical polishing (CMP) process is performed to planarize until the top portion of the tungsten 14 is flatly exposed (FIG. 2F). Hereinafter, an embodiment of the present invention as described above will be described in more detail.

먼저, 도2a에 도시한 바와같이 반도체소자들이 형성된 반도체웨이퍼(11)의 상부에 하부 금속배선(12)을 형성한다.First, as shown in FIG. 2A, the lower metal wiring 12 is formed on the semiconductor wafer 11 on which the semiconductor devices are formed.

그리고, 도2b에 도시한 바와같이 금속배선(12)이 형성된 반도체웨이퍼(11)상에 제1티오스막(13)을 증착한다. 이때, 제1티오스막(13)은 1000Å∼1500Å의 두께로 증착한다.As shown in FIG. 2B, the first thiose film 13 is deposited on the semiconductor wafer 11 on which the metal wiring 12 is formed. At this time, the first thiose film 13 is deposited to a thickness of 1000 kPa to 1500 kPa.

그리고, 도2c에 도시한 바와같이 사진식각공정을 이용하여 금속배선(12)의 일부가 노출되도록 제1티오스막(13)의 일부를 식각한다.As shown in FIG. 2C, a part of the first thiose film 13 is etched by using a photolithography process so that a part of the metal wiring 12 is exposed.

그리고, 도2d에 도시한 바와같이 노출된 금속배선(12)상에 소정높이로 텅스텐(14)을 선택성장시킨다. 이때, 텅스텐(14)은 텅스텐이나 티타늄과 같은 금속의 상부에서는 증착이 이루어지지만, 산화막이나 질화막같은 절연층의 상부에서는 증착이 이루어지지 않는 특성을 이용하여 노출된 금속배선(12)상에 선택성장시키며, 성장시키는 높이는 1㎛이다.As shown in FIG. 2D, tungsten 14 is selectively grown on the exposed metal wiring 12 at a predetermined height. At this time, the tungsten 14 is selectively grown on the exposed metal wiring 12 by using the characteristic that the deposition is performed on the top of the metal such as tungsten or titanium, but not on the top of the insulating layer such as the oxide film or the nitride film. And the height to grow is 1㎛.

그리고, 도2e에 도시한 바와같이 텅스텐(14) 및 제1티오스막(13)의 상부에 제2티오스막(15)을 증착한다. 이때, 제2티오스막(15)의 두께는 2㎛이다.As shown in FIG. 2E, the second thiose film 15 is deposited on the tungsten 14 and the first thiose film 13. At this time, the thickness of the second thios film 15 is 2 μm.

그리고, 도2f에 도시한 바와같이 화학기계적연마공정을 통해 텅스텐(14)의 상부가 평평하게 노출될때까지 평탄화한다.As shown in FIG. 2F, the tungsten 14 is planarized until the top of the tungsten 14 is flatly exposed through the chemical mechanical polishing process.

상기한 바와같은 본 발명에 의한 반도체소자의 콘택 제조방법은 콘택의 상부 중앙에 구멍이 형성되는 것을 방지하여 콘택의 신뢰성을 향상시킬수 있는 효과와; 공정을 단순화할 수 있는 효과가 있다.The method for manufacturing a contact of a semiconductor device according to the present invention as described above has the effect of preventing the formation of a hole in the upper center of the contact to improve the reliability of the contact; The effect is to simplify the process.

Claims (4)

하부 금속배선이 형성된 반도체웨이퍼상에 제1티오스막을 증착하는 단계와; 사진식각공정을 통해 제1티오스막을 부분적으로 식각하여 상기 하부 금속배선의 일부를 노출시키는 단계와; 상기 노출된 금속배선상에 소정높이로 텅스텐을 선택성장시켜 기둥모양의 텅스텐을 형성하는 단계와; 상기 텅스텐 및 제1티오스막의 상부에 제2티오스막을 증착한 후, 화학기계적연마법을 통해 상기 텅스텐의 상부가 평평하게 노출될때까지 평탄화하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 콘택 제조방법.Depositing a first thiose film on a semiconductor wafer on which lower metal wirings are formed; Partially etching the first thios film through a photolithography process to expose a portion of the lower metal wiring; Selectively growing tungsten at a predetermined height on the exposed metal interconnection to form columnar tungsten; And depositing a second thiose film on top of the tungsten and first thiose film, and then planarizing the surface of the tungsten until the top surface of the tungsten is flatly exposed by chemical mechanical polishing. . 제 1항에 있어서, 상기 제1티오스막은 1000Å∼1500Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 콘택 제조방법.2. The method of claim 1, wherein the first thiose film is deposited to a thickness of 1000 GPa to 1500 GPa. 제 1항에 있어서, 상기 텅스텐은 1㎛의 높이로 선택성장시키는 것을 특징으로 하는 반도체소자의 콘택 제조방법.The method of claim 1, wherein the tungsten is selectively grown to a height of 1 μm. 제 1항에 있어서, 상기 제2티오스막은 2㎛의 두께로 증착하는 것을 특징으로 하는 반도체소자의 콘택 제조방법.The method of claim 1, wherein the second thiose film is deposited to a thickness of 2 μm.
KR1019970061758A 1997-11-21 1997-11-21 Method for fabricating contact of semiconductor device KR100253355B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7867902B2 (en) 2008-07-10 2011-01-11 Samsung Electronics Co., Ltd. Methods of forming a contact structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7867902B2 (en) 2008-07-10 2011-01-11 Samsung Electronics Co., Ltd. Methods of forming a contact structure

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