JPH09229996A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to easily execute a dynamic burn-in test (B test) by a facility corresponding to static burn-in by assembling the B test function into a testing circuit as a part of functional test mode. SOLUTION: The semiconductor integrated circuit comprises a clock signal generator 1, a B test signal generator 2, a test mode setter 3 and testing circuits 4 to 6. In the case of functional test, a functional test mode set signal TM is supplied via a terminal TT1, the setter 3 outputs a test control signal CT in response to it to operate the circuits 4 to 6, thereby executing the functional test. At the time of the B test, the B test mode signal TB via the terminal TT2 is activated, the setter 3 becomes the control state corresponding to the B test mode in response to it. Simultaneously, the generator 2 supplies the B test signal DB to the circuits 4 to 6, which insert the signal DB to the input signal, and supply it to inner circuit blocks 7 to 9. Thus, the B tests of the blocks 7 to 9 is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which performs a burn-in test process in a manufacturing stage.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been increasing in circuit scale and operating at high speed. In addition, in order to eliminate initial defects and ensure reliability in the manufacturing stage,
The burn-in test is becoming important as an accelerated test performed in the sorting process and the like. However, in the above trend, static burn-in that supplies only the DC level of the power supply and the input terminal in the high temperature atmosphere that has been widely used in the past, and clock burn-in that supplies the power supply and the clock signal of several kinds of frequencies in the high temperature atmosphere. It is becoming difficult to achieve the intended purpose in the test. The reason is that in the former, the power supply voltage is supplied, but the internal circuit does not operate, and in the latter, although some of the internal circuits operate with several types of clock signals, circuits with very small circuit scale and circuits with few signals are used. This is because it is difficult to bring the operating rate of the circuit close to 100% except in some cases.

Since a clock signal that is normally used is a simple repeating signal of a few types, if there is a circuit that requires initial setting at the start of operation, this initial setting is impossible and therefore internal The circuit operation does not start. Further, when a common clock signal is supplied to a place where two kinds of clock signals should be originally supplied, such as a shift register, due to the restriction of the number of clock signals, from the place where the data frequency becomes equal to the clock frequency, Since the change of data is not transmitted, the operation stops.

For this reason, it is desirable that the burn-in test be performed in a state in which all the elements of the internal circuit are operating in order to remove the initial failure. Therefore, signals are supplied to all the input terminals for actual use. There is an ever-increasing need for dynamic burn-in tests that operate in near-state conditions. However, in order to perform such a dynamic burn-in test, a test device that generates a large number of complicated test signals for each type of semiconductor integrated circuit is required, and a high-speed clock is also required depending on the type. As a result, there are problems such as large scale burn-in equipment, longer development period, and higher cost.

In order to solve such a problem, conventionally,
Built-in dynamic burn-in test signal generation circuit including clock generation circuit in the semiconductor integrated circuit itself to be inspected,
It has been proposed to provide an external input terminal for inputting a control signal, activate the dynamic burn-in test signal generating circuit by controlling the control signal, and supply a test signal to an internal circuit. For example, JP-A-5-1023
98 (Reference 1), JP-A-4-218938 (Reference 2), and JP-A-63-2719666 (Reference 3).

The conventional semiconductor integrated circuits described in the above documents 1 to 3 are easily controlled by controlling the above-mentioned dynamic burn-in test signal generating circuit built in the semiconductor integrated circuit itself, so that the dynamic burn-in test device can be easily constructed. It is to carry out a test.

A test circuit incorporating a semiconductor integrated circuit for a normal operation test is used for the purpose of confirming whether or not the manufactured semiconductor integrated circuit satisfies desired functions and characteristics, and without this test circuit. It is indispensable when the above confirmation is difficult. However, the incorporation of the dynamic burn-in test signal generation circuit is not necessary when the static burn-in or the clock burn-in is performed, and the chip area is increased and the cost is increased. However, it is expected that the number of products with a built-in dynamic burn-in test signal generation circuit of this type will increase in the future from the viewpoint of increasing the circuit scale, speeding up, and ensuring reliability.

Referring to FIG. 2, which shows a block diagram of a conventional semiconductor integrated circuit of this type, this conventional semiconductor integrated circuit responds to activation of a dynamic burn-in test mode (hereinafter referred to as B test mode) signal TB. A clock signal generating circuit 1 for generating a clock signal for generating a test signal (hereinafter referred to as a B test signal), a dynamic burn-in test signal generating circuit 2 for generating a B test signal DB in response to the supply of the clock signal, and a signal T.
A test signal insertion circuit 10 for inserting a B test signal into each of the input signals in response to activation of B, and internal circuit blocks 7 to 9 to be tested are provided.

Next, the operation of the conventional semiconductor integrated circuit will be described with reference to FIG. 2. During normal operation, the B test mode signal TB supplied through the B test mode setting terminal TT1 is inactivated. That is, the logic 0 is set, the clock signal generation circuit 1 and the dynamic burn-in test signal generation circuit 2 are inactivated in response to the logic 0, and the test signal insertion circuit 10 is input to the input terminals TI1 and TI2.
Input signals I1 and I2 from the internal circuit block 7 to
Normal operation is performed by supplying each of the nine. Next, at the time of the dynamic burn-in test, the B test mode signal TB is activated, that is, set to logic 1, and the clock signal generation circuit 1 and the dynamic burn-in test signal generation circuit 2 are activated in response to the logic 1 of the signal TB.
The B test signal DB is output and supplied to the test signal insertion circuit 10. The test signal insertion circuit 10 inserts the B test signal DB into the input signals I1 and I2, and the internal circuit blocks 7 to 9 are inserted.
To each of the Thereby, the dynamic burn-in test of the internal circuit is performed.

However, although this conventional semiconductor integrated circuit has a dynamic burn-in test function, it performs a test for confirming the operation of the function of a deeper portion of the logic circuit at the time of selection inspection at the time of manufacture or at the time of normal operation. It had no functional test function. This is because the logic of the internal circuit to be tested is generally complicated and control for operation confirmation is difficult, and the circuit scale becomes too large when this function is included.

[0011]

Although the above-mentioned conventional semiconductor integrated circuit has a dynamic burn-in test function, it is more detailed in the logic circuit during the selection inspection during manufacturing or the normal operation which causes an increase in the circuit scale. However, there is a drawback that it does not have a function test function for testing to confirm the operation of various functions and performances.

An object of the present invention is to provide a semiconductor integrated circuit which suppresses an increase in circuit scale and includes a dynamic burn-in test function as one of the function test functions.

[0013]

A semiconductor integrated circuit according to the present invention sets a dynamic burn-in test mode in which the test signal is supplied to all input terminals of a circuit under test to operate in a state close to an actual use state. A clock generation circuit for generating a test clock signal in response to the supply of the test mode signal, and a dynamic burn-in circuit activated in response to the supply of the first test mode signal and responding to the supply of the clock signal A dynamic burn-in test signal generating circuit for generating a burn-in test signal, and a functional test mode for confirming the function / performance of the circuit under test in response to the supply of the first test mode signal; The burn-in test mode is switched to and the function test is performed when the function test mode is set. A test mode setting circuit that outputs a corresponding functional test signal in response to the supply of a second test mode signal that sets one of the modes, and the test mode setting circuit that responds to the supply of the functional test signal or the burn-in test signal. And a test circuit for executing the test of the test circuit.

[0014]

FIG. 2 shows an embodiment of the present invention.
Referring to FIG. 1, which is also a block in which common reference characters / numerals are given to common constituent elements with those of FIG. 1 and dynamic burn-in test (B
In addition to the test) signal generation circuit 2 and the internal circuit blocks 7 to 9, in response to the level of the burn-in test mode signal TB, it switches between the functional test mode and the burn-in test mode and supplies the functional test mode setting signal TM. Test control signal CT for responding and performing a functional test
And a test mode setting circuit 3 for outputting a test control signal CT, and test circuits 4-6 for supplying an input / test signal to each of the internal circuit blocks 7-9 in response to the supply of the test control signal CT.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, as in the conventional case, in the normal operation, the B test mode signal supplied via the B test mode setting terminal TT1 is supplied. TB is deactivated, that is, logic 0
In response to the logic 0, the clock signal generation circuit 1 and the dynamic burn-in test signal generation circuit 2 are inactivated, and the test mode setting circuit 3 is functionally tested.
It is set to the control state corresponding to normal input. Therefore, the dynamic burn-in test mode is not set. When performing a function test, the terminal T for setting the function test mode
A functional test mode setting signal TM including serial data is supplied via T2. In response to the supply of the functional test mode setting signal TM, the test mode setting circuit 3 outputs the test control signal CT corresponding to the desired functional test to operate the test circuits 4 to 6 to carry out the desired functional test. When the B test mode signal TB is logic 0, it does not affect the normal operation and other functional test mode settings.

At the time of the dynamic burn-in test, the B test mode signal TB is activated, that is, set to logic 1, and the test mode setting circuit 3 is set to the control state corresponding to the burn-in test mode in response to the logic 1 of the signal TB. It At the same time, the clock signal generation circuit 1 and the dynamic burn-in test signal generation circuit 2 are activated, and the B test signal DB is output and supplied to the test circuits 4 to 6. The test circuits 4 to 6 are the conventional test signal insertion circuit 1
Like 0, insert B test signal DB into each input signal,
It is supplied to each of the internal circuit blocks 7 to 9. Thereby, the dynamic burn-in test of the internal circuit blocks 7 to 9 is carried out.

As a result, in the semiconductor integrated circuit of the present embodiment, the dynamic burn-in test function is incorporated into the test circuit as a part of the functional test mode, so that the dynamic burn-in test can be easily performed by the conventional equipment corresponding to the static burn-in. Not only will it be possible, but it will also be possible to carry out functional tests to confirm more complicated functions and performance of internal circuits. Moreover, by sharing the common parts of the signals and circuits of the dynamic burn-in test function and the general function test function, it is possible to suppress an increase in the overall circuit size to a minimum and suppress an increase in the chip area. As a result, the introduction of the dynamic burn-in test function is facilitated.

Further, by incorporating the dynamic burn-in test function into the test circuit as a part of the functional test mode as described above, it is more effective from the circuit design stage.
It is possible to construct an efficient dynamic burn-in test system, and it is also possible to design a test system that uses the generated dynamic burn-in test signal to confirm the function of the internal circuit.

Further, by outputting the above-mentioned dynamic burn-in test signal to the outside, the operation confirmation of the clock generation circuit and the dynamic burn-in test signal generation circuit can be carried out at the selection inspection stage at the time of manufacturing.

As described above, by supplying the dynamic burn-in test signal to the test circuit for the function test, the respective functions can be mutually reinforced and a more powerful test system can be constructed.

[0021]

As described above, the semiconductor integrated circuit of the present invention incorporates the dynamic burn-in test function into the test circuit as a part of the functional test mode, so that the dynamic burn-in test can be performed with conventional static burn-in compatible equipment. The effect is not only that it can be easily implemented, but also that it is possible to perform a functional test that confirms the more complicated function and performance of the internal circuit.

Further, an increase in the overall circuit scale can be suppressed to a minimum, and an increase in chip area, which causes a cost increase, can be suppressed. Therefore, there is an effect that the introduction of the dynamic burn-in test function is facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 Clock signal generation circuit 2 Dynamic burn-in test signal generation circuit 3 Test mode setting circuit 4-6 Test circuit 7-9 Internal circuit block 10 Test signal insertion circuit

Claims (2)

[Claims] 1. A test in response to supply of a first test mode signal for setting a dynamic burn-in test mode in which the test signal is supplied to all input terminals of a circuit under test to operate in a state close to an actual use state. And a dynamic burn-in test signal generation circuit for generating a burn-in test signal for dynamic burn-in in response to the supply of the clock signal. And a burn-in test mode for confirming the function / performance of the circuit under test in response to the supply of the first test mode signal. Sometimes a second test mode that sets one of the functional test modes A test mode setting circuit that outputs a corresponding functional test signal in response to the supply of a signal, and a test circuit that executes a test of the circuit under test in response to the supply of the functional test signal or the burn-in test signal A semiconductor integrated circuit characterized by the above. 2. The first test mode signal is a logic 0,
2. The semiconductor integrated circuit according to claim 1, wherein the second test mode signal is a binary level signal of 1, and the second test mode signal is composed of a serial code.