JPH1048290A - Semiconductor integrated circuit and method for testing its performance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct performance tests on a logical block without delaying the operating speed of the block nor increasing the area of a chip. SOLUTION: A tester 9 is connected to the external terminals 11 and 12 of a chip 1 and a logical block 2 and other logical blocks 3 are integrated in the chip 1. After serial data are stored in a register 4 for test by temporarily stopping the internal clock of the block 2, the internal clock is operated and the value of the clock is read in the block 2. After the block 2 is made to repeat test data reading operations, operated result data are outputted from the block 2 and stored in a register 5 for test. Thereafter, the operated result data are read by means of the tester 9 by operating the clock for shift of a signal line 71 in a state where the internal clock of the block 2 is again stopped and whether or not the block 2 normally operates is discriminated by comparing the operated result data with an expected value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a built-in logic block for which an operation test is externally performed by a tester, and an operation test method thereof.

[0002]

2. Description of the Related Art With the recent advance in miniaturization technology, in a semiconductor integrated circuit, a logic block having a specific function and a circuit related thereto or a plurality of logic blocks have been integrated on the same chip. . For example, there is one in which a programmable processor element and a memory are integrated on the same chip. In such a semiconductor integrated circuit, test data for testing is generally created for each logical block. In addition, another semiconductor integrated circuit in which the same logic block is built uses the test data to shorten the time for generating the test data.

However, it is difficult to directly apply test data from an external source to a logic block in a semiconductor integrated circuit, which makes it difficult to perform an operation test on the logic block. Conventionally, an operation test of such a logic block has been performed as follows. FIG. 3 is an explanatory diagram showing a first operation test method of a conventional logic block. First
In the operation test method, a special register (scan cell) 102 that can be used as such at the time of design is used in advance so that all or some necessary registers in the logic block 101 can be used as shift registers.

FIG. 4 is a block diagram showing a configuration of the scan cell 102 which can be used also as a shift register. In the scan cell 102, during normal operation, the flip-flop 10
3 is connected to the input of "Data i
n ”is selected as an input, and data is read in synchronization with the clock“ CK. ”On the other hand, during the shift register operation, the selector 104 selects“ SI ”as an input, and immediately before it is connected to“ SI ”. Output of flip-flop "S"
The value of "O" is read in synchronization with the clock "SCK".
By connecting the input and output of the shift register to an external terminal, an arbitrary value can be read and written from and to the register in the logical block by serial input / output.

Therefore, by configuring the logical block 101 using the scan cell 102, an arbitrary operation required for testing the logical block 101 is performed, the result is read from the logical block 101, and the expected value is compared with the expected value by the tester 105. A test can be performed by comparing. FIG. 5 is an explanatory diagram showing a second operation test method of a conventional logic block. In the second operation test method, the logic block 2
A special flip-flop (boundary scan cell) 202 that outputs the input value as it is during the normal operation and outputs the value in the flip-flop during the test operation is inserted into the input and output 01. The flip-flop 202 can also operate as a shift register, and its input is connected to an external terminal 211.
Thus, the flip-flop 202 is connected to the logic block 20.
By inserting the logic block 201 into one input path, an arbitrary value necessary for testing the logic block 201 can be given to the logic block 201 by serial input / output from the external tester 205.

Also, by reading the value of the flip-flop 203 inserted into the output path of the logic block 201 as a serial output to the external tester 205 via the external terminal 212, it is determined whether the logic block 201 is operating normally. Can be determined, and an operation test of the logic block 201 can be performed.

[0007]

However, in order to use the first operation test method, it is necessary to use a special register (scan cell) 102 having a shift register function in all or a part of the logic block 101. is there. Since the register 102 having this special function has an extra circuit, there is a problem that the operation speed is slow and the chip area is increased. On the other hand, in order to use the second operation test method, special flip-flops (boundary scan cells) 202 and 203 for the input path and the output path of the logic block 201 must be inserted. Since the input path and the output path need to be operated even during the normal operation, a buffer circuit having a sufficient size must be used so as to satisfy the specification in terms of speed. Therefore, there is a problem that the chip area increases, and an extra circuit is inserted in the data path.
There is a problem that the performance is deteriorated also in terms of speed.
If the input and output terminals of the logic block 201 are the same terminal in both directions, such a boundary scan cell cannot be inserted.

An object of the present invention is to provide a semiconductor integrated circuit capable of performing an operation test of a logic block without delaying the operation speed and without increasing the chip area, and an operation test method thereof.

[0009]

In order to achieve the above object, a semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit having a built-in logic block that is subjected to an operation test by an external tester. An input shift register connected to the tester via an input terminal and sequentially storing test data from the tester; a switching circuit connecting the input shift register to an input node of the logic block; A read circuit that reads test data stored in the input shift register from the node into the logic block; and an output shift register that sequentially stores operation result data from which the test data is read and processed by the logic block. Wherein the tester outputs an operation result output from the output shift register via an output terminal. And comparing the over data with a predetermined expected value.

In addition, a plurality of logic blocks are built in, and the logic block on which the operation test is performed is capable of reading data from another logic block via the input node, and the switching circuit is connected to the input node. Is preferably switched from the other logic block to the input shift register. Further, it is preferable that the logic block generates a write signal of operation result data sequentially stored in the output shift register. 5. The operation test method for a semiconductor integrated circuit according to claim 4, wherein the operation test of the built-in logic block is performed by an external tester using a tester. The test data from the tester is sequentially stored in a shift register, the input shift register is connected to an input node of the logic block, and the test data stored in the input shift register is read from the connected input node. Read into a logic block, the test data is read, and the operation result data processed by the logic block is sequentially stored in a shift register for output,
The tester compares the operation result data output from the output shift register via an output terminal with a predetermined expected value.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor integrated circuit and an operation test method thereof according to the present invention will be described. FIG. 1 is a block diagram showing a configuration of the semiconductor integrated circuit according to the embodiment. In the semiconductor integrated circuit according to the present embodiment, a tester 9 for performing an operation test is connected to the external terminals 11 and 12 of the chip 1. A logic block 2 to be measured and another logic block 3 are integrated inside the chip 1. The logic block 2 may include a register inside without being limited to the combinational circuit.
In this case, a simple flip-flop can be used as a register included in the logic block 2. FIG. 2 is a block diagram showing a configuration of a flip-flop included in the logic block 2. The flip-flop 7 is a simple flip-flop that outputs data input to a Datain terminal to a Dataout terminal in synchronization with a clock input to a CK terminal.

An output node 32 of the logic block 3 is connected to an input node 21 of the logic block 2 via a tri-state buffer 31. Further, the output node 42 of the test register 4 is connected to the input node 21 of the logic block 2 via the tri-state buffer 41. On the other hand, output node 2 of logic block 2
2 is connected to the input node 51 of the test register 5. The output of a multi-input OR gate 36 is connected to the control line 34 of the tristate buffer 31, and one of its inputs is connected to a test control line 61 via an inverter 37.
Is connected. The other input of the multi-input OR gate 36 is connected to the control line 23 of the logic block 2. Therefore, the signal on the control line 34 of the tristate buffer 31 always becomes logic "1" when the signal on the test control line 61 is logic "0". At this time, the output node 32 of the logic block 3 is in a floating state and is invalid. It is.

On the other hand, the control line 43 of the tri-state buffer 41 is connected to the output of the multi-input OR gate 47, and one of its inputs is directly connected to the test control line 61. The other input of the multi-input OR gate 47 is connected to the control line 23 of the logic block 2. Therefore,
The signal on the control line 43 of the tri-state buffer 41 is controlled by the signal on the control line 23 of the logic block 2 when the signal on the test control line 61 is logic "0". When the control signal on the test control line 61 is logic “1”, the signal on the control line 43 of the tristate buffer 41 is always logic “1”, and the output node 42 of the test register 4 is output.
Is in a floating state and is invalid. At this time, the signal on the control line 34 of the tristate buffer 31 is controlled by the control line 23 of the logic block 2 because the signal on the test control line 61 is logic “1”.

The test registers 4 and 5 operate as shift registers when a shift clock is supplied from a signal line 71. The input terminal 44 of the test register 4 and the output terminal 55 of the test register 5 are connected to the external terminals 11 and 12 of the chip 1, respectively, and the tester 9 is connected to the external terminals 11 and 12 as described above. I have. The output terminal 45 of the test register 4 and the input terminal 54 of the test register 5 are connected inside the chip 1. Logical block 2
Is applied to the test register 5 from the signal line 52, the operation result data of the logic block 2 is written to the test register 5 from the output node 22. An operation test of the logic block 2 of the semiconductor integrated circuit having the above configuration will be described. When an operation test is performed, the signal on the test control line 61 is logic “0”.

Further, the internal clock of the logic block 2 is temporarily stopped, and the test registers 4 and 5 are set to the shift operation mode. In this state, the data (test data) to be given to the logic block 2 is given as serial data from the external terminal 11, and the shift clock on the signal line 71 is operated to store the test data in the test register 4. After that, the internal clock of the logic block 2 is operated to read the test data into the logic block 2.
After the operation of reading test data into the logic block 2 is repeated a required number of times in this way, the operation result data is output from the logic block 2. Logical block 2
Is read from the output node 22 to the test register 5 and stored therein. At this time, a write signal to the test register 5 is output from the logic block 2 through the signal line 52. .

Thereafter, the shift clock on the signal line 71 is operated while the internal clock of the logic block 2 is stopped again, and the operation result data stored in the test register 5 is output from the external terminal 12 as serial data. And
Read with tester 9. The tester 9 compares the operation result data output from the external terminal 12 with an expected value stored in advance to determine whether the logic block 2 has operated correctly. As described above, in the semiconductor integrated circuit according to the present embodiment, the test data prepared for testing the logic block 2 is directly input to the logic block 2 to cause the logic block 2 to perform an arbitrary operation. And the operation result data of the logic block 2 can be read. Therefore, since a special register such as a scan cell is not incorporated, the operation test of the logic block can be performed without delaying the operation speed of the semiconductor integrated circuit and without increasing the chip area.

In this embodiment, the case where the input node 21 and the output node 22 of the logic block 2 are different is shown. However, when the input node 21 and the output node 22 are the same node, The present invention can be applied to a case where the same test register performs the functions of the register 4 and the test register 5. Further, in this embodiment, when the test registers 4 and 5 are operated as shift registers, all the registers constituting the shift register input or output to the logical block 2. Even if an extraneous register is included, the operation of the present invention is not hindered.

Further, although the case where the test registers 4 and 5 are formed as a single chain has been described, a configuration in which the test registers are divided into a plurality of chains may be employed. In this case, the test registers 4 and 5 can be expanded to a configuration used for testing another logic block 3.

[0019]

According to the semiconductor integrated circuit according to the first aspect of the present invention, the input shift register includes a logic block for which an operation test is externally performed by a tester and is connected to the tester via an input terminal. The test data from the tester is sequentially stored, the input shift register is connected to the input node of the logic block by the switching circuit, and the input shift register is stored in the input shift register from the connected input node by the read circuit. The test data is read into the logic block, the test data is read, and the operation result data processed by the logic block is sequentially stored in an output shift register. The tester outputs the output shift register via an output terminal. Is compared with a predetermined expected value, so that one or more of the The logic block has a built-in logic block, and by directly inputting test data prepared for performing an operation test of the logic block to the logic block, the logic block can be arbitrarily operated, and the operation result of the logic block can be obtained. Can be read. Therefore, it is not necessary to provide a special register such as a scan cell or a boundary scan cell, so that a delay in the operation speed of the logic block and an increase in the chip area can be minimized.

According to the semiconductor integrated circuit of the second aspect,
A plurality of logic blocks are incorporated, and the logic block on which the operation test is performed is capable of reading data from another logic block via the input node, and the switching circuit sets a connection with the input node to the other logic block. Since the block is switched to the input shift register, even if there are a plurality of logical blocks, only the operation test of a specific logical block can be effectively performed. According to the semiconductor integrated circuit of the third aspect, the logic block generates the write signal of the operation result data sequentially stored in the output shift register, and thus generates the write signal to the output shift register. It is not necessary to provide a separate circuit, and an increase in chip area can be suppressed.

According to the semiconductor integrated circuit operation test method of the present invention, in the semiconductor integrated circuit operation test method in which the operation test of the built-in logic block is externally performed by a tester, the tester is connected to the tester via an input terminal. The test data from the tester is sequentially stored in the connected input shift register, the input shift register is connected to the input node of the logic block, and the input shift register is stored in the input shift register from the connected input node. The test data is read into the logic block, the test data is read, and the operation result data processed by the logic block is sequentially stored in an output shift register, and output from the output shift register via an output terminal. Since the operation result data is compared with a predetermined expected value by the tester, the logical block Delay in operation speed of and an increase in the chip area can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment.

FIG. 2 is a block diagram showing a configuration of a flip-flop included in a logic block 2.

FIG. 3 is an explanatory diagram showing a first operation test method of a conventional logic block.

FIG. 4 is a scan cell 1 that can also be used as a shift register.
FIG. 2 is a block diagram showing a configuration of the second embodiment.

FIG. 5 is an explanatory diagram showing a second operation test method of a conventional logic block.

[Explanation of symbols]

1 chip 2, 3 logic block 4, 5 test register 9 tester 31, 41 tri-state buffer

Claims (4)

[Claims] 1. A semiconductor integrated circuit having a built-in logic block for which an operation test is performed by a tester from the outside, comprising: an input shift register connected to said tester via an input terminal for sequentially storing test data from said tester; A switching circuit that connects the input shift register to an input node of the logic block; a read circuit that reads test data stored in the input shift register from the connected input node into the logic block; Test data is read, and an output shift register for sequentially storing operation result data processed by the logic block, wherein the tester has operation result data output from the output shift register via an output terminal. A semiconductor integrated circuit characterized by comparing with a predetermined expected value. 2. A logic block including a plurality of logic blocks, wherein a logic block on which the operation test is performed is capable of reading data from another logic block via the input node, and wherein the switching circuit is connected to the input node. 2. The semiconductor integrated circuit according to claim 1, wherein the logic circuit is switched from the other logic block to the input shift register. 3. The semiconductor integrated circuit according to claim 1, wherein said logic block generates a write signal of operation result data sequentially stored in said output shift register. 4. An operation test method for a semiconductor integrated circuit in which an operation test of a built-in logic block is performed by an external tester, wherein test data from the tester is supplied to an input shift register connected to the tester via an input terminal. The input shift register is connected to an input node of the logic block, and the test data stored in the input shift register is read from the connected input node into the logic block, and the test data is read. Are read and the operation result data processed by the logic block are sequentially stored in an output shift register, and the operation result data output from the output shift register via an output terminal and a predetermined expected value are compared with the tester. An operation test method for a semiconductor integrated circuit, characterized in that the operation is compared by: