JPH0922958A - Manufacture of package for housing semiconductor element - Google Patents

Manufacture of package for housing semiconductor element

Info

Publication number
JPH0922958A
JPH0922958A JP16879195A JP16879195A JPH0922958A JP H0922958 A JPH0922958 A JP H0922958A JP 16879195 A JP16879195 A JP 16879195A JP 16879195 A JP16879195 A JP 16879195A JP H0922958 A JPH0922958 A JP H0922958A
Authority
JP
Japan
Prior art keywords
layer
metallized
metal layer
metallized wiring
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16879195A
Other languages
Japanese (ja)
Other versions
JP3210838B2 (en
Inventor
Naomi Kayakiri
直美 茅切
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP16879195A priority Critical patent/JP3210838B2/en
Publication of JPH0922958A publication Critical patent/JPH0922958A/en
Application granted granted Critical
Publication of JP3210838B2 publication Critical patent/JP3210838B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a package by which a semiconductor element housed inside a container can be operated normally and stably for a long period by a method wherein a part of a metallized layer, for connection, which connects a metallized wiring layer on an insulating board to a metallized metal layer is covered with an insulating layer. SOLUTION: An insulating base body 1 comprises a step-shaped recessed part 1a used to house a semiconductor element. A plurality of metallized wiring layers 5 are applied to the surface from the stepped part of the recessed part 1a. A frameshaped metallized metal layer 8 is applied to the surface around the recessed part 1a. Then, a part of a metallized layer 10, for connection, which connects the metallized wiring layers 5 to the metallized metal layer 8 is covered with an insulating layer 11. Thereby, a container 4 which is composed of the insulating substrate 1 and a lid body 2 is airtightly sealed completely, and the semiconductor element which is housed at the inside of the container 4 can be operated normally and stably for a long period.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子を収容する
ための半導体素子収納用パッケージの製造方法に関し、
より詳細には半導体素子収納用パッケージに被着された
メタライズ金属層に電解メッキによりメッキ金属層を被
着させる方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor element housing package for housing semiconductor elements,
More specifically, the present invention relates to a method of depositing a plated metal layer on a metallized metal layer deposited on a semiconductor device housing package by electrolytic plating.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは一般に、酸化アルミニウム質
焼結体等の電気絶縁材料から成り、その上面に半導体素
子を収容するための段状の凹部を有し、且つ該凹部の段
差部周辺から上面外周部にかけてタングステン、モリブ
デン、マンガン等の高融点金属粉末から成る複数個のメ
タライズ配線層が被着された絶縁基体と、前記各メタラ
イズ配線層で絶縁基体の上面外周部に被着された部位に
銀ろう等のろう材を介して取着される鉄−ニッケル合金
等の金属から成る外部リード端子と、鉄−ニッケル−コ
バルト合金から成る蓋体とから構成されており、前記絶
縁基体の凹部底面に半導体素子を例えば金−シリコンろ
う材等の接着剤を介して接着固定するとともに該半導体
素子の各電極をボンディングワイヤーを介してメタライ
ズ配線層に電気的に接続し、しかる後、前記絶縁基体の
上面に蓋体をろう材を介して接合させ、絶縁基体と蓋体
とから成る容器内部に半導体素子を気密に収容すること
によって製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating a semiconductor element is generally made of an electrically insulating material such as an aluminum oxide sintered body and has a stepped concave portion for accommodating the semiconductor element on its upper surface. And an insulating substrate on which a plurality of metallized wiring layers made of a refractory metal powder such as tungsten, molybdenum, or manganese is deposited from around the step portion of the recess to the outer peripheral portion of the upper surface, and the metallized wiring layers. An external lead terminal made of a metal such as an iron-nickel alloy, which is attached to a portion adhered to the outer peripheral portion of the upper surface of the insulating substrate via a brazing material such as silver solder, and a lid made of an iron-nickel-cobalt alloy. The semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating substrate with an adhesive such as a gold-silicon brazing material, and each electrode of the semiconductor element is bonded. It is electrically connected to the metallized wiring layer via a bonding wire, and then a lid is joined to the upper surface of the insulating substrate via a brazing material to hermetically seal the semiconductor element inside the container composed of the insulating substrate and the lid. It becomes a semiconductor device as a product by being housed in.

【0003】尚、前記半導体素子収納用パッケージにお
いては絶縁基体の凹部周囲の上面にタングステン、モリ
ブデン、マンガン等の高融点金属粉末から成る枠状のメ
タライズ金属層が被着形成されており、該枠状のメタラ
イズ金属層に蓋体を金−錫ろう材等の封止材を介し接合
させることによって絶縁基体と蓋体とから成る容器が気
密に封止される。
In the package for accommodating semiconductor elements, a frame-shaped metallized metal layer made of refractory metal powder such as tungsten, molybdenum or manganese is deposited on the upper surface around the recess of the insulating substrate. The container including the insulating base and the lid is hermetically sealed by joining the lid to the metallized metal layer in the form of a strip through a sealing material such as a gold-tin brazing material.

【0004】また前記絶縁基体に被着させたメタライズ
配線層及び枠状のメタライズ金属層はその露出表面にニ
ッケル、金等の耐蝕性に優れ、且つボンディングワイヤ
ーや封止材としての金−錫ろう材等と接合性の良い金属
がメッキ法により被着されており、該ニッケル、金等か
ら成るメッキ金属層によってメタライズ配線層及びメタ
ライズ金属層の酸化腐食を有効に防止するとともにメタ
ライズ配線層とボンディングワイヤーとの接続及びメタ
ライズ金属層と蓋体との金−錫ろう材等の封止材を介し
ての接合を容易、且つ強固なものとしている。
The metallized wiring layer and the frame-shaped metallized metal layer deposited on the insulating substrate have excellent corrosion resistance against nickel, gold, etc. on the exposed surface thereof, and gold-tin solder as a bonding wire or a sealing material. A metal having a good bonding property with a metal or the like is deposited by a plating method, and the plated metal layer made of nickel, gold or the like effectively prevents oxidative corrosion of the metallized wiring layer and the metallized metal layer and bonds with the metallized wiring layer. The connection with the wire and the joining of the metallized metal layer and the lid through the sealing material such as a gold-tin brazing material are easy and strong.

【0005】更に前記メタライズ配線層及びメタライズ
金属層の露出表面へのメッキ金属層の被着は通常、電解
メッキ法が採用され、具体的にはメタライズ配線層の一
部とメタライズ金属層とを接続用メタライズ層で電気的
に接続するとともに各メタライズ配線層に連結部材で電
気的に共通に接続された外部リード端子をろう材を介し
て取着し、次にこれを所定の電解メッキ液中に浸漬する
とともに外部リード端子を介して各メタライズ配線層及
びメタライズ金属層にメッキ電力を印加し、各メタライ
ズ配線層及びメタライズ金属層の表面にメッキ金属層を
析出被着させ、最後に前記接続用メタライズ層の一部を
リューター等の研削装置により研削除去しメタライズ配
線層とメタライズ金属層とを電気的に独立させることに
よって行われている。
Further, the plating metal layer is usually deposited on the exposed surfaces of the metallized wiring layer and the metallized metal layer by an electrolytic plating method. Specifically, a part of the metallized wiring layer and the metallized metal layer are connected. External lead terminals that are electrically connected to each metallized wiring layer and electrically connected to each metallized wiring layer in common by a connecting member are attached through a brazing material, and then these are placed in a predetermined electrolytic plating solution. Immersion and applying plating power to each metallized wiring layer and metallized metal layer through external lead terminals, depositing and depositing a plated metal layer on the surface of each metallized wiring layer and metallized metal layer, and finally the metallization for connection Part of the layer is ground and removed by a grinder such as a router to electrically separate the metallized wiring layer and the metallized metal layer. .

【0006】[0006]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージによれば、メタライズ
配線層とメタライズ金属層の露出表面にメッキ金属層を
被着させる際、メタライズ配線層とメタライズ金属層を
電気的に接続する接続用メタライズ層の露出表面にもメ
ッキ金属層が被着されてしまい、接続用メタライズ層の
一部をリューター等の研削装置により研削除去する時に
接続用メタライズ層の表面に被着されたメッキ金属層の
一部が研削時の機械的応力によって接続用メタライズ層
から剥がれて、その結果、前記剥がれたメッキ金属層と
接続用メタライズ層との間に大気中の水分が浸入して接
続用メタライズ層に腐食を発生させるとともに、該腐食
がメタライズ金属層にまで進行して絶縁基体と蓋体とか
ら成る容器の気密封止を破り、容器内部に収容する半導
体素子を正常、且つ安定に作動させることができなくな
るという欠点を有していた。
However, according to this conventional package for accommodating semiconductor elements, the metallized wiring layer and the metallized metal layer are deposited when the plated metal layer is deposited on the exposed surfaces of the metallized wiring layer and the metallized metal layer. The plated metal layer is also deposited on the exposed surface of the metallization layer for connection that electrically connects the connection metallization layer, and when a part of the metallization layer for connection is ground and removed by a grinding device such as a router, the surface of the metallization layer for connection is removed. Part of the deposited plating metal layer is peeled from the connection metallization layer due to mechanical stress during grinding, and as a result, moisture in the atmosphere enters between the peeled plating metal layer and the connection metallization layer. As a result, corrosion is generated in the metallization layer for connection, and the corrosion progresses to the metallization metal layer to hermetically seal the container including the insulating base and the lid. Breaking the stop, the semiconductor element housed in the container properly, had the disadvantage and can not be stably operated.

【0007】[0007]

【目的】本発明は、かかる従来の欠点に鑑み案出された
ものであり、その目的は、内部に収容する半導体素子を
長期間にわたり正常、且つ安定に作動させることができ
る半導体素子収納用パッケージの製造方法を提供するこ
とにある。
[Object] The present invention has been devised in view of the above conventional drawbacks, and an object of the present invention is to package a semiconductor element in which a semiconductor element accommodated therein can be normally and stably operated for a long period of time. It is to provide a manufacturing method of.

【0008】[0008]

【課題を解決するための手段】本発明は上面に半導体素
子を収容するための段状の凹部を有し、且つ該凹部の段
差部から上面外周部にかけて複数個のメタライズ配線層
が被着されるとともに凹部周囲の上面に枠状のメタライ
ズ金属層が被着されている絶縁基体と、前記メタライズ
配線層に取着されている複数個の外部リード端子と、前
記枠状のメタライズ金属層に取着される蓋体とから成る
半導体素子収納用パッケージであって、前記外部リード
端子の取着された絶縁基体が下記(1)乃至(6)の工
程によって製作されていることを特徴とするものであ
る。
The present invention has a stepped recess for accommodating a semiconductor element on the upper surface, and a plurality of metallized wiring layers are deposited from the stepped portion of the recess to the outer periphery of the upper surface. In addition, an insulating substrate having a frame-shaped metallized metal layer deposited on the upper surface around the recess, a plurality of external lead terminals attached to the metallized wiring layer, and the framed metallized metal layer. A package for accommodating a semiconductor element, comprising a lid to be attached, characterized in that the insulating base body to which the external lead terminals are attached is manufactured by the following steps (1) to (6). Is.

【0009】(1)上面に半導体素子を収容するための
段状の凹部を有し、且つ該凹部の段差部より上面外周部
にかけて複数個のメタライズ配線層を、凹部周囲の上面
に枠状のメタライズ金属層を、上面に前記メタライズ配
線層の少なくとも1つと前記メタライズ金属層を接続す
る接続用メタライズ層を被着させた絶縁基体を形成する
工程と、(2)前記接続用メタライズ層の一部を絶縁層
で被覆する工程と、(3)一端が連結部材に共通に連結
されている複数個の外部リード端子の他端を各メタライ
ズ配線層に取着させる工程と、(4)前記メタライズ配
線層、メタライズ金属層、接続用メタライズ層及び外部
リード端子の露出表面に電解メッキ法によりメッキ金属
層を被着させる工程と、(5)前記接続用メタライズ層
の一部を、前記絶縁層が被着されている部位で研削除去
し、前記メタライズ配線層とメタライズ金属層とを電気
的に独立させる工程と、(6)前記各外部リード端子を
連結部材より切断分離する工程 また本発明は上面に半導体素子を収容するための段状の
凹部を有し、且つ該凹部の段差部から上面外周部にかけ
て複数個のメタライズ配線層が被着されるとともに凹部
周囲の上面に枠状のメタライズ金属層が被着されている
絶縁基体と、前記メタライズ配線層に取着されている複
数個の外部リード端子と、前記枠状のメタライズ金属層
に取着される蓋体とから成る半導体素子収納用パッケー
ジであって、前記外部リード端子の取着された絶縁基体
が下記(1)乃至(6)の工程によって製作されている
ことを特徴とするものである。
(1) A step-like recess for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers are provided on the upper surface around the recess from the stepped portion of the recess to the outer peripheral portion of the upper surface. Forming a metallized metal layer on the upper surface of which a metallization layer for connection connecting at least one of the metallized wiring layers and the metallized metal layer is formed, and (2) a part of the metallized layer for connection. And (3) attaching the other ends of a plurality of external lead terminals, one end of which is commonly connected to the connecting member, to each metallized wiring layer, and (4) the metallized wiring. A metal layer, a metallized metal layer, a metallized layer for connection, and an external lead terminal, and a plating metal layer is deposited on the exposed surfaces of the outer lead terminals by electrolytic plating. The step of grinding and removing the layer where the layer is adhered to electrically separate the metallized wiring layer and the metallized metal layer, and (6) the step of cutting and separating each external lead terminal from the connecting member. Has a stepped concave portion for accommodating a semiconductor element on the upper surface, and a plurality of metallized wiring layers are deposited from the step portion of the concave portion to the outer peripheral portion of the upper surface, and a frame-shaped metallized layer is formed on the upper surface around the concave portion. Semiconductor device housing including an insulating substrate having a metal layer deposited thereon, a plurality of external lead terminals attached to the metallized wiring layer, and a lid attached to the frame-shaped metallized metal layer A package for use, wherein the insulating base body to which the external lead terminals are attached is manufactured by the following steps (1) to (6).

【0010】(1)上面に半導体素子を収容するための
段状の凹部を有し、且つ該凹部の段差部より上面外周部
にかけて複数個のメタライズ配線層を、凹部周囲の上面
に枠状のメタライズ金属層を、上面に前記メタライズ配
線層の少なくとも1つと前記メタライズ金属層を接続す
る接続用メタライズ層を被着させた絶縁基体を形成する
工程と、(2)前記接続用メタライズ層の一部を間に隙
間を有する2つの絶縁層で被覆する工程と、(3)一端
が連結部材に共通に連結されている複数個の外部リード
端子の他端を各メタライズ配線層に取着させる工程と、
(4)前記メタライズ配線層、メタライズ金属層、接続
用メタライズ層及び外部リード端子の露出表面に電解メ
ッキ法によりメッキ金属層を被着させる工程と、(5)
前記接続用メタライズ層の一部を、前記2つの絶縁層の
隙間で研削除去し、前記メタライズ配線層とメタライズ
金属層とを電気的に独立させる工程と、(6)前記各外
部リード端子を連結部材より切断分離する工程
(1) A step-like recess for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers are provided on the upper surface around the recess from the stepped portion of the recess to the outer peripheral portion of the upper surface. Forming a metallized metal layer on the upper surface of which a metallization layer for connection connecting at least one of the metallized wiring layers and the metallized metal layer is formed, and (2) a part of the metallized layer for connection. And (3) attaching the other ends of the plurality of external lead terminals, one end of which is commonly connected to the connecting member, to each metallized wiring layer. ,
(4) A step of depositing a plating metal layer on the exposed surfaces of the metallized wiring layer, the metallized metal layer, the metallized layer for connection, and the external lead terminals by electrolytic plating, (5)
A step of grinding and removing a part of the connection metallization layer in a gap between the two insulating layers to electrically separate the metallization wiring layer and the metallization metal layer; and (6) connecting the external lead terminals. Process of cutting and separating from parts

【0011】[0011]

【作用】本発明の半導体素子収納用パッケージの製造方
法によれば、メタライズ配線層とメタライズ金属層とを
接続する接続用メタライズ層の一部を絶縁層で被覆、或
いは間に隙間を有する2つの絶縁層で被覆したことから
メタライズ配線層とメタライズ金属層の露出表面にメッ
キ金属層を被着させる際に接続用メタライズ層の露出表
面にメッキ金属層が被着され、接続用メタライズ層の一
部をリューター等の研削装置により研削除去する時に接
続用メタライズ層の表面に被着されたメッキ金属層の一
部が研削時の機械的応力によって剥がれようとしてもそ
の剥がれは前記絶縁層によって有効に防止され、その結
果、前記接続用メタライズ層とメッキ金属層との間に大
気中の水分が浸入するとともに該侵入した水分によって
接続用メタライズ層が腐食されることはなく、これによ
って絶縁基体と蓋体とから成る容器の気密封止を完全と
し、容器内部に収容する半導体素子を正常、且つ安定に
作動させることが可能となる。
According to the method of manufacturing a package for housing a semiconductor device of the present invention, two metallization layers for connection, which connect the metallized wiring layer and the metallized metal layer, are covered with an insulating layer or have two gaps between them. When the plated metal layer is deposited on the exposed surfaces of the metallized wiring layer and the metallized metal layer because it is covered with an insulating layer, the plated metal layer is deposited on the exposed surface of the metallized layer for connection, and a part of the metallized layer for connection Even if part of the plated metal layer adhered to the surface of the metallizing layer for connection is peeled off by the mechanical stress during grinding when it is ground and removed by a grinding device such as a router, the peeling is effectively prevented by the insulating layer. As a result, moisture in the atmosphere enters between the metallizing layer for connection and the plated metal layer, and the metallizing layer for connection is formed by the infiltrated water. There is not to be corroded, whereby the complete hermetic sealing of the container made of the insulating base and the lid, the semiconductor element housed in the container properly, it is possible to stably operate.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の製造方法によって製作される半導体
素子収納用パッケージの一実施例を示し、1は絶縁基
体、2は蓋体である。この絶縁基体1と蓋体2とで半導
体素子3を収容する容器4が構成される。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a semiconductor element housing package manufactured by the manufacturing method of the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.

【0013】前記絶縁基体1は、酸化アルミニウム質焼
結体、ムライト質焼結体、窒化アルミニウム質焼結体、
炭化珪素質焼結体、ガラスセラミックス等の電気絶縁材
料から成り、その上面中央部に半導体素子が収容される
段状の凹部1aが形成されており、該凹部1a底面には
半導体素子3がガラス、樹脂、ろう材等の接着剤を介し
て接着固定される。
The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or glass ceramics, and a step-like recess 1a for accommodating a semiconductor element is formed in the center of the upper surface thereof. , And is fixed by adhesion through an adhesive such as resin or brazing material.

【0014】また前記絶縁基体1はその凹部1aの段差
部から内部を通り上面外周部にかけて導出する複数個の
メタライズ配線層5を有しており、該メタライズ配線層
5の凹部1aの段差部に位置する領域には半導体素子3
の各電極がボンディングワイヤー6を介して電気的に接
続され、また絶縁基体1の上面外周部に導出する部位に
は外部電気回路に接続される外部リード端子7が銀ろう
等のろう材を介して取着される。
The insulating substrate 1 has a plurality of metallized wiring layers 5 extending from the stepped portion of the recess 1a through the inside to the outer peripheral portion of the upper surface. The metallized wiring layer 5 has a stepped portion of the recessed portion 1a. The semiconductor element 3 is located in the area
Are electrically connected to each other via bonding wires 6, and external lead terminals 7 connected to an external electric circuit are connected to an external electric circuit through a brazing material such as silver brazing material. Be attached.

【0015】前記メタライズ配線層5はタングステン、
モリブデン、マンガン、パラジウム、銀、銅等の金属か
ら成り、半導体素子3の各電極を外部リード端子7に接
続する作用を為す。
The metallized wiring layer 5 is made of tungsten,
It is made of a metal such as molybdenum, manganese, palladium, silver, and copper, and has a function of connecting each electrode of the semiconductor element 3 to the external lead terminal 7.

【0016】また前記メタライズ配線層5に取着される
外部リード端子7は半導体素子3の各電極を所定の外部
電気回路に接続する作用を為し、鉄ーニッケルーコバル
ト合金や鉄ーニッケル合金等の金属材料で形成されてい
る。
The external lead terminals 7 attached to the metallized wiring layer 5 have the function of connecting the respective electrodes of the semiconductor element 3 to a predetermined external electric circuit, such as iron-nickel-cobalt alloy or iron-nickel alloy. It is made of metal material.

【0017】更に前記絶縁基体1はその上面で凹部1a
周辺に枠状のメタライズ金属層8が被着されており、該
メタライズ金属層8には金属製の蓋体2が金ー錫ロウ材
等から成る封止材を介して接合されるようになってい
る。
Further, the insulating substrate 1 has a recess 1a on its upper surface.
A frame-shaped metallized metal layer 8 is attached to the periphery, and the metal lid 2 is bonded to the metallized metal layer 8 via a sealing material made of gold-tin brazing material or the like. ing.

【0018】前記枠状のメタライズ金属層8はタングス
テン、モリブデン、マンガン、パラジウム、銀、銅等の
金属から成り、蓋体2を絶縁基体1に接合させる際の下
地金属層として作用する。
The frame-shaped metallized metal layer 8 is made of a metal such as tungsten, molybdenum, manganese, palladium, silver and copper, and acts as a base metal layer when the lid 2 is bonded to the insulating base 1.

【0019】尚、前記絶縁基体1に被着させたメタライ
ズ配線層5及びメタライズ金属層8はその露出表面にニ
ッケル、金等の耐蝕性に優れ、且つボンディングワイヤ
ー及び封止材との接合性に優れるメッキ金属層9が従来
周知の電解メッキ法により被着されており、該メッキ金
属層9によりメタライズ配線層5及びメタライズ金属層
8が酸化腐食するのが有効に防止されるとともに前記メ
タライズ配線層5とボンディングワイヤー6との接合及
び前記メタライズ金属層8と蓋体2との接合が容易、且
つ強固なものとなっている。
The metallized wiring layer 5 and the metallized metal layer 8 deposited on the insulating substrate 1 have excellent corrosion resistance against nickel, gold, etc. on their exposed surfaces, and have good bonding properties with bonding wires and sealing materials. An excellent plating metal layer 9 is deposited by a conventionally known electrolytic plating method, and the plating metal layer 9 effectively prevents the metallized wiring layer 5 and the metallized metal layer 8 from being oxidized and corroded, and the metallized wiring layer The bonding between the bonding wire 5 and the bonding wire 6 and the bonding between the metallized metal layer 8 and the lid 2 are easy and strong.

【0020】かくして、この半導体素子収納用パッケー
ジによれば、絶縁基体1の凹部1a底面に半導体素子3
をガラス、樹脂、ろう材等の接着剤を介して接着固定す
るとともに該半導体素子3の各電極をメタライズ配線層
5にボンディングワイヤー6を介して電気的に接続し、
しかる後、絶縁基体1の上面に被着させた枠状のメタラ
イズ金属層8に蓋体2を金−錫ろう材等の封止材を介し
て接合させ、絶縁基体1と蓋体2とから成る容器4内部
に半導体素子3を気密に収容することによって最終製品
としての半導体装置となる。
Thus, according to this semiconductor element housing package, the semiconductor element 3 is formed on the bottom surface of the recess 1a of the insulating base 1.
Is bonded and fixed through an adhesive such as glass, resin, or a brazing material, and each electrode of the semiconductor element 3 is electrically connected to the metallized wiring layer 5 through a bonding wire 6.
Thereafter, the lid 2 is joined to the frame-shaped metallized metal layer 8 adhered to the upper surface of the insulating base 1 via a sealing material such as a gold-tin brazing material, and the insulating base 1 and the lid 2 are separated from each other. A semiconductor device as a final product is obtained by hermetically housing the semiconductor element 3 in the container 4 made of the above.

【0021】次に上述の半導体素子収納用パッケージの
外部リード端子が取着された絶縁基体の製造方法につい
て図2乃至図5に基づき説明する。まず、図2(a)
(b)示すように、上面に半導体素子を収容するための
段状の凹部1aを有し、且つ該凹部1aの段差部より上
面外周部にかけて複数個のメタライズ配線層5を、凹部
1a周囲の上面に枠状のメタライズ金属層8を、上面に
前記メタライズ配線層5の少なくとも1つと前記メタラ
イズ金属層8を接続する接続用メタライズ層10を被着
させた絶縁基体1を準備するとともに前記接続用メタラ
イズ層10の一部を絶縁層11で被覆する。
Next, a method of manufacturing the insulating base body to which the external lead terminals of the above-mentioned semiconductor element housing package are attached will be described with reference to FIGS. First, FIG.
As shown in (b), a stepped recess 1a for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers 5 are provided around the recess 1a from the step portion of the recess 1a to the outer peripheral portion of the upper surface. A frame-shaped metallized metal layer 8 is provided on the upper surface, and an insulating substrate 1 on which at least one of the metallized wiring layers 5 and a connection metallization layer 10 for connecting the metallized metal layer 8 are adhered to the upper surface is prepared and the connection is made. A part of the metallized layer 10 is covered with the insulating layer 11.

【0022】前記メタライズ配線層5、メタライズ金属
層8、接続用メタライズ層10及び絶縁層11が被着さ
れた絶縁基体1は、例えば酸化アルミニウム質焼結体か
ら成る場合、酸化アルミニウム、酸化珪素、酸化カルシ
ウム、酸化マグネシウム等の原料粉末に適当な有機バイ
ンダー、溶剤、可塑剤、分散剤等を添加混合して泥漿状
となすとともにこれを従来周知のドクターブレード法を
採用してシート状に成形して複数枚のセラミックグリー
ンシートを得、しかる後、前記セラミックグリーンシー
トに適当な打ち抜き加工を施すとともに該セラミックグ
リーンシートを上下に積層してセラミック生成形体とな
し、最後に前記セラミック生成形体を還元雰囲気中約1
600℃の温度で焼成することによって製作され、また
メタライズ配線層5、メタライズ金属層8及び接続用メ
タライズ層10は、例えばタングステン、モリブデン等
の金属粉末に適当な有機バインダー、可塑剤、溶剤を添
加混合して金属ペーストを得、これを絶縁基体1となる
セラミックグリーンシートに予めスクリーン印刷法によ
り所定パターンに印刷塗布しておくことによって絶縁基
体1の所定位置に所定パターンに被着形成される。
The insulating substrate 1 on which the metallized wiring layer 5, the metallized metal layer 8, the metallized layer for connection 10 and the insulating layer 11 are adhered is made of, for example, an aluminum oxide sintered body, aluminum oxide, silicon oxide, Appropriate organic binders, solvents, plasticizers, dispersants, etc. are added to and mixed with raw material powders of calcium oxide, magnesium oxide, etc. to form a slurry, and this is formed into a sheet using the conventionally known doctor blade method. To obtain a plurality of ceramic green sheets, and thereafter, the ceramic green sheets are appropriately punched, and the ceramic green sheets are laminated on top of each other to form a ceramic green body, and finally the ceramic green sheet is subjected to a reducing atmosphere. About 1
The metallized wiring layer 5, the metallized metal layer 8 and the connecting metallized layer 10 are manufactured by firing at a temperature of 600 ° C. For example, a metal powder such as tungsten or molybdenum is mixed with an appropriate organic binder, a plasticizer and a solvent. The metal paste is mixed to obtain a ceramic paste, which is printed and applied in advance to a predetermined pattern by a screen printing method on the ceramic green sheet to be the insulating substrate 1, so that the insulating paste is formed in a predetermined pattern on the insulating substrate 1.

【0023】更に前記絶縁層11は絶縁基体1と同質の
セラミック原料粉末に適当な有機バインダー、可塑剤、
溶剤を添加混合して絶縁ペーストを得、これを接続用メ
タライズ層の一部にスクリーン印刷法により印刷塗布し
ておくことによって被着される。
Further, the insulating layer 11 is made of a ceramic raw material powder having the same quality as that of the insulating substrate 1, and an appropriate organic binder, plasticizer,
A solvent is added and mixed to obtain an insulating paste, and the insulating paste is applied to a part of the metallizing layer for connection by screen printing by a screen printing method.

【0024】次に、図3(a)、(b)に示すように、
前記絶縁基体1に被着されたメタライズ配線層5で絶縁
基体1の上面外周部に導出した部位に、一端が枠状の連
結部材12により電気的に共通に接続された外部リード
端子7の他端を銀ろう等のろう材を介して取着する。
Next, as shown in FIGS. 3 (a) and 3 (b),
In addition to the external lead terminal 7, one end of which is electrically commonly connected by a frame-shaped connecting member 12 to a portion of the metallized wiring layer 5 attached to the insulating substrate 1 which is led to the outer peripheral portion of the upper surface of the insulating substrate 1. Attach the ends with a brazing material such as silver wax.

【0025】前記外部リード端子7は、鉄−ニッケル合
金や鉄ーニッケルーコバルト合金等の金属材料から成
り、該鉄−ニッケル合金等のインゴット(塊)に圧延加
工法や打ち抜き加工法、エッチング加工法等、従来周知
の金属加工法を施すことによって一端が連結部材12に
取着された状態で形成される。
The external lead terminal 7 is made of a metal material such as an iron-nickel alloy or an iron-nickel-cobalt alloy, and the ingot (lump) of the iron-nickel alloy or the like is rolled, punched or etched. It is formed in a state in which one end is attached to the connecting member 12 by performing a conventionally known metal processing method such as a method.

【0026】また前記外部リード端子7のメタライズ配
線層5への取着はメタライズ配線層5上に間に銀ろう箔
を挟んで外部リード端子7を載置させ、しかる後、前記
銀ろう箔を約850℃の温度で溶融させることによって
行われる。
The external lead terminals 7 are attached to the metallized wiring layer 5 by placing the external lead terminals 7 on the metallized wiring layer 5 with a silver brazing foil sandwiched between them. It is performed by melting at a temperature of about 850 ° C.

【0027】次に図4(a)、(b)に示すように、前
記メタライズ配線層5及びメタライズ金属層8の表面に
電解メッキ法によりメッキ金属層9を被着させる。
Next, as shown in FIGS. 4A and 4B, a plating metal layer 9 is deposited on the surfaces of the metallized wiring layer 5 and the metallized metal layer 8 by electrolytic plating.

【0028】前記メタライズ配線層5及びメタライズ金
属層8へのメッキ金属層9の被着は外部リード端子7が
取着された絶縁基体1をニッケルや金の電解メッキ液中
に浸漬するとともに外部リード端子7を介してメタライ
ズ配線層5及びメタライズ金属層8に電解メッキの為の
メッキ電力を印加することによって行われる。この場
合、メタライズ配線層5とメタライズ金属層8は接続用
メタライズ層10によって電気的に接続されており、ま
た各メタライズ配線層5は外部リード端子7の連結部材
12によって電気的に接続されているため外部リード端
子7にメッキ電力を印加するだけで全てのメタライズ配
線層5及びメタライズ金属層8にメッキ金属層9を被着
させることができる。
The metallized wiring layer 5 and the metallized metal layer 8 are coated with the plated metal layer 9 by immersing the insulating substrate 1 with the external lead terminals 7 in an electrolytic plating solution of nickel or gold and external leads. This is performed by applying plating power for electrolytic plating to the metallized wiring layer 5 and the metallized metal layer 8 via the terminal 7. In this case, the metallized wiring layer 5 and the metallized metal layer 8 are electrically connected by the connecting metallized layer 10, and each metallized wiring layer 5 is electrically connected by the connecting member 12 of the external lead terminal 7. Therefore, the plating metal layer 9 can be deposited on all the metallized wiring layers 5 and the metallized metal layers 8 simply by applying the plating power to the external lead terminals 7.

【0029】最後に図5(a)、(b)に示すように、
前記接続用メタライズ層10の絶縁層11で被覆された
部位をリューター等の研削装置を用いて研削除去し、メ
タライズ配線層5とメタライズ金属層8とを電気的に独
立させることによって図1に示す外部リード端子7が取
着された絶縁基体1が完成する。
Finally, as shown in FIGS. 5 (a) and 5 (b),
The portion of the connection metallization layer 10 covered with the insulating layer 11 is ground and removed by using a grinding device such as a router to electrically separate the metallized wiring layer 5 and the metallized metal layer 8 from each other, as shown in FIG. The insulating substrate 1 to which the external lead terminals 7 are attached is completed.

【0030】尚、この場合、リューター等の研削装置を
用いて研削除去される接続用メタライズ層10はその表
面が絶縁層11が被覆されているためメッキ金属層9は
被着されておらず、従って、接続用メタライズ層を研削
装置で研削除去してもメッキ金属層9が研削の機械的応
力により接続用メタライズ層10から剥離することは一
切なく、その結果、接続用メタライズ層10とメッキ金
属層9との間に大気中の水分が浸入し、接続用メタライ
ズ層10を腐食させるとともに該腐食がメタライズ金属
層8にまで進行して絶縁基体1と蓋体2とから成る容器
4の気密封止を破ることもない。
In this case, since the surface of the connecting metallized layer 10 ground and removed by using a grinder such as a router is covered with the insulating layer 11, the plated metal layer 9 is not deposited, Therefore, even if the connection metallization layer is ground and removed by a grinding device, the plated metal layer 9 is never separated from the connection metallization layer 10 due to the mechanical stress of grinding, and as a result, the connection metallization layer 10 and the plated metal layer are not separated. Moisture in the atmosphere penetrates into the layer 9 to corrode the connection metallization layer 10 and the corrosion progresses to the metallization metal layer 8 to hermetically seal the container 4 composed of the insulating substrate 1 and the lid 2. It won't break.

【0031】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では接続用
メタライズ層の一部に絶縁層を被着させておき、該絶縁
層の被着された領域の接続用メタライズ層をリューター
等の研削装置を用いて研削除去し、メタライズ配線層と
メタライズ金属層の電気的独立を図ったが、これを図6
(a)(b)に示すように、接続用メタライズ層10の
表面に間に隙間を有する2つの絶縁層11a、11bを
被着させておき、2つの絶縁層11a、11bの隙間に
位置する接続用メタライズ層10をリューター等の研削
装置を用いて研削除去しメタライズ配線層5とメタライ
ズ金属層8との電気的独立を図ってもよい。この場合、
接続用メタライズ層10の表面に被着されるメッキ金属
層は研削の機械的応力により接続用メタライズ層10よ
り剥離するのが2つの絶縁層11a、11bによって有
効に防止され、その結果、接続用メタライズ層10とメ
ッキ金属層との間に大気中の水分が浸入し、接続用メタ
ライズ層10を腐食させるとともに該腐食がメタライズ
金属層8にまで進行して絶縁基体と蓋体とから成る容器
の気密封止を破ることはない。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the metallization layer for connection is used. An insulating layer is partially deposited, and the connecting metallization layer in the deposited region of the insulating layer is ground and removed using a grinder such as a router to electrically separate the metallized wiring layer and the metallized metal layer. I tried to
As shown in (a) and (b), two insulating layers 11a and 11b having a gap between them are deposited on the surface of the connecting metallization layer 10 and are located in the gap between the two insulating layers 11a and 11b. The metallized wiring layer 5 and the metallized metal layer 8 may be electrically isolated by grinding and removing the connecting metallization layer 10 by using a grinding device such as a router. in this case,
The two insulating layers 11a and 11b effectively prevent the plated metal layer deposited on the surface of the connection metallization layer 10 from being separated from the connection metallization layer 10 due to mechanical stress of grinding. Moisture in the atmosphere penetrates between the metallized layer 10 and the plated metal layer to corrode the connecting metallized layer 10 and the corrosion progresses to the metallized metal layer 8 so that the container including the insulating base and the lid is It does not break the hermetic seal.

【0032】[0032]

【発明の効果】本発明の半導体素子収納用パッケージの
製造方法によれば、メタライズ配線層とメタライズ金属
層とを接続する接続用メタライズ層の一部を絶縁層で被
覆、或いは間に隙間を有する2つの絶縁層で被覆したこ
とからメタライズ配線層とメタライズ金属層の露出表面
にメッキ金属層を被着させる際に接続用メタライズ層の
露出表面にメッキ金属層が被着され、接続用メタライズ
層の一部をリューター等の研削装置により研削除去する
時に接続用メタライズ層の表面に被着されたメッキ金属
層の一部が研削時の機械的応力によって剥がれようとし
てもその剥がれは前記絶縁層によって有効に防止され、
その結果、前記接続用メタライズ層とメッキ金属層との
間に大気中の水分が浸入するとともに該侵入した水分に
よって接続用メタライズ層が腐食されることはなく、こ
れによって絶縁基体と蓋体とから成る容器の気密封止を
完全とし、容器内部に収容する半導体素子を正常、且つ
安定に作動させることが可能となる。
According to the method of manufacturing a package for accommodating semiconductor elements of the present invention, a part of the metallizing layer for connection connecting the metallized wiring layer and the metallized metal layer is covered with an insulating layer or has a gap therebetween. Since the metallized wiring layer and the metallized metal layer are covered with two insulating layers, when the plated metal layer is deposited on the exposed surfaces of the metallized wiring layer and the metallized metal layer, the plated metal layer is deposited on the exposed surface of the metallized layer for connection. Even if part of the plated metal layer deposited on the surface of the metallizing layer for connection is peeled off by mechanical stress during grinding when part of it is ground and removed by a grinding device such as a router, the peeling is effective by the insulating layer. Is prevented by
As a result, moisture in the atmosphere does not enter between the metallizing layer for connection and the plated metal layer, and the metallizing layer for connection does not corrode due to the intruded water. It becomes possible to completely hermetically seal the container formed, and to normally and stably operate the semiconductor element housed inside the container.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)及び(b)は本発明の製造方法によって
製造される半導体素子収納用パッケージの一実施例を示
す断面図及び使用される絶縁基体の平面図である。
1A and 1B are a cross-sectional view showing an embodiment of a package for housing a semiconductor device manufactured by a manufacturing method of the present invention and a plan view of an insulating base used.

【図2】(a)及び(b)は本発明の半導体素子収納用
パッケージの製造方法を説明するための断面図及び平面
図である。
2 (a) and 2 (b) are a cross-sectional view and a plan view for explaining a method for manufacturing a semiconductor element housing package of the present invention.

【図3】(a)及び(b)は本発明の半導体素子収納用
パッケージの製造方法を説明するための断面図及び平面
図である。
3 (a) and 3 (b) are a cross-sectional view and a plan view for explaining a method for manufacturing a semiconductor element housing package of the present invention.

【図4】(a)及び(b)は本発明の半導体素子収納用
パッケージの製造方法を説明するための断面図及び平面
図である。
4 (a) and 4 (b) are a cross-sectional view and a plan view for explaining a method for manufacturing a semiconductor element housing package of the present invention.

【図5】(a)及び(b)は本発明の半導体素子収納用
パッケージの製造方法を説明するための断面図及び平面
図である。
5 (a) and 5 (b) are a cross-sectional view and a plan view for explaining a method for manufacturing a semiconductor element housing package of the present invention.

【図6】(a)及び(b)は本発明の半導体素子収納用
パッケージの製造方法の他の実施例を説明するための断
面図及び平面図である。
6 (a) and 6 (b) are a cross-sectional view and a plan view for explaining another embodiment of the method for manufacturing a semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・蓋体 3・・・・半導体素子 4・・・・容器 5・・・・メタライズ配線層 7・・・・外部リード端子 8・・・・メタライズ金属層 9・・・・メッキ金属層 10・・・・接続用メタライズ層 11・・・・絶縁層 12・・・・連結部材 1 ... Insulating substrate 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallized wiring layer 7 ... External lead terminal 8 ... Metallized metal Layer 9 ... Plating metal layer 10 ... Connection metallization layer 11 ... Insulating layer 12 ... Connecting member

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子を収容するための段状の
凹部を有し、且つ該凹部の段差部から上面外周部にかけ
て複数個のメタライズ配線層が被着されるとともに凹部
周囲の上面に枠状のメタライズ金属層が被着されている
絶縁基体と、前記メタライズ配線層に取着されている複
数個の外部リード端子と、前記枠状のメタライズ金属層
に取着される蓋体とから成る半導体素子収納用パッケー
ジであって、前記外部リード端子の取着された絶縁基体
が下記(1)乃至(6)の工程によって製作されている
ことを特徴とする半導体素子収納用パッケージの製造方
法。 (1)上面に半導体素子を収容するための段状の凹部を
有し、且つ該凹部の段差部より上面外周部にかけて複数
個のメタライズ配線層を、凹部周囲の上面に枠状のメタ
ライズ金属層を、上面に前記メタライズ配線層の少なく
とも1つと前記メタライズ金属層を接続する接続用メタ
ライズ層を被着させた絶縁基体を形成する工程と、
(2)前記接続用メタライズ層の一部を絶縁層で被覆す
る工程と、(3)一端が連結部材に共通に連結されてい
る複数個の外部リード端子の他端を各メタライズ配線層
に取着させる工程と、(4)前記メタライズ配線層、メ
タライズ金属層、接続用メタライズ層及び外部リード端
子の露出表面に電解メッキ法によりメッキ金属層を被着
させる工程と、(5)前記接続用メタライズ層の一部
を、前記絶縁層が被着されている部位で研削除去し、前
記メタライズ配線層とメタライズ金属層とを電気的に独
立させる工程と、(6)前記各外部リード端子を連結部
材より切断分離する工程
1. A stepped recess for accommodating a semiconductor element is provided on an upper surface, and a plurality of metallized wiring layers are deposited from a step portion of the recess to an outer peripheral portion of the upper surface, and an upper surface around the recess is provided. From an insulating substrate to which a frame-shaped metallized metal layer is applied, a plurality of external lead terminals attached to the metallized wiring layer, and a lid attached to the framed metallized metal layer. A method of manufacturing a package for accommodating a semiconductor device, characterized in that the insulating substrate to which the external lead terminals are attached is manufactured by the following steps (1) to (6). . (1) A step-like recess for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers are provided from the step portion of the recess to the outer peripheral portion of the upper surface, and a frame-shaped metallized metal layer is provided on the upper surface around the recess. Forming an insulating substrate on the upper surface of which a metallizing layer for connection connecting at least one of the metallized wiring layers and the metallized metal layer is deposited,
(2) a step of covering a part of the metallization layer for connection with an insulating layer, and (3) taking the other ends of a plurality of external lead terminals, one end of which is commonly connected to a connecting member, to each metallized wiring layer. And (4) depositing a plating metal layer on the exposed surfaces of the metallized wiring layer, the metallized metal layer, the metallization layer for connection, and the external lead terminals by electrolytic plating, and (5) the metallization for connection. A step of grinding and removing a part of the layer at a portion where the insulating layer is adhered to electrically separate the metallized wiring layer and the metallized metal layer, and (6) a connecting member for connecting the external lead terminals. Process of cutting and separating
【請求項2】上面に半導体素子を収容するための段状の
凹部を有し、且つ該凹部の段差部から上面外周部にかけ
て複数個のメタライズ配線層が被着されるとともに凹部
周囲の上面に枠状のメタライズ金属層が被着されている
絶縁基体と、前記メタライズ配線層に取着されている複
数個の外部リード端子と、前記枠状のメタライズ金属層
に取着される蓋体とから成る半導体素子収納用パッケー
ジであって、前記外部リード端子の取着された絶縁基体
が下記(1)乃至(6)の工程によって製作されている
ことを特徴とする半導体素子収納用パッケージの製造方
法。 (1)上面に半導体素子を収容するための段状の凹部を
有し、且つ該凹部の段差部より上面外周部にかけて複数
個のメタライズ配線層を、凹部周囲の上面に枠状のメタ
ライズ金属層を、上面に前記メタライズ配線層の少なく
とも1つと前記メタライズ金属層を接続する接続用メタ
ライズ層を被着させた絶縁基体を形成する工程と、
(2)前記接続用メタライズ層の一部を間に隙間を有す
る2つの絶縁層で被覆する工程と、(3)一端が連結部
材に共通に連結されている複数個の外部リード端子の他
端を各メタライズ配線層に取着させる工程と、(4)前
記メタライズ配線層、メタライズ金属層、接続用メタラ
イズ層及び外部リード端子の露出表面に電解メッキ法に
よりメッキ金属層を被着させる工程と、(5)前記接続
用メタライズ層の一部を、前記2つの絶縁層の隙間で研
削除去し、前記メタライズ配線層とメタライズ金属層と
を電気的に独立させる工程と、(6)前記各外部リード
端子を連結部材より切断分離する工程
2. A stepped concave portion for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers are deposited from the step portion of the concave portion to the outer peripheral portion of the upper surface and the upper surface around the concave portion is covered. From an insulating substrate to which a frame-shaped metallized metal layer is applied, a plurality of external lead terminals attached to the metallized wiring layer, and a lid attached to the framed metallized metal layer. A method of manufacturing a package for accommodating a semiconductor device, characterized in that the insulating substrate to which the external lead terminals are attached is manufactured by the following steps (1) to (6). . (1) A step-like recess for accommodating a semiconductor element is provided on the upper surface, and a plurality of metallized wiring layers are provided from the step portion of the recess to the outer peripheral portion of the upper surface, and a frame-shaped metallized metal layer is provided on the upper surface around the recess. Forming an insulating substrate on the upper surface of which a metallizing layer for connection connecting at least one of the metallized wiring layers and the metallized metal layer is deposited,
(2) A step of covering a part of the connection metallization layer with two insulating layers having a gap therebetween, and (3) the other ends of the plurality of external lead terminals whose one end is commonly connected to the connecting member. And (4) depositing a plating metal layer on the exposed surfaces of the metallized wiring layer, the metallized metal layer, the connecting metallized layer and the external lead terminals by electrolytic plating. (5) A step of grinding and removing a part of the connection metallization layer in the gap between the two insulating layers to electrically separate the metallization wiring layer and the metallization metal layer, and (6) each of the external leads. Process of cutting and separating terminals from connecting members
JP16879195A 1995-07-04 1995-07-04 Manufacturing method of semiconductor device storage package Expired - Fee Related JP3210838B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16879195A JP3210838B2 (en) 1995-07-04 1995-07-04 Manufacturing method of semiconductor device storage package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16879195A JP3210838B2 (en) 1995-07-04 1995-07-04 Manufacturing method of semiconductor device storage package

Publications (2)

Publication Number Publication Date
JPH0922958A true JPH0922958A (en) 1997-01-21
JP3210838B2 JP3210838B2 (en) 2001-09-25

Family

ID=15874546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16879195A Expired - Fee Related JP3210838B2 (en) 1995-07-04 1995-07-04 Manufacturing method of semiconductor device storage package

Country Status (1)

Country Link
JP (1) JP3210838B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317602A (en) * 2004-04-27 2005-11-10 Kyocera Corp Wiring board and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317602A (en) * 2004-04-27 2005-11-10 Kyocera Corp Wiring board and manufacturing method therefor

Also Published As

Publication number Publication date
JP3210838B2 (en) 2001-09-25

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