JPH07297530A - Wiring substrate - Google Patents

Wiring substrate

Info

Publication number
JPH07297530A
JPH07297530A JP6090973A JP9097394A JPH07297530A JP H07297530 A JPH07297530 A JP H07297530A JP 6090973 A JP6090973 A JP 6090973A JP 9097394 A JP9097394 A JP 9097394A JP H07297530 A JPH07297530 A JP H07297530A
Authority
JP
Japan
Prior art keywords
connection pad
external lead
metallized
insulating substrate
brazing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6090973A
Other languages
Japanese (ja)
Inventor
Toshifumi Kiyohara
敏史 清原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP6090973A priority Critical patent/JPH07297530A/en
Publication of JPH07297530A publication Critical patent/JPH07297530A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To provide a wiring substrate capable of firmly fitting an external lead terminal on an insulating basic without generating a crack or a fracture in the insulating basic. CONSTITUTION:In this wiring substrate, on a surface of an insulating base 1 made of a ceramic having a metallized wire layer 2, a connection pad 7 connecting electrically with the metallized wire layer 2 is provided, and also an external lead terminal 3 is soldered in the connection pad 7. The connection pad 7 is formed so that a plurality of metallized layers 7a, 7b having different outer dimensions are laminated and adhered to the surface of the insulating base 1 according to the descending order of the outer dimensions.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子収納用パッケ
ージや混成集積回路装置等に用いられる配線基板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for a semiconductor element housing package, a hybrid integrated circuit device, or the like.

【0002】[0002]

【従来の技術】従来、配線基板、例えば、半導体素子を
収容する半導体素子収納用パッケージに使用される配線
基板は一般に、酸化アルミニウム質焼結体、ムライト質
焼結体、ガラスセラミックス焼結体、窒化アルミニウム
質焼結体等の電気絶縁性のセラミックスから成り、その
上面の略中央部に半導体素子を収容するための凹部を有
する絶縁基体と、前記絶縁基体の凹部周辺から下面にか
けて導出されているタングステン、モリブデン、マンガ
ン等の高融点金属粉末から成るメタライズ配線層と、前
記絶縁基体下面に取着され、メタライズ配線層と電気的
に接続している鉄ーニッケルーコバルト合金や鉄ーニッ
ケル合金等から成る外部リード端子とで構成されてお
り、絶縁基体の凹部底面に半導体素子をガラス、樹脂、
ロウ材等の接着剤を介して接着固定するとともに半導体
素子の各電極を凹部周辺に位置するメタライズ配線層に
ボンディングワイヤを介して電気的に接続し、しかる
後、前記絶縁基体の上面に金属やセラミックス等から成
る蓋体を絶縁基体の凹部を塞ぐようにガラス、樹脂、ロ
ウ材等から成る封止材を介して接合させ、絶縁基体の凹
部内に半導体素子を気密に収容することによって最終製
品としての半導体装置となる。
2. Description of the Related Art Conventionally, a wiring board, for example, a wiring board used for a semiconductor element housing package for housing a semiconductor element is generally an aluminum oxide sintered body, a mullite sintered body, a glass ceramics sintered body, An insulating base made of an electrically insulating ceramics such as an aluminum nitride sintered body and having a recess for accommodating a semiconductor element in a substantially central portion of its upper surface, and a portion extending from the periphery of the recess of the insulating base to the lower surface. From a metallized wiring layer made of a refractory metal powder such as tungsten, molybdenum, or manganese, and an iron-nickel-cobalt alloy or an iron-nickel alloy attached to the lower surface of the insulating substrate and electrically connected to the metallized wiring layer. The semiconductor element is formed on the bottom surface of the concave portion of the insulating substrate by glass, resin,
The electrodes are bonded and fixed via an adhesive such as a brazing material, and each electrode of the semiconductor element is electrically connected to a metallized wiring layer located in the periphery of the recess via a bonding wire. A lid made of ceramics or the like is bonded via a sealing material made of glass, resin, brazing material, etc. so as to cover the recess of the insulating base, and the semiconductor element is hermetically housed in the recess of the insulating base to obtain a final product. As a semiconductor device.

【0003】尚、前記絶縁基体への外部リード端子の取
着は、図3に示すように、絶縁基体11の下面に、一部が
メタライズ配線層12と電気的に接続する円形状の接続パ
ッド13を被着させておき、該接続パッド13に外部リード
端子14の一端を銀ロウ等のロウ材15を介しロウ付けする
ことによって行われている。
As shown in FIG. 3, the external lead terminals are attached to the insulating base by circular connection pads, a part of which is electrically connected to the metallized wiring layer 12 on the lower surface of the insulating base 11. This is done by depositing 13 and brazing one end of the external lead terminal 14 to the connection pad 13 via a brazing material 15 such as silver brazing.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、この従
来の配線基板においては、外部リード端子を接続パッド
にロウ付けするロウ材が接続パッドの略全面に接合する
とともに固化時に大きく収縮すること及び絶縁基体が脆
弱で、且つ引っ張り力に対する機械的強度が弱いセラミ
ックスで形成されていること等から、接続パッドに外部
リード端子を銀ロウ等のロウ材を介してロウ付けする
と、ロウ材の固化収縮に伴う引っ張り力が接続パッドの
外周部に大きく作用して接続パッドの外周部に位置する
絶縁基体にクラックや割れを発生させ、半導体素子の気
密封止の信頼性や外部リード端子の絶縁基体への取着の
信頼性が大きく低下するという欠点を有していた。
However, in this conventional wiring board, the brazing material for brazing the external lead terminals to the connection pads is bonded to substantially the entire surface of the connection pads and greatly contracts during solidification, and the insulating substrate. Is fragile and is formed of ceramics that has low mechanical strength against pulling force. Therefore, when external lead terminals are brazed to a connecting pad via a brazing material such as silver brazing, the brazing material is solidified and shrinks. The tensile force largely acts on the outer peripheral portion of the connection pad to cause cracks or breaks in the insulating substrate located on the outer peripheral portion of the connection pad, which may lead to reliability of hermetic sealing of the semiconductor element and attachment of the external lead terminal to the insulating substrate. It has a drawback that the reliability of the clothes is greatly reduced.

【0005】[0005]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は絶縁基体に外部リード端子を、該絶縁基
体にクラックや割れを発生することなく強固に取着する
ことができる配線基板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to firmly attach an external lead terminal to an insulating substrate without causing cracks or breaks in the insulating substrate. To provide a wiring board.

【0006】[0006]

【課題を解決するための手段】本発明は、メタライズ配
線層を有するセラミックス製絶縁基体の表面に、前記メ
タライズ配線層と電気的に接続される接続パッドを設け
るとともに該接続パッドに外部リード端子をロウ付けし
て成る配線基板であって、前記接続パッドは外形寸法の
異なる複数のメタライズ層を、外形寸法の大きいものよ
り順に絶縁基体の表面に被着積層させて形成されている
ことを特徴とするものである。
According to the present invention, a connection pad electrically connected to the metallized wiring layer is provided on the surface of a ceramic insulating substrate having a metallized wiring layer, and an external lead terminal is provided on the connection pad. A wiring board formed by brazing, wherein the connection pad is formed by depositing and laminating a plurality of metallized layers having different outer dimensions on the surface of an insulating substrate in order from the outer layer having the largest outer dimension. To do.

【0007】[0007]

【作用】本発明の配線基板によれば、外部リード端子が
ロウ付けされる接続パッドを、外形寸法の異なる複数の
メタライズ層を、外形寸法の大きいものより順に絶縁基
体の表面に被着積層させることによって形成したことか
ら、接続パッドに外部リード端子をロウ材を介してロウ
付けする際、ロウ材は外形寸法の小さいメタライズ層に
接合して外形寸法が最も大きく絶縁基体に直接接触する
メタライズ層に接合することはなく、その結果、ロウ材
の固化収縮に伴う引っ張り力は接続パッドの外周部に大
きく作用することはなく、接続パッドの外周部に位置す
る絶縁基体にクラックや割れ等が発生するのを皆無とし
て、半導体素子の気密封止の信頼性や外部リード端子の
絶縁基体への取着の信頼性を極めて高いものとなすこと
ができる。
According to the wiring board of the present invention, the connection pads to which the external lead terminals are brazed are formed by laminating a plurality of metallized layers having different outer dimensions on the surface of the insulating substrate in order of increasing outer dimensions. Therefore, when the external lead terminal is brazed to the connection pad via the brazing material, the brazing material is bonded to the metallization layer having the smallest outer dimension and directly contacts the insulating substrate having the largest outer dimension. As a result, the tensile force due to the solidification shrinkage of the brazing material does not significantly act on the outer peripheral portion of the connection pad, and cracks or cracks occur in the insulating substrate located on the outer peripheral portion of the connection pad. By omitting this, the reliability of hermetically sealing the semiconductor element and the reliability of attaching the external lead terminal to the insulating substrate can be made extremely high.

【0008】[0008]

【実施例】次に本発明を添付図面に示す実施例に基づき
詳細に説明する。図1及び図2は本発明の配線基板を半
導体素子を収容する半導体素子収納用パッケージに適用
した場合の一実施例を示し、1は絶縁基体、2は絶縁基
体1に被着されたメタライズ配線層、3はメタライズ配
線層2にロウ材を介してロウ付け取着された外部リード
端子である。この絶縁基体1に被着されたメタライズ配
線層2に外部リード端子3を取着したものが配線基板A
となる。
The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. 1 and 2 show an embodiment in which the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, 1 is an insulating base, and 2 is a metallized wiring adhered to the insulating base 1. Layers 3 are external lead terminals brazed and attached to the metallized wiring layer 2 via a brazing material. The wiring board A is obtained by attaching the external lead terminals 3 to the metallized wiring layer 2 attached to the insulating substrate 1.
Becomes

【0009】前記絶縁基体1はその上面中央部に半導体
素子4を収容するための空所を形成する凹部1aが設け
てあり、該凹部1a底面には半導体素子4がガラス、樹
脂、ロウ材等の接着剤を介して接着固定される。
The insulating substrate 1 is provided with a recess 1a at the center of its upper surface for forming a space for accommodating the semiconductor element 4, and the semiconductor element 4 is provided on the bottom surface of the recess 1a with glass, resin, brazing material or the like. The adhesive is fixed through the adhesive.

【0010】前記絶縁基体1は酸化アルミニウム質焼結
体、ムライト質焼結体、ガラスセラミックス焼結体、窒
化アルミニウム質焼結体等の電気絶縁性のセラミックス
から成り、例えば酸化アルミニウム質焼結体から成る場
合は、アルミナ、シリカ、カルシア、マグネシア等のセ
ラミック原料粉末に適当な有機溶剤、溶媒を添加混合し
て泥漿状となすとともに該泥漿物を従来周知のドクター
ブレード法やカレンダーロール法等を採用することによ
ってセラミックグリーンシート(セラミック生シート)
と成し、しかる後、前記セラミックグリーンシートに適
当な打ち抜き加工を施すとともにこれを複数枚積層し、
約1600℃の温度で焼成することによって製作され
る。
The insulating substrate 1 is made of an electrically insulating ceramic such as an aluminum oxide sintered body, a mullite sintered body, a glass ceramic sintered body, or an aluminum nitride sintered body. For example, an aluminum oxide sintered body. In the case of consisting of alumina, silica, calcia, a suitable organic solvent to a ceramic raw material powder such as magnesia, a solvent is added and mixed to form a sludge, and the sludge is subjected to a conventionally known doctor blade method or calendar roll method. By adopting ceramic green sheet (ceramic green sheet)
After that, appropriate punching processing is applied to the ceramic green sheet and a plurality of these are laminated,
It is manufactured by firing at a temperature of about 1600 ° C.

【0011】また前記絶縁基体1はその凹部1a周辺か
ら下面にかけて複数個のメタライズ配線層2が被着され
ており、該メタライズ配線層2の凹部1a周辺部には半
導体素子4の各電極がボンディングワイヤ5を介し電気
的に接続され、また下面に導出された部位には外部電気
回路と接続される外部リード端子3が電気的に接続され
ている。
The insulating substrate 1 is covered with a plurality of metallized wiring layers 2 from the periphery of the recess 1a to the lower surface, and the electrodes of the semiconductor element 4 are bonded to the periphery of the recess 1a of the metallized wiring layer 2. An external lead terminal 3 which is electrically connected via a wire 5 and which is connected to an external electric circuit is electrically connected to a portion led out to the lower surface.

【0012】前記絶縁基体1に被着させたメタライズ配
線層2はタングステン、モリブデン、マンガン等の高融
点金属粉末から成り、該メタライズ配線層2は外部電気
回路に接続される外部リード端子3に半導体素子4の各
電極を電気的に導通させる作用を為す。
The metallized wiring layer 2 deposited on the insulating substrate 1 is made of a refractory metal powder such as tungsten, molybdenum, or manganese, and the metallized wiring layer 2 is connected to an external electric circuit by a semiconductor on an external lead terminal 3. It serves to electrically connect each electrode of the element 4.

【0013】尚、前記メタライズ配線層2は例えば、タ
ングステン等の高融点金属粉末に適当な有機溶剤、溶媒
を添加混合して得た金属ペーストを絶縁基体1となるセ
ラミックグリーンシートに予め従来周知のスクリーン印
刷法により所定パターンに印刷塗布しておくことによっ
て絶縁基体1の所定位置に被着される。
For the metallized wiring layer 2, for example, a metal green paste, which is obtained by adding a suitable organic solvent or a solvent to a high melting point metal powder such as tungsten, and mixing the same, is conventionally known in advance on a ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by the screen printing method, the insulating base 1 is attached at a predetermined position.

【0014】また前記メタライズ配線層2はその露出す
る外表面にニッケル、金等の耐蝕性に優れ、且つロウ材
と濡れ性の良い金属をメッキ法により1.0乃至20.
0μmの厚みに層着させておくとメタライズ配線層2の
酸化腐食を有効に防止することができるとともにメタラ
イズ配線層2とボンディングワイヤ5との電気的接続を
強固なものとなすことができる。従って、前記メタライ
ズ配線層2の表面にはニッケル、金等の耐蝕性に優れ、
且つロウ材と濡れ性の良い金属をメッキ法により1.0
乃至20.0μmの厚みに層着させておくことが好まし
い。
The metallized wiring layer 2 is coated with a metal, such as nickel or gold, which is excellent in corrosion resistance and has a good wettability with the brazing material, on the exposed outer surface by plating.
When the metallized wiring layer 2 is layered to a thickness of 0 μm, oxidative corrosion of the metallized wiring layer 2 can be effectively prevented and the electrical connection between the metallized wiring layer 2 and the bonding wire 5 can be strengthened. Therefore, the surface of the metallized wiring layer 2 has excellent corrosion resistance against nickel, gold, etc.,
In addition, the brazing material and the metal having good wettability are 1.0 by the plating method.
It is preferable that the layers are laminated to a thickness of 20.0 μm.

【0015】更に前記メタライズ配線層2はその絶縁基
体1の下面に導出された部位が絶縁基体1の下面に被着
形成させた接続パッド7に電気的に接続されており、該
接続パッド7には外部リード端子3が銀ロウ等のロウ材
6を介してロウ付けされている。
Further, the metallized wiring layer 2 is electrically connected at its portion led out on the lower surface of the insulating substrate 1 to the connection pad 7 formed on the lower surface of the insulating substrate 1 by means of the connection pad 7. The external lead terminals 3 are brazed via a brazing material 6 such as silver brazing.

【0016】前記接続パッド7は絶縁基体1に外部リー
ド端子3を取着させるとともに外部リード端子3をメタ
ライズ配線層2を介して半導体素子4に電気的に接続さ
せる作用を為し、タングステン、モリブデン、マンガン
等の高融点金属粉末により形成されている。
The connection pad 7 serves to attach the external lead terminal 3 to the insulating substrate 1 and electrically connect the external lead terminal 3 to the semiconductor element 4 via the metallized wiring layer 2, and tungsten, molybdenum and molybdenum are used. , High melting point metal powder such as manganese.

【0017】前記接続パッド7はまた図2に示すよう
に、外形寸法の異なる2つのメタライズ層7a、7b
を、外形寸法の大きいメタライズ層7aを絶縁基体1の
表面側として被着積層させることによって形成されてお
り、外形寸法の大きなメタライズ層7aが絶縁基体1側
に、外形寸法の小さいメタライズ層7bが外部リード端
子3のロウ付けされる側に位置することから、接続パッ
ド7に外部リード端子3をロウ材6を介してロウ付けす
る際、ロウ材6は外形寸法の小さいメタライズ層7bの
表面のみに接合して外形寸法が大きく絶縁基体1に直接
接触しているメタライズ層7aには接合しなくなり、そ
の結果、ロウ材6の固化収縮に伴う引っ張り力は接続パ
ッド7の外周部に大きく作用することはなく、接続パッ
ド7の外周部に位置する絶縁基体1にクラックや割れ等
を発生するのは皆無となる。
As shown in FIG. 2, the connection pad 7 has two metallization layers 7a and 7b having different outer dimensions.
Is formed by depositing and laminating the metallization layer 7a having a large outer dimension on the surface side of the insulating substrate 1, and the metallized layer 7a having a large outer dimension is formed on the insulating substrate 1 side and the metallized layer 7b having a small outer dimension is formed. Since the external lead terminals 3 are located on the side to be brazed, when the external lead terminals 3 are brazed to the connection pads 7 via the brazing material 6, the brazing material 6 has only the surface of the metallized layer 7b having a small outer dimension. To the metallized layer 7a which has a large outer dimension and is in direct contact with the insulating substrate 1, and thus the tensile force due to the solidification shrinkage of the brazing material 6 largely acts on the outer peripheral portion of the connection pad 7. As a result, no cracks or cracks are generated in the insulating substrate 1 located on the outer peripheral portion of the connection pad 7.

【0018】尚、前記接続パッド7はメタライズ配線層
2と同様の方法、即ち、タングステン等の高融点金属粉
末に適当な有機溶剤、溶媒を添加混合して得た金属ペー
ストを絶縁基体1となるセラミックグリーンシートに予
め従来周知のスクリーン印刷法により印刷面積を順次小
さくして複数回塗布することによって絶縁基体1の下面
所定位置に被着形成される。
The connection pad 7 is used as the insulating substrate 1 in the same manner as the metallized wiring layer 2, that is, a metal paste obtained by adding and mixing an appropriate organic solvent or solvent to a refractory metal powder such as tungsten. The ceramic green sheet is applied to a predetermined position on the lower surface of the insulating substrate 1 by applying a plurality of times to the ceramic green sheet by sequentially reducing the printing area by a conventionally known screen printing method.

【0019】また前記接続パッド7は外形寸法の小さい
メタライズ層7bの厚みtを10μm以上としておく
と、外形寸法の小さいメタライズ層7bと外形寸法の大
きなメタライズ層7aとの間に大きな段差が形成され、
該段差によって接続パッド7に外部リード端子3をロウ
材6を介してロウ付けする際、ロウ材6がメタライズ層
7aに流出接合することはなく、これによってロウ材6
の固化収縮に伴う引っ張り力に起因して接続パッド7の
外周部に位置する絶縁基体1にクラックや割れ等が発生
するのを皆無となすことができる。従って、前記接続パ
ッド7は外形寸法の小さいメタライズ層7bの厚みtを
10μm以上としておくことが好ましい。
When the thickness t of the metallization layer 7b having a small outer dimension is set to 10 μm or more in the connection pad 7, a large step is formed between the metallization layer 7b having a small outer dimension and the metallization layer 7a having a large outer dimension. ,
When the external lead terminal 3 is brazed to the connection pad 7 via the brazing material 6 due to the step, the brazing material 6 does not flow out and join to the metallized layer 7a, and thus the brazing material 6
It is possible to prevent the occurrence of cracks or breaks in the insulating base 1 located on the outer peripheral portion of the connection pad 7 due to the tensile force caused by the solidification and contraction of the. Therefore, it is preferable that the thickness t of the metallized layer 7b having a small external dimension is 10 μm or more in the connection pad 7.

【0020】更に前記接続パッド7はその表面にニッケ
ル、金等の耐蝕性に優れ、且つロウ材と濡れ性の良い金
属をメッキ法により1.0乃至20.0μmの厚みに層
着させておくと接続パッド7の酸化腐食を有効に防止す
ることができるとともに接続パッド7に外部リード端子
3をロウ材6を介して強固にロウ付け取着することがで
きる。従って、前記接続パッド7の表面にはニッケル、
金等の耐蝕性に優れ、且つロウ材と濡れ性の良い金属を
メッキ法により1.0乃至20.0μmの厚みに層着さ
せておくことが好ましい。
Further, the connection pad 7 is formed by depositing a metal such as nickel or gold having excellent corrosion resistance and good wettability with a brazing material to a thickness of 1.0 to 20.0 μm by a plating method. With this, the oxidative corrosion of the connection pad 7 can be effectively prevented, and the external lead terminal 3 can be firmly brazed and attached to the connection pad 7 via the brazing material 6. Therefore, on the surface of the connection pad 7, nickel,
It is preferable to deposit a metal such as gold having excellent corrosion resistance and good wettability with the brazing material to a thickness of 1.0 to 20.0 μm by a plating method.

【0021】また更に前記絶縁基体1に被着させた接続
パッド7には外部リード端子3が銀ロウ等のロウ材6を
介してロウ付けされ、該外部リード端子3は絶縁基体1
の凹部1a内に収容する半導体素子4を外部電気回路に
接続する作用を為し、外部リード端子3を外部電気回路
に接続することによって凹部1a内に収容される半導体
素子4はメタライズ配線層2及び外部リード端子3を介
し外部電気回路に電気的に接続されることとなる。
Further, the external lead terminals 3 are brazed to the connection pads 7 attached to the insulating base 1 via the brazing material 6 such as silver solder, and the external lead terminals 3 are attached to the insulating base 1.
The semiconductor element 4 housed in the recess 1a has a function of connecting the semiconductor element 4 to the external electric circuit, and the external lead terminal 3 is connected to the external electric circuit. And, it is electrically connected to an external electric circuit through the external lead terminal 3.

【0022】前記外部リード端子3は鉄ーニッケルーコ
バルト合金や鉄ーニッケル合金等の金属材料から成り、
例えば鉄ーニッケルーコバルト合金等のインゴット
(塊)を圧延加工法や打ち抜き加工法等、従来周知の金
属加工法を採用し、所定の棒状に加工することによって
形成される。
The external lead terminal 3 is made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy.
For example, an ingot (lump) of iron-nickel-cobalt alloy or the like is formed into a predetermined rod shape by using a conventionally known metal processing method such as a rolling processing method or a punching processing method.

【0023】かくして、上述の半導体素子収納用パッケ
ージによれば、絶縁基体1の凹部1a底面に半導体素子
4をガラス、樹脂、ロウ材等の接着剤を介して接着固定
するとともに該半導体素子4の各電極をボンディングワ
イヤ5を介してメタライズ配線層2に電気的に接続し、
しかる後、絶縁基体1の上面に蓋体8を絶縁基体1の凹
部1aを塞ぐようにガラス、樹脂、ロウ材等から成る封
止材を介して接合させ、絶縁基体1の凹部1a内に半導
体素子4を気密に収容することによって最終製品として
の半導体装置となる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 4 is adhered and fixed to the bottom surface of the concave portion 1a of the insulating substrate 1 via an adhesive such as glass, resin, or brazing material, and the semiconductor element 4 Each electrode is electrically connected to the metallized wiring layer 2 via the bonding wire 5,
Thereafter, the lid 8 is bonded to the upper surface of the insulating base 1 through a sealing material made of glass, resin, brazing material or the like so as to close the recess 1a of the insulating base 1, and the semiconductor is placed in the recess 1a of the insulating base 1. A semiconductor device as a final product is obtained by hermetically housing the element 4.

【0024】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば、上述の実施例では本発
明の配線基板を半導体素子を収容する半導体素子収納用
パッケージに適用した場合の例で説明したが、これを混
成集積回路装置に使用される配線基板にも適用し得る。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiments, the wiring of the present invention is used. The example in which the substrate is applied to the semiconductor element housing package that houses the semiconductor element has been described, but the present invention can also be applied to the wiring board used in the hybrid integrated circuit device.

【0025】[0025]

【発明の効果】本発明の配線基板によれば、外部リード
端子がロウ付けされる接続パッドを、外形寸法の異なる
複数のメタライズ層を、外形寸法の大きいものより順に
絶縁基体の表面に被着積層させることによって形成した
ことから、接続パッドに外部リード端子をロウ材を介し
てロウ付けする際、ロウ材は外形寸法の小さいメタライ
ズ層に接合して外形寸法が最も大きく絶縁基体に直接接
触するメタライズ層に接合することはなく、その結果、
ロウ材の固化収縮に伴う引っ張り力は接続パッドの外周
部に大きく作用することはなく、接続パッドの外周部に
位置する絶縁基体にクラックや割れ等が発生するのを皆
無として、半導体素子の気密封止の信頼性や外部リード
端子の絶縁基体への取着の信頼性を極めて高いものとな
すことができる。
According to the wiring board of the present invention, the connection pads to which the external lead terminals are brazed, the plurality of metallized layers having different outer dimensions, are attached to the surface of the insulating substrate in the order of increasing outer dimensions. Since they are formed by stacking, when the external lead terminal is brazed to the connection pad via the brazing material, the brazing material is bonded to the metallized layer having the smallest outer dimension and directly contacts the insulating substrate having the largest outer dimension. Does not bond to the metallization layer, resulting in
The tensile force due to the solidification shrinkage of the brazing material does not significantly affect the outer peripheral portion of the connection pad, and the insulating substrate located on the outer peripheral portion of the connection pad is completely free from cracks and cracks, and the semiconductor element The reliability of tight sealing and the reliability of attachment of the external lead terminals to the insulating substrate can be made extremely high.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment in which a wiring board of the present invention is applied to a semiconductor element housing package.

【図2】図1の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.

【図3】従来の配線基板の要部拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a main part of a conventional wiring board.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・メタライズ配線層 3・・・・外部リード端子 6・・・・ロウ材 7・・・・接続パッド 1 ... Insulating substrate 2 ... Metallized wiring layer 3 ... External lead terminal 6 ... Brazing material 7 ... Connection pad

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】メタライズ配線層を有するセラミックス製
絶縁基体の表面に、前記メタライズ配線層と電気的に接
続される接続パッドを設けるとともに該接続パッドに外
部リード端子をロウ付けして成る配線基板であって、前
記接続パッドは外形寸法の異なる複数のメタライズ層
を、外形寸法の大きいものより順に絶縁基体の表面に被
着積層させて形成されていることを特徴とする配線基
板。
1. A wiring board comprising a ceramic insulating base having a metallized wiring layer, a connection pad electrically connected to the metallized wiring layer, and an external lead terminal brazed to the connection pad. The connection pad is formed by depositing and laminating a plurality of metallized layers having different outer dimensions on the surface of an insulating substrate in order of increasing outer dimensions.
JP6090973A 1994-04-28 1994-04-28 Wiring substrate Pending JPH07297530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6090973A JPH07297530A (en) 1994-04-28 1994-04-28 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6090973A JPH07297530A (en) 1994-04-28 1994-04-28 Wiring substrate

Publications (1)

Publication Number Publication Date
JPH07297530A true JPH07297530A (en) 1995-11-10

Family

ID=14013460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6090973A Pending JPH07297530A (en) 1994-04-28 1994-04-28 Wiring substrate

Country Status (1)

Country Link
JP (1) JPH07297530A (en)

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