JPH09213973A - Quantizing element and quantizing device therewith, and their production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a quantum element having a negative resistance characteristic by using an SOI(silicon on insulator) substrate. SOLUTION: A double barrier structure 1000 to generate a resonant tunnel effect is formed in a part of a silicon thin plate 107 while the plate 107 is used as a quantum well and the silicon oxide film 108 on the surface thereof as a tunnel barrier respectively. First and second electrodes 111 and 112 are formed on both sides of the structure 1000 in a manner to sandwich the structure 1000 therewith, thereby constituting a resonant tunnel diode 10. Since the plate 107 functioning as a quantum well is formed as a part of an upper silicon layer 100 of an SOI substrate, it has a high-quality crystallinity same as that of a silicon substrate. In addition, the barrier 108 is made of excellent quality silicon thermal oxide film 108 and has a high-potential barrier against electron. As a result, the quantization level of extremely sharp electronic energy is established in the plate 107 and optimal resonant tunnel effect of electron can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantizing function element utilizing the resonance tunnel effect, a quantizing function device using the same, and a manufacturing method thereof, and more particularly to a resonance tunnel diode and a memory using the same. And their manufacturing methods.

[0002]

2. Description of the Related Art In recent years, research on a quantized functional element utilizing a quantum effect has been advanced. An element utilizing the resonant tunneling effect of electrons, for example, a resonant tunneling diode has been proposed as one of the practical quantization function elements.
In order to form such a device, it is necessary to form a double barrier structure in which a quantum well having a size of an electron de Broglie wavelength is sandwiched by tunnel barriers. Specifically, a semiconductor heterostructure in a compound semiconductor material is required. A configuration utilizing joining has been proposed.

The manufacturing method is generally a method in which a thin film layer of a compound semiconductor material is crystal-grown by several atomic layers on a compound semiconductor substrate to obtain a desired semiconductor heterojunction (eg, Reona Esaki, Sakaki Sakaki). Hiroyuki, "Superlattice Heterostructure Device", Industrial Research Society, 1988, 197-25
See page 2 and pages 397-435).

A molecular beam epitaxy method is generally used for laminating compound semiconductor materials. 40 (a) to (d)
An example of a conventional method for manufacturing a resonant tunneling diode using a compound semiconductor material will be described with reference to FIG.

First, as shown in FIG. 40A, a first AlGaAs layer 12 having a thickness of about 2.3 nm is grown on the first Si-doped GaAs layer 11. Next, FIG.
As shown in order from (b) to (d), the first AlGa
On the As layer 12, a GaAs layer 13 having a thickness of about 7 nm, a second AlGaAs layer 14 having a thickness of about 2.3 nm, and finally a second Si-doped GaAs layer 15 are sequentially grown. As a result, the first AlGaAs layer 12 /
A resonant tunnel diode having a double barrier structure composed of the GaAs layer 13 / the second AlGaAs layer 14 can be formed.

On the other hand, as a double barrier structure using a silicon material, a structure in which a double barrier structure is formed on a silicon substrate by a silicon oxide film and polysilicon has been proposed (for example, Kazuro Sa left, et al. , 1991 (Heisei 3
Year) Autumn 52nd Annual Meeting of the Japan Society of Applied Physics, Lecture Collection,
No. 2, p. 653,10a-B-3, "SiO ₂ /
Resonance tunnel effect in Si / SiO ₂ double barrier structure ").

With reference to FIGS. 41 (a) to 41 (e), an example of a conventional method of manufacturing a resonant tunneling diode using a silicon material will be described.

First, an n-type silicon substrate 21 shown in FIG. 41 (a) is prepared, and then, by dry oxidation at a temperature of about 1000 ° C., a thickness of about 3 nm to about 4 nm is obtained as shown in FIG. 41 (b). To form a first silicon oxide film 22. Subsequently, FIG. 41C is formed on the silicon oxide film 22.
A polysilicon film 23 having a thickness of about 8 nm to about 12 nm is provided as shown in FIG. Further, by dry oxidation at a temperature of about 1000 ° C., a thickness of about 3 is formed on the polysilicon layer 23.
a second silicon oxide film 24 of about 4 nm to about 4 nm is formed,
A double barrier structure is formed as shown in FIG. Further, an aluminum electrode 25 is formed on the second silicon oxide film 24 by vacuum evaporation of aluminum (FIG. 41).
(See (e)). As a result, the first silicon oxide film 22
A resonance tunnel diode having a double barrier structure composed of / polysilicon layer 23 / second silicon oxide film 24 is formed.

[0009]

However, the conventional resonant tunnel diode configuration has the following problems.

First, when a compound semiconductor material is used, the height of the tunnel barrier is low (about 1.5 eV or less), so that the electron confinement in the quantum well becomes insufficient. As a result, electrons are transmitted through the double barrier structure even when the electron energy in the quantum well is not in a resonance state, so that the P / V ratio (peak current value and valley current value) in the IV characteristic of the device is generated. Ratio) cannot be increased. Here, the valley current is the minimum current value in the IV characteristic.

When a silicon material is used,
Since it is difficult to obtain a quantum well having good crystallinity, the quantum level in the well is blurred (that is, the energy level is broadened), and a good negative resistance characteristic cannot be obtained.

The present invention has been made to solve the above problems, and an object thereof is to provide a quantizing function element utilizing the resonance tunnel effect and a quantizing function apparatus utilizing the same.
And to provide a method for producing them. In particular, (1) a double barrier structure including a tunnel barrier having a high barrier height and a quantum well structure having perfect crystallinity, which is suitable for an existing manufacturing method of a silicon semiconductor device, is preferable. Providing a quantizing function element such as a resonance tunnel diode exhibiting operating characteristics, (2) providing a quantizing function device such as a memory using them, and (3) providing a manufacturing method thereof. ,
With the goal.

[0013]

A quantization function element of the present invention has silicon having first and second planes having predetermined crystal planes and having a thickness sufficiently thin to function as a quantum well. A silicon thin plate made of a single crystal, each formed along the first and second surfaces of the silicon thin plate;
A pair of tunnel barriers, and first and second electrodes operably coupled to each other, which are formed so as to sandwich the silicon thin plate and the pair of tunnel barriers from both sides,
Which achieves the above object.

In one embodiment, the silicon thin plate is
At least in part, it is a substantially free-standing structure.

[0015] Preferably, there is further provided a third electrode operably coupled to said silicon sheet.

The first and second electrodes may be made of polysilicon or single crystal silicon.

[0017] In one embodiment, the structure is formed on a silicon layer having a first conductivity type, and at least a part of the silicon thin plate has a second conductivity type opposite to the first conductivity type. An impurity having a conductivity type of is added.

In another embodiment, at least a part of the silicon thin plate other than a portion located immediately below the second electrode is completely oxidized.

In still another embodiment, the thickness of the pair of tunnel barriers is different between the first surface side and the second surface side of the silicon thin plate.

The pair of tunnel barriers are made of SiO ₂ , S.
iN, silicon oxynitride, SiC, CaF ₂ , and Si
It may be a film made of a material selected from the group consisting of Ge.

Preferably, the thickness of the silicon thin plate is set within the range of about 0.3 nm to about 100 nm.

The quantizing function element of the present invention having the above characteristics may be a resonant tunneling diode.

According to one aspect of the present invention, a quantizing function including an electrode and a plurality of quantizing function elements having the above-mentioned characteristics, which are operatively coupled in series through the electrode. An apparatus is provided by which the above objectives are achieved.

According to another aspect of the present invention, a quantizing function element having the above-mentioned characteristics is formed on a silicon-on-insulator substrate, and a MOS formed on the silicon-on-insulator substrate. Type transistor,
There is provided a quantizing function device including a quantizing function element and a conductive layer that operably couples the MOS type transistor, thereby achieving the above object.

According to still another aspect of the present invention, a quantizing function element having the above-mentioned features formed on a silicon-on-insulator substrate, and the silicon-on-insulating element.
There is provided a quantization function device including a MOS transistor formed on an insulator substrate, and an electrode that operably connects the quantization function element and the MOS transistor, thereby achieving the above object. To be done.

The quantization function device of the present invention having the above characteristics may be a resonant tunnel diode.

The method of manufacturing a quantization function element according to the present invention functions as a quantum well and a step of forming a silicon island on a silicon-on-insulator substrate including a silicon substrate, a buried insulating layer and an upper silicon layer. Forming a silicon sheet having a first and second surface that is sufficiently thin, and a pair of tunnel barriers, each along the first and second surfaces of the silicon sheet. Forming a first electrode and a second electrode sandwiching the silicon thin plate and the pair of tunnel barriers from both sides, the first and second electrodes being operably coupled to each other. The above object is achieved.

In one embodiment, in the step of forming the silicon thin plate, a step of removing a part of the buried insulating film layer directly under the silicon island to process the silicon island into the silicon thin plate, and the silicon thin plate. Of at least a part of the free standing structure.

Alternatively, in the step of forming the silicon thin plate,
Removing a part of the buried insulating film layer directly below the silicon island to form at least a part of the silicon island into a free-standing structure; and processing at least a part of the free-standing structure into the silicon thin plate. And, including.

In one embodiment, the step of forming the first and second electrodes is the same as the step of depositing a polysilicon layer on the surface of the silicon-on-insulator substrate and the step of forming the polysilicon layer on the polysilicon layer is the same as the upper silicon layer. The method includes a step of adding an impurity having a conductivity type in a high concentration and a step of patterning the polysilicon layer to form the first and second electrodes.

In another embodiment, the step of forming the silicon thin plate includes a step of removing the buried insulating film layer directly below the silicon island to form at least a part of the silicon island into a free-standing structure. First and second
The step of forming the electrode, exposing a part of the silicon substrate immediately below the free-standing structure,
A step of forming lateral epitaxial crystal growth using the exposed portion as a seed to form a single crystal silicon film,
The method includes the steps of adding an impurity having the same conductivity type as that of the upper silicon layer to the single crystal silicon film, and patterning the single crystal silicon film to form the first and second electrodes.

In still another embodiment, the step of forming the pair of tunnel barriers includes the step of forming the pair of tunnel barriers on the first surface of the silicon thin plate which is closer to the silicon-on-insulator substrate than the second surface of the silicon thin plate. Forming a first tunnel barrier, and forming a second tunnel barrier on the second surface of the silicon sheet opposite the first surface of the silicon sheet, The step of forming the first and second electrodes comprises depositing a first polysilicon layer on the surface of the silicon-on-insulator substrate, and forming the first polysilicon layer with the same conductivity as the upper silicon layer. Adding an impurity having a mold to a high concentration; patterning the first polysilicon layer to form the first electrode on the first tunnel barrier; Insi Forming a first insulating film on the surface of the insulator substrate, and providing an opening in the first insulating film directly above the first electrode to expose a part of the silicon thin plate through the opening. A step of depositing a second polysilicon layer on the surface of the silicon-on-insulator substrate, and an impurity having the same conductivity type as that of the upper silicon layer is added to the second polysilicon layer at a high concentration. And a step of patterning the second polysilicon layer to form a second electrode on the second tunnel barrier formed on the exposed portion.

In one embodiment, in the step of forming the silicon island, a part of the upper silicon layer of the silicon-on-insulator substrate is oxidized to form a silicon oxide film, and the buried insulating film layer and the silicon film are formed. The method includes the step of forming a silicon island separated from the oxide film.

Alternatively, the step of forming the silicon island includes a step of etching away the upper silicon layer other than the region where the silicon island is formed.

Preferably, the method of manufacturing a quantization function element according to the present invention further includes the step of forming a third electrode operably coupled to the silicon thin plate. In one embodiment, the step of forming the third electrode includes a step of forming an insulating layer covering the first and second electrodes, and a step of depositing and patterning a conductive layer on the surface of the insulating layer to form the insulating layer. Forming a third electrode. Alternatively, the step of forming the third electrode includes a step of thermally oxidizing the silicon-on-insulator substrate, a step of forming an insulating layer covering the first and second electrodes, and a step of forming an insulating layer on the surface of the insulating layer. Depositing and patterning a conductive layer to form the third electrode.

Further, after the step of forming the first and second electrodes, the silicon thin plate is self-aligned with impurities having a conductivity type opposite to that of the upper silicon layer by using the second electrode as an implantation mask. The method may further include a step of introducing into the above and a step of performing heat treatment for activating the introduced impurities.

The step of forming the pair of tunnel barriers includes thermal oxidation, plasma oxidation, thermal nitriding, chemical vapor deposition of silicon oxide film, chemical vapor deposition of silicon nitride film, and chemical vapor deposition of silicon nitride oxide film. Vapor deposition method, SiC film crystal growth method,
A method selected from the group consisting of molecular beam epitaxy of CaF ₂ films and crystal growth of SiGe films can be used.

Preferably, in the step of forming the silicon thin plate, the thickness of the silicon thin plate is about 0.3 nm to about 10.
Set within the range of 0 nm.

A resonant tunneling diode can be formed by the method of manufacturing a quantizing function element having the above characteristics according to the present invention.

According to an aspect of the present invention, a step of forming a plurality of quantization function elements by a method having the above characteristics and an electrode for operably coupling the plurality of quantization function elements in series are provided. A method of manufacturing a quantization function device including a forming step is provided, thereby achieving the above object.

According to another aspect of the present invention, a step of forming a quantizing function element by a method having the above characteristics, and a resistive load operably connected to the quantizing function element in series are provided. A method of manufacturing a quantization function device including a forming step is provided, thereby achieving the above object.

According to still another aspect of the present invention, a step of forming a quantization function element on a substrate by a method having the above characteristics, and a step of forming a MOS transistor on the substrate. , A step of operably coupling the quantization function element and the MOS transistor in series is provided, thereby achieving the above object.

A memory element can be formed by the method of manufacturing a quantization function element of the present invention having the above characteristics.

In the quantization function element of the present invention, the silicon thin plate formed in the substrate functions as a quantum well that brings about a quantum effect. A structure that functions as a resonant tunnel diode can be obtained by providing a pair of tunnel barriers and electrodes that sandwich the quantum well from both sides.

The quantizing function element of the present invention is made of a silicon material, and is basically formed by the same forming process as the CMOS manufacturing process such as thermal oxidation. Therefore, it becomes possible to simultaneously form the quantization function element of the present invention and another semiconductor device such as a MOS transistor on the same substrate in a series of manufacturing steps.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on embodiments.

(First Embodiment) A resonant tunneling diode 10 according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a top view of a resonant tunneling diode 10 according to the present invention, and FIGS. 1B and 1C are lines XX ′ and X ′ of the top view of FIG. 1A, respectively. It is sectional drawing in line YY '. FIG. 2 (a)
And (c), FIGS. 3 (a) and (c), and FIG.
(A) And (c) is a process top view showing the manufacturing process of the resonant tunneling diode 10, and is shown in FIGS. 2 (b) and (d), 3 (b) and (d), and FIG. 4 (b). 2 (a), 2 (c) and 3 (d) respectively.
FIG. 4A is a cross-sectional view taken along line XX ′ in FIGS. 3A, 3 </ b> C, 4 </ b> A, and 4 </ b> C. In the drawings, the same components are designated by the same reference numerals.

As shown in FIGS. 1B and 1C, in the resonant tunneling diode 10, on the silicon substrate 1,
A silicon thin plate 107 whose both ends are held by the field oxide film 102 is formed. The silicon thin plate 107 is formed of single crystal silicon and has a thickness of about 0.3 nm to about 100 nm, preferably several nm to allow a quantum size effect to occur therein to function as a quantum well.
It is about 50 nm, more typically about 10 nm. This lower limit corresponds to the thickness of one atomic layer. In addition, at least the portion located immediately below the second electrode 112 has a uniform thickness. At least a part of the field oxide film 102 under the silicon thin plate 107 is removed by using a hydrofluoric acid-based etching solution, and as a result, a part of the silicon thin plate 107 is held at both ends by, for example, a field oxide film. It has a free-standing structure as described above.

A pair of silicon oxide films 108 functioning as tunnel barriers sandwiching the silicon thin plate 107.
Are formed. The silicon oxide film 108 has a uniform thickness, and each thickness is about 5 nm or less, preferably about 1.5 nm.

On the silicon oxide films 108 formed on both sides of the silicon thin plate 107, the first electrodes 11 are formed, respectively.
Each of the first and second electrodes 112 is made of polysilicon to which an n-type impurity is added at a high concentration. As the n-type impurity, phosphorus, arsenic, or the like commonly used in semiconductor technology can be used. In addition, a third electrode 114 is provided via an interlayer insulating film 113 for controlling a voltage applied to the first electrode 111 and the second electrode 112 and controlling a potential of the silicon thin plate (quantum well) 107. ing.

In the attached drawings, the first electrode 1
11 is drawn larger than the second electrode 112,
Actually, the relative sizes of the two electrodes 111 and 112 are not limited to this. The first electrode 111 is the second
Electrode 112, or both electrodes 111 and 112 may have the same size.

Resonant tunnel diode 10 as described above
In the above structure, the double barrier structure 1000 in which the resonance tunnel effect occurs is formed in the silicon thin plate 107 portion by using the silicon thin plate 107 as a quantum well and the silicon oxide film 108 on the surface thereof as a tunnel barrier. . This double barrier structure 1000 is sandwiched between the first electrode 111 and the second electrode 111.
The electrodes 112 form a main part of the resonant tunnel diode 10.

Resonant tunnel diode 10 of this embodiment
In, the silicon thin plate 10 functioning as a quantum well
7 is formed as part of the upper silicon layer 100 of the silicon-on-insulator substrate 90. Therefore, its crystallinity is as high as that of the silicon substrate. Further, since a good quality thermal oxide film is used as the silicon oxide film 108, the height of the potential barrier in the double barrier structure 1000 is about 3.1 eV for electrons, and a high potential barrier can be realized. In addition, since the silicon / silicon oxide film interface is flat at the atomic level, an extremely sharp quantization level of electron energy is formed in the silicon thin plate 107, and a good electron resonance tunnel effect is obtained. Further, since the resonant tunnel diode 10 is made of silicon, which is excellent in mass productivity and economical efficiency, it is also excellent in manufacturing cost and mass productivity.

Next, FIGS. 2A to 2D and FIGS.
A method of manufacturing the resonant tunneling diode 10 of the present embodiment will be described with reference to (d) and FIGS.

First, an n-type silicon substrate 1 having a (001) plane orientation, a buried silicon oxide film layer 99 having a thickness of about 400 nm, and an upper silicon layer 10 having a thickness of about 100 nm.
Silicon-on-insulator (SOI) consisting of 0
On the substrate 90, a pad oxide film / nitride film multilayer film 101 is formed.
To form The pad oxide film included in the multilayer film 101 is
It is formed by pyrogenic oxidation at a temperature of about 900 ° C. for about 26 minutes, and its thickness is about 50 nm. The nitride film is deposited by low pressure chemical vapor deposition (LPCVD) method and has a thickness of about 120 nm.

Next, by using the photolithography method and the dry etching method using O ₂ and CF ₄ gas, as shown in FIG.
As shown in (a) and (b), the pad oxide film / nitride film multilayer film 101 is patterned into a rectangular shape having a size of about 3 μm × about 10 μm.

Further, by thermal oxidation treatment by pyrogenic oxidation at a temperature of about 1000 ° C. for about 1 hour, LOC
OS (local oxidation of silicon) separation is performed. At this time, the upper silicon film layer 100 other than the part covered with the pad oxide film / nitride film multilayer film 101 is completely oxidized, and is bonded to the buried oxide film layer 99, so that the upper silicon film layer 100 and the buried oxide film layer 99 shown in FIGS.
A field oxide film 102 is formed as shown in FIG. As a result, the field oxide film 102 forms a silicon island 103 that is completely insulated and separated from the silicon island of the adjacent element. At this point, the thickness of the silicon island 103 is
It will typically be about 77 nm.

Then, the nitride film is removed by etching with hot phosphoric acid at about 160 ° C. for about 80 minutes, and the pad oxide film is removed by etching with 2% buffered hydrofluoric acid at a temperature of about 25 ° C. for about 4 minutes. To do. Thereby, the multilayer film 10
Remove 1.

Then, as shown in FIG. 3A, a first resist 104 is formed on the field oxide film 102, and the first resist 104 is formed by a photolithography method to about 0.5 μm × about 1 μm.
The resist opening portion 105 having the size is provided. Further, the field oxide film 102 immediately below the silicon island 103 is removed by etching through the resist opening 105 with 20% buffered hydrofluoric acid for about 10 minutes to form a part of the silicon island 103 as a free-standing structure (FIG. 3). (See (b)).

Next, after removing the first resist 104, pyrogenic oxidation is performed at a temperature of about 1000 ° C., which is higher than the viscous flow temperature of the silicon oxide film (about 965 ° C.), and a silicon oxide film with a thickness of about 76 nm is obtained. (Not shown). After that, an etching process using 5% buffered hydrofluoric acid is performed to remove the formed silicon oxide film having a thickness of about 75 nm. As a result, the free standing portion of the silicon island 103 is thinned, and a silicon thin plate 107 having a thickness of about 7 nm, which will be a quantum well later, is formed.

Here, the edge portion around the silicon island 103 generated in the LOCOS separation step is about 900 due to the oxidation suppressing effect due to stress concentration due to its shape.
Thermal oxidation performed at a temperature of ℃ or less (thermal oxidation at low temperature) is not sufficiently oxidized. Therefore, the thickness of the silicon oxide film in that portion becomes very thin. However, in this embodiment, since the thermal oxidation is performed at a temperature equal to or higher than the viscous flow temperature of the silicon oxide film, an oxide film having a sufficient thickness is formed even at the above-mentioned edge portion, and the next tunnel barrier forming step is performed. Of the electrode 11 at the edge portion due to the oxidation suppressing effect after
No current leakage occurs between 1 and 112 and the thin silicon plate 107.

After that, dry oxidation is performed at a temperature of about 700 ° C. for about 10 minutes to form a silicon thin plate 10 having a thickness of about 7 nm.
A thermal oxide film having a thickness of about 1.5 nm is formed on the upper and lower surfaces of 7 (that is, the silicon island 103), and thereby the silicon oxide film 108 functioning as the tunnel barrier 108 is obtained. Along with this, the thickness of the silicon thin plate 107 is reduced to about 5 nm. In this oxidation step, another silicon oxide film 108 is formed on the silicon substrate 1.

After that, by LPCVD method, about 300 nm
A thickness of polysilicon layer 106 is deposited. Due to the good step coverage, the silicon thin plate 10 sandwiched by the silicon oxide films 108 is formed as shown in FIGS.
7 is formed, which is completely surrounded by the polysilicon layer 106.

Next, a high-concentration phosphorus diffusion process using POCl ₃ gas is performed at a temperature of about 900 ° C. for about 20 minutes, so that the polysilicon layer has a concentration of about 1 × 10 ¹⁹ cm ^-3 or more. Add to 106.

After that, a second resist 109 is formed on the polysilicon layer 106 by photolithography and patterning. Then, SiCl ₄ , CH ₂
The polysilicon layer 106 is patterned by dry etching using F ₂ , SF ₆ and O ₂ gas. As a result, as shown in FIG. 4B, about 1 μm × about 1 μm
m first electrode 111 and second electrode 112
Is formed.

After that, the second resist 109 is removed, and as shown in FIGS. 4C and 4D, the interlayer insulating film 1 is formed.
13 is deposited by LPCVD to a thickness of about 200 nm.
Then, the first electrode 1 is formed by the photolithography method.
11 and the second electrode 112, a mask pattern having an opening at a position corresponding to the second electrode 112 is formed on the interlayer insulating film 113, and CF ₄ and O ₂ gas are used to form the interlayer insulating film 1 in the opening.
Remove 13. After that, an aluminum film is deposited to a thickness of about 1 μm by a sputtering method, and is further patterned to form a film shown in FIG.
A third electrode 114 as shown in (c) and (d) is formed.

In the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. And a third electrode 114 of
The resonant tunneling diode 10 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by a chemical vapor deposition method or an ozone oxidation method instead of the thermal oxidation formation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Although the silicon substrate 1 has a (001) plane orientation, any substrate orientation may be used as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

Next, the current-voltage characteristics of the resonance tunnel diode 10 of this embodiment and the resonance tunnel diode of the prior art will be compared.

FIG. 5 is a diagram showing the current-voltage characteristic (curve 1200) of the resonant tunneling diode 10 according to the present embodiment and the current-voltage characteristic (curve 1100) of the conventional resonant tunneling diode. These characteristics are, for example, the resonance tunnel diode 1 of the present embodiment.
In the case of 0, it can be obtained by measuring the current flowing when a voltage is applied between the first electrode 111 and the second electrode 112 described above. In addition, in the current-voltage characteristics of FIG. 5, the peak current Ip is the quantization level in the silicon thin plate 107 that is the quantum well and the first electrode 111 and the second electrode 11
This corresponds to the case where the Fermi level of the electron in 2 matches. By applying a voltage exceeding the applied voltage Vp that gives the current Ip to the resonant tunneling diode, a negative resistance characteristic is observed in which the current decreases as the applied voltage increases. Here, the minimum value of the current is called the valley current Iv.

Characteristics of Conventional Resonant Tunneling Diode 11
00 and the characteristic 1200 of the resonant tunneling diode 10 of the present embodiment, if the width of the quantum well and the thickness of the silicon oxide film (potential barrier) are the same, the peak current value Ip and the valley current Iv are respectively It is obtained with the same applied voltage. However, in the resonant tunnel diode 10 of the present embodiment, since the thin silicon plate 107 is made of single crystal silicon, the blur of the quantization level is extremely small, so that the valley current Iv can be suppressed to an extremely low level. . As a result, a high value can be obtained for the peak valley ratio Ip / Iv, which is an index indicating the goodness of the device characteristics.

For example, in the resonance tunnel diode 10 according to the present embodiment, polysilicon to which phosphorus is added at a high concentration of about 1 × 10 ¹⁹ cm ⁻³ is used as the first and second electrodes 111 and 112, and A silicon oxide film 1 having a barrier height of about 3.1 eV and a thickness of about 1.5 nm
08 and n-type single crystal silicon thin plate 107 having a thickness of about 5 nm
If the double barrier structure 1000 consisting of is used, the peak current density Jp is about 20 A / c at an applied voltage of about 0.5 V.
m ² and peak valley ratio Ip / Iv = about 120 (when the size of the electrode is about 1 μm × about 1 μm, Ip = 0.2 μm
A and Iv = about 1.7 nA) are obtained as good values.

In the double barrier structure of the silicon / silicon oxide film system, the obtained voltage-current characteristics greatly differ depending on the thickness of the silicon oxide film serving as the tunnel barrier and the width of the silicon quantum well layer. For example, in the above example, the thickness of the n-type single crystal silicon thin plate is about 5 nm to about 1 nm.
When it is changed to 0 nm, the peak current density Jp in the vicinity of the applied voltage of about 0.5 V is about 13 A / cm ² and the peak valley ratio Ip / Iv is about 4, and the characteristics are greatly changed as compared with the values described above. I understand. Therefore, the thickness of the silicon thin plate needs to be controlled with extremely high accuracy. In this regard, in the manufacturing method according to the first embodiment of the present invention, the thinning of the silicon thin plate 107 is performed in the thermal oxidation step of the silicon islands 103, which facilitates the control of the thickness of the angstrom order. It can be carried out.

(Second Embodiment) A resonance tunnel diode 20 according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 6 (a) is a top view of the resonant tunneling diode 20 of the present invention, and FIGS. 6 (b) and 6 (c) are lines XX 'and 6'of the top view of FIG. 6 (a), respectively. It is sectional drawing in line YY '. In addition, FIG.
8A and 8C, FIGS. 8A and 8C, FIGS. 9A and 9C, and FIG. 10A are process top views showing a manufacturing process of the resonant tunneling diode 20.
(B) and (d), FIG. 8 (b) and (d), FIG. 9 (b)
7 (d) and FIG. 10 (b) are respectively shown in FIG.
(A), FIG. 7 (c), FIG. 8 (a), FIG. 8 (c), FIG.
(A), FIG. 9 (c), and line X- in FIG. 10 (a).
It is sectional drawing in X '. In the drawings, the same components are designated by the same reference numerals. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In the resonant tunnel diode 20, a double barrier structure 100 consisting of a silicon thin plate 107 whose both ends are held by a field oxide film 103 and a silicon oxide film 108 formed on the surface of the silicon thin plate 107.
0 is formed in the n-type silicon-on-insulator substrate 90, and the double barrier structure 1000 is sandwiched between the first electrode 111 and the second electrode 112, which is the resonant tunneling diode 10 of the first embodiment. Is the same as. Accordingly, as in the first embodiment, the double barrier structure 1000
A resonant tunneling diode 20 is constituted by two terminals of a first electrode 111 and a second electrode 112 on both sides of the resonance tunnel diode 20.

The resonance tunnel diode 20 of the second embodiment is different from that of the first embodiment in that the resonance tunnel diode 10 of the first embodiment has a silicon thin plate 107 of a free-standing portion having a thickness different from that of the first embodiment. In the resonant tunneling diode 20 of the second embodiment, the silicon thin plate 107 other than the portion directly below the second electrode 112 is more uniform than the silicon thin plate 107 directly below the second electrode 112 in the resonant tunneling diode 20 of the second embodiment. Is also thick. This makes it possible to more firmly support the free-standing portion even when the silicon thin plate 107 directly below the second electrode 112, which serves as a quantum well, is as thin as several nm.

Further, when forming the potential control electrode of the silicon thin plate 107 using the third electrode 114, as shown in FIGS. 6A to 6C, the interlayer insulating film 11 is formed.
It is desirable to set the thickness of the silicon thin plate 107 at the opening of No. 3 to about 50 nm or more in consideration of the process margin. According to this embodiment, the silicon thin plate 10 in the opening is
It is possible to set the thickness of the silicon thin plate 107 to about 10 nm or less where a remarkable quantum effect can be obtained only just under the second electrode 112 while keeping the thickness of 7 about 50 nm or more.

Next, FIGS. 7 (a)-(d) and 8 (a)-
A method of manufacturing the resonant tunneling diode 20 of the present embodiment will be described with reference to (d), FIGS. 9 (a) to 9 (d), and FIGS. 10 (a) and 10 (b).

First, an n-type silicon substrate 1 having a (001) plane orientation, a buried silicon oxide film layer 99 having a thickness of about 400 nm, and an upper silicon layer 10 having a thickness of about 100 nm.
Silicon-on-insulator (SOI) consisting of 0
On the substrate 90, a pad oxide film / nitride film multilayer film 101 is formed.
To form The pad oxide film included in the multilayer film 101 is
It is formed by pyrogenic oxidation at a temperature of about 900 ° C. for about 26 minutes, and its thickness is about 50 nm. The nitride film is deposited by low pressure chemical vapor deposition (LPCVD) method and has a thickness of about 120 nm.

[0086] Next, by a dry etching method using photolithography and O ₂ and CF ₄ gas, 7
As shown in (a) and (b), the pad oxide film / nitride film multilayer film 101 is patterned into a rectangular shape having a size of about 3 μm × about 10 μm.

Further, by thermal oxidation treatment by pyrogenic oxidation at a temperature of about 1000 ° C. for about 1 hour, LOC
OS separation is performed. At this time, the upper silicon film layer 100 other than the portion covered with the pad oxide film / nitride film multilayer film 101 is formed.
Is completely oxidized and is bonded to the buried oxide layer 99,
Field oxide film 1 as shown in FIGS. 7 (c) and 7 (d)
02 is formed. As a result, the field oxide film 102
Then, a silicon island 103 which is completely insulated and separated from the silicon island of the adjacent element is formed. At this point, the thickness of silicon island 103 is typically about 77 nm.

Then, the nitride film is removed by etching with hot phosphoric acid at about 160 ° C. for about 80 minutes, and the pad oxide film is removed by etching with 2% buffered hydrofluoric acid at a temperature of about 25 ° C. for about 4 minutes. To do. Thereby, the multilayer film 10
1 is removed.

Further, unlike the first embodiment, pyrogenic oxidation is performed again at a temperature of about 900 ° C. for about 26 minutes to form a thermal oxide film having a thickness of about 20 nm. After that, as shown in FIG. 8A, the thickness is about 1 by the LPCVD method.
A 20 nm second nitride film 300 is continuously deposited. Then, the photolithography method and CH ₃ F and CH ₂ F _{2 are used.}
By the dry etching method using a gas, the second nitride film 300 located in the center of the silicon island 103 has a thickness of about 1.
An opening having a size of 5 μm × about 1.5 μm is provided (FIG. 8).
(B)).

Next, pyrogenic oxidation is performed at a temperature of about 1000 ° C. which is higher than the viscous flow temperature (about 965 ° C.) of the silicon oxide film to form a silicon oxide film (not shown) having a thickness of about 152 nm. After that, an etching process using 5% buffered hydrofluoric acid is performed, and the formed thickness is about 1
The 52 nm silicon oxide film is removed. At this point, the thickness of the silicon island 103 at the position corresponding to the opening of the second nitride film 300 is about 7 nm, and the silicon island 103 functions as a silicon thin plate described later. On the other hand, the thickness of the silicon island 103 in the region covered with the second nitride film 300 is about 70 nm (see FIGS. 8A and 8B).

After that, the second nitride film 300 is removed by etching with hot phosphoric acid at a temperature of about 160 ° C. for about 80 minutes. Then, as shown in FIG. 8C, a first resist 104 is deposited on the field oxide film 102,
A resist opening 105 having a size of about 0.5 μm × about 1 μm is provided by a photolithography method. Further, the field oxide film 102 immediately below the silicon island 103 is passed through the resist opening 105 and is filled with 20% buffered hydrofluoric acid to about 1
The silicon island 103 is partially removed by etching for 0 minutes to form a free-standing structure (see FIG. 8D).

After that, dry oxidation is performed at a temperature of about 700 ° C. for about 10 minutes to form a thermal oxide film having a thickness of about 1.5 nm on the upper and lower surfaces of the silicon island 103 (that is, the silicon thin plate 107). A silicon oxide film 108 functioning as a tunnel barrier 108 is formed by. At this time,
The thickness of the silicon thin plate 107 is about 5 nm.
In this oxidation step, another silicon oxide film 108 is formed on the silicon substrate 1.

After that, as in the first embodiment, the LPC
The polysilicon layer 106 having a thickness of about 300 nm is formed by the VD method.
Is deposited. Due to its good step coverage, FIG.
As shown in (a) and (b), the silicon oxide film 108
A thin silicon plate 107 sandwiched between is completely surrounded by the polysilicon layer 106.

Next, a high-concentration phosphorus diffusion process using POCl ₃ gas is performed at a temperature of about 900 ° C. for about 20 minutes to make the polysilicon layer have a concentration of about 1 × 10 ¹⁹ cm ⁻³ or more. Add to 106.

After that, a second resist 109 is formed on the polysilicon layer 106 by photolithography and patterning, as shown in FIG. 9C.
Then, the polysilicon layer 106 is dry-etched by using SiCl ₄ , CH ₂ F ₂ , SF ₆ and O ₂ gas.
Is performed. As a result, as shown in FIG. 9D, the first electrode 11 having a size of about 1 μm × about 1 μm is formed.
First and second electrodes 112 are formed.

After that, the second resist 109 is removed, and the interlayer insulating film 113 is deposited by LPCVD to a thickness of about 200 nm. Then, a mask pattern having openings at positions corresponding to the first electrode 111 and the second electrode 112 is formed by photolithography on the interlayer insulating film 11.
3, and the interlayer insulating film 113 in the opening is removed by using CF ₄ and O ₂ gas. After that, an aluminum film is deposited to a thickness of about 1 μm by a sputtering method and further patterned to form a third electrode 114 as shown in FIGS. 10A and 10B.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. Second electrode of the present invention, comprising:
The resonant tunneling diode 20 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by a chemical vapor deposition method or an ozone oxidation method instead of the thermal oxidation formation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Further, although the silicon substrate 1 having the (001) plane orientation is used, a substrate having any plane orientation may be used as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

(Third Embodiment) A resonance tunnel diode 30 according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 11A is a top view of the resonance tunnel diode 30 according to the present invention, and FIGS. 11B and 11C are respectively lines XX ′ in the top view of FIG. 11A.
3 is a cross-sectional view taken along line YY ′. FIG.
(A) and (c), FIG. 13 (a) and (c), FIG.
FIGS. 12A and 12C, and FIG. 15A are process top views showing the manufacturing process of the resonant tunnel diode 30, and FIGS. 12B and 12D, 13B and 13D. 14 (b) and (d), and FIG.
12 (b) are respectively FIG. 12 (a), FIG. 12 (c), and FIG.
3 (a), FIG. 13 (c), FIG. 14 (a), and FIG.
FIG. 16C is a cross-sectional view taken along line XX ′ in FIG. 15A. In the drawings, the same components are designated by the same reference numerals. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The resonance tunnel diode 30 of the third embodiment is different from that of the first embodiment in that the resonance tunnel diode 10 of the first embodiment is different from the first embodiment.
While the electrode 111 and the second electrode 112 are made of polysilicon formed by the LPCVD method,
In the resonant tunnel diode 30 of the third embodiment, these electrodes 111 and 112 are exposed through the opening of the silicon oxide film 108 provided on the upper surface of the silicon substrate 1, as shown in FIG. 11B. Silicon substrate 1
It is composed of single crystal silicon formed by the lateral solid phase orientation growth method, using the exposed portion of as a seed.
By using single crystal silicon instead of polysilicon as the constituent material of the electrodes 111 and 112, the levels in the silicon forbidden band of the electrodes 111 and 112 are significantly reduced. Therefore, according to the present embodiment, the tunnel current via the forbidden band level and the quantum well quantum level, which is a leak component of the resonant tunnel diode, is suppressed.

Next, FIGS. 12A to 12D and FIG.
(A)-(d), FIG. 14 (a)-(d), and FIG.
A method of manufacturing the resonant tunneling diode 30 of the present embodiment will be described with reference to 5 (a) and 5 (b). However, of these, the steps up to the step corresponding to FIG. 13B are the same as the corresponding steps in the first embodiment described above, so description thereof will be omitted here.

As shown in FIG. 13B, silicon island 1
03 is partially brought into a free-standing state, the first resist 104 is removed, and the silicon oxide film 10 is further removed.
8 the silicon island 103 (that is, the silicon thin plate 10
7) After forming on the upper and lower surfaces and the silicon substrate 1,
As shown in FIGS. 13C and 13D, a second resist 301 is formed by photolithography. The second resist 301 has an opening portion at a portion corresponding to a portion of the silicon substrate 1 exposed in the etching process of the field oxide film 102 previously performed to make the silicon island 103 a free-standing structure. Is patterned so as to have Then, the second resist 30 is formed by a dry etching method using O ₂ and CF ₄ gas.
The silicon oxide film 108 formed in the portion corresponding to the opening 1 is removed to form the exposed portion 303 of the silicon substrate 1 as shown in FIG.

After that, the second resist 301 is removed,
By a thermal decomposition method using silane gas as a raw material gas, amorphous silicon having a thickness of about 2 at a reaction temperature of about 550 ° C. to about 580 ° C.
Deposited to 00 nm. Then, phosphorus atoms are introduced by ion implantation to a concentration of about 2 × 10 ¹⁵ cm ^-2 . Next, the temperature is about 6
Lateral solid phase orientation growth of the amorphous silicon film is performed by heat treatment at 00 ° C. for about 7 hours. As a result, single crystal silicon is grown from the exposed portion 302 of the silicon substrate 1, that is, the seed portion 303, and the single crystal silicon 302 to which phosphorus is added at a high concentration of about 1 × 10 ²⁰ cm ⁻³ is formed ( 14 (a) and (b)).

The subsequent steps are the same as those in the first embodiment shown in FIG.
The same as the steps described with reference to (a) to (d),
Here, the description is omitted.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. A third electrode 114 of the present invention.
The resonant tunneling diode 30 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by chemical vapor deposition or ozone oxidation instead of thermal oxidation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Although the silicon substrate 1 has the (001) plane orientation, it may have any plane orientation as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

(Fourth Embodiment) A resonant tunneling diode 40 according to a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 16 (a) is a top view of the resonant tunneling diode 40 of the present invention, and FIGS. 16 (b) and 16 (c) are respectively lines XX 'in the top view of FIG. 16 (a).
3 is a cross-sectional view taken along line YY ′. FIG.
(A) and (c), FIGS. 18 (a) and (c), and FIGS. 19 (a) and (c) show the resonant tunneling diode 4
17 is a process top view showing the manufacturing process of No. 0, and FIG.
18 (b) and (d), FIGS. 18 (b) and (d), and FIGS. 19 (b) and (d) are respectively FIG. 17 (a), FIG. 17 (c), FIG. 18 (a), and FIG. 18 (c), FIG.
FIG. 20A is a cross-sectional view taken along line XX ′ of FIG. 19C. In the drawings, the same components are designated by the same reference numerals. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The resonance tunnel diode 40 of the fourth embodiment is different from that of the first embodiment in that in the resonance tunnel diode 10 of the first embodiment, the conductivity type of the silicon thin plate 107 is n-type. On the other hand, in the resonant tunneling diode 40 of the fourth embodiment, as can be seen from FIGS. 16B and 16C, only the portion of the silicon thin plate 107 that is directly below the second electrode 112 is exposed. It is an n-type, and the silicon thin plate 107 at the other portions is a p-type. In the following description, the n-type region of the silicon thin plate 107 will be referred to as “n-type silicon thin plate 2”.
01 ”, and the p-type region of the silicon thin plate 107 is called“ p-type silicon thin plate 200 ”.

The impurity concentration of the n-type silicon thin plate 201 is
In order to suppress the blurring (spreading) of the quantum level due to scattering, it is preferably set to 1 × 10 ¹⁵ cm ⁻³ or less. On the other hand, the impurity concentration of the p-type silicon thin plate 200 is 1 × 10.
Set it to ¹⁶ cm ^-3 or higher.

The potential control electrode of the quantum well portion is formed from a part of the p-type silicon thin plate 200 to the third electrode 11.
It is taken out through 4. By applying a reverse bias (that is, a negative voltage) to the p-type silicon thin plate 200 to extend the depletion layer at the pn junction of the silicon thin plates 200 and 201, the effective area of the resonant tunnel diode 40 can be reduced. It will be possible.

By optimizing the value of the reverse bias, the element area of the resonant tunnel diode 40 is about 100 nm ^2.
(That is, about 10 nm x about 10 nm) or less,
The quantum well portion becomes a silicon quantum dot. As a result, the quantized state density function becomes a delta function, and a resonant tunnel diode having an extremely high peak-valley ratio can be realized. Further, at that time, the interval between the quantization levels becomes large, so that the voltage value applied to the first electrode 111 and the second electrode 112 at the time when the peak current is obtained becomes larger, and the quantum well portion It is possible to change the current-voltage characteristics by changing the applied voltage of.

Next, FIGS. 17A to 17D and FIG.
A method of manufacturing the resonant tunneling diode 40 of the present embodiment will be described with reference to (a) to (d) and FIGS. 19 (a) to (d). However, up to the step corresponding to FIG. 18D among these steps is the same as the corresponding step in the first embodiment described above, and thus the description thereof is omitted here.

After the polysilicon layer 106 is formed, a high-concentration phosphorus diffusion process using POCl ₃ gas is performed at a temperature of about 900 ° C. for about 20 minutes, so that the concentration of phosphorus is about 1 × 10 ¹⁹ cm ⁻³ or more. Is added to the polysilicon layer 106. After that, as shown in FIG. 19A, a second resist 109 is formed on the polysilicon layer 106 by photolithography and patterning. And SiCl
_The polysilicon layer 106 is patterned by dry etching using ₄ , CH ₂ F ₂ , SF ₆ and O ₂ gas. As a result, as shown in FIG.
A first electrode 111 and a second electrode 112 each having a size of m × about 1 μm are formed.

Next, with the second resist 109 remaining, the silicon oxide film 10 is formed on the silicon thin plate 107.
BF ₂ ⁺ ions are entirely implanted at an accelerating voltage of about 40 keV through 8. As a result, the p-type silicon thin plate 200 is formed by using the part of the silicon thin plate 107 other than the part corresponding to the second electrode 112 as the p-type region (FIG. 19A).
And (b)).

After that, the second resist 109 is removed, and heat treatment is performed in a nitrogen atmosphere at a temperature of about 900 ° C. for about 20 minutes to activate the implanted p-type impurities.

Subsequent manufacturing steps are the same as the corresponding manufacturing steps of the first embodiment described above with reference to FIGS. 4A and 4B, and a description thereof will be omitted here.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. And a third electrode 114 of
The resonant tunneling diode 40 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by chemical vapor deposition or ozone oxidation instead of thermal oxidation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Further, although the silicon substrate 1 having the (001) plane orientation is used, a substrate having any plane orientation may be used as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

Next, the current-voltage characteristics obtained by the resonant tunneling diode 40 of this embodiment will be described.

In FIG. 20, a curve 1300 shows the characteristic obtained in the resonant tunneling diode 40 of this embodiment in a state where no bias voltage is applied.
On the other hand, the curve 1400 is obtained when a reverse bias is applied to the pn junction formed between the n-type silicon thin plate 201 and the p-type silicon thin plate 200 of the resonant tunnel diode 40 by using the third electrode 114. It is the obtained current-voltage characteristic between the 1st electrode 111 and the 2nd electrode 112.

In the resonant tunnel diode 40, n
Type silicon thin plate 201 and the first electrode 111
The peak current Ip is observed in the current-voltage characteristic of FIG. When a reverse bias is applied to the pn junction between the p-type silicon thin plate 200 and the n-type silicon thin plate 201, a depletion layer spreads on the n-type silicon thin plate 201 side. As a result, the device area is effectively reduced, the electron confinement effect is increased, and the quantum level interval is widened. As a result, the peak current Ip
The peak voltage Vp that gives the voltage shifts to the high voltage side. Moreover, the value of the peak current Ip decreases as the element area decreases.

As described above, according to this embodiment, the resonant tunnel diode 4 is changed by changing the reverse bias.
It is possible to modulate the I-V characteristic of 0, and it is possible to change the operating point of the transistor.

(Fifth Embodiment) A resonant tunneling diode 50 according to a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 21 (a) is a top view of the resonant tunneling diode 50 according to the present invention, and FIGS. 21 (b) and 21 (c) are respectively lines XX 'in the top view of FIG. 21 (a).
3 is a cross-sectional view taken along line YY ′. In addition, FIG.
(A) and (c), FIG. 23 (a) and (c), and FIG. 24 (a) and (c) show the resonant tunneling diode 5
22 is a process top view showing a manufacturing process of No. 0, and FIG.
(B) and (d), FIG. 23 (b) and (d), and FIG. 24 (b) and (d) are FIG. 22 (a), FIG. 22 (c), FIG. 23 (a), and FIG. 23 (c), FIG.
FIG. 25A is a cross-sectional view taken along line XX ′ of FIG. 24C. In the drawings, the same components are designated by the same reference numerals. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The resonant tunnel diode 50 of the fifth embodiment is different from that of the first embodiment in that a region of the silicon thin plate other than immediately below the second electrode 112 is the oxidized silicon thin plate 400. That is the point. For this reason, the number of leak current paths is extremely small, and it is possible to significantly reduce the valley current, and a high P / V ratio is achieved.

Next, FIGS. 22A to 22D and FIG.
A method of manufacturing the resonant tunneling diode 50 of the present embodiment will be described with reference to (a) to (d) and FIGS. 24 (a) to (d). However, among these steps, the steps up to the step corresponding to FIG. 24B are the same as the corresponding steps in the first embodiment described above, and thus the description thereof is omitted here.

In this embodiment, the second resist 109 is removed between the steps of FIGS. 4 (a) and 4 (b) and the steps of FIGS. 4 (c) and 4 (d) in the first embodiment. After that, thermal oxidation treatment is performed for about 10 minutes by pyrogenic oxidation at a temperature of about 900 ° C. to form a thermal oxide film with a thickness of about 20 nm. By this thermal oxidation step, as shown in FIGS. 24C and 24D, the surfaces of the first electrode 111 and the second electrode 112 made of polysilicon are oxidized and the second electrode
The silicon thin plate 107 in a portion other than immediately below the electrode 112 of becomes the oxidized silicon thin plate 400.

The manufacturing process after the thermal oxidation process is the same as the manufacturing process described with reference to FIGS. 4C and 4D in the first embodiment, and the description thereof is omitted here.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. And a third electrode 114 of
The resonant tunneling diode 50 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by chemical vapor deposition or ozone oxidation instead of thermal oxidation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Although the silicon substrate 1 has the (001) plane orientation, it may have any plane orientation as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

(Sixth Embodiment) A resonance tunnel diode 60 according to a sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 25 (a) is a top view of the resonant tunneling diode 60 according to the present invention, and FIGS. 25 (b) and 25 (c) are respectively lines XX 'in the top view of FIG. 25 (a).
3 is a cross-sectional view taken along line YY ′. Also, FIG.
(A) and (c), FIG. 27 (a) and (c), FIG.
(A) and (c), and FIG. 29 (a) are process top views showing the manufacturing process of the resonant tunneling diode 60, and FIGS. 26 (b) and (d), 27 (b) and (d). 28 (b) and (d), and FIG.
26 (b) are respectively FIG. 26 (a), FIG. 26 (c), and FIG.
7 (a), FIG. 27 (c), FIG. 28 (a), FIG.
FIG. 30C is a sectional view taken along line XX ′ in FIG. 29A. In the drawings, the same components are designated by the same reference numerals. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The resonance tunnel diode 60 of the sixth embodiment is different from that of the first embodiment in that FIG.
As shown in (a) to (c), a pair of tunnel barrier materials sandwiching the silicon thin plate 107 to be a quantum well are asymmetric. That is, the silicon thin plate 107
Although the tunnel barrier on the lower surface of the silicon oxide film 108 is the tunnel barrier 401 on the upper surface of the silicon thin plate 107.
Is a silicon oxide film 10 such as calcium fluoride CaF ₂ film.
8 and a film made of a material different from that of No. 8.

In the resonance electron tunnel diode, the magnitude of the peak current and its half-value width can be changed by changing the height of the tunnel barrier on the electron incident side. For example, the potential height is about 3.1 eV
If a CaF ₂ film having a potential height of about 1 eV is used instead of the silicon oxide film as in this embodiment like the resonant tunneling diode 60, the full width at half maximum of the peak current becomes broader, but It is possible to obtain a high peak current value. As a result, if the resonant tunneling diode 60 of the present embodiment is used in a portion of the integrated circuit element that requires high speed, the operation speed of the obtained integrated circuit element can be increased.

Next, FIGS. 26A to 26D and FIG.
(A)-(d), FIG. 28 (a)-(d), and FIG.
A method of manufacturing the resonant tunneling diode 60 of the present embodiment will be described with reference to 9 (a) and 9 (b). However, the steps up to the step corresponding to FIG. 27D are the same as the corresponding steps in the first embodiment described above, and thus the description thereof is omitted here.

After the polysilicon layer 106 is formed, a high-concentration phosphorus diffusion step using POCl ₃ gas is performed at a temperature of about 900 ° C. for about 20 minutes, so that the concentration of phosphorus is about 1 × 10 ¹⁹ cm ⁻³ or more. Is added to the polysilicon layer 106. After that, by photolithography and patterning,
As shown in FIG. 28A, a second resist 109 having a predetermined pattern is formed. Then, SiCl ₄ , CH ₂ F
_The polysilicon layer 106 is patterned by dry etching using ₂ , SF ₆ and O ₂ gas. As a result, as shown in FIG. 28B, the first electrode 111
Is formed.

Here, in the present embodiment, unlike the first embodiment, the second resist 109 is not formed on the silicon thin plate 107. Therefore, the polysilicon layer 106 on the silicon thin plate 107 is completely removed by the dry etching process, and the silicon oxide film 108 is exposed (see FIG. 28B).

After that, as shown in FIGS. 28C and 28D, the second resist 109 is removed, and the interlayer insulating film 1 is removed.
13 is deposited by LPCVD to a thickness of about 200 nm.
Then, an opening mask pattern having a size of about 1 μm × about 1 μm is formed on the silicon thin plate 107 by the photolithography method. Then, the surface of the silicon thin plate 107 is exposed by dry etching using CF ₄ and O ₂ gas. Further, by the MBE method, C having a thickness of about 1.5 nm is formed on the exposed surface of the silicon thin plate 107.
The aF ₂ film is deposited to form the second tunnel barrier 401.

After that, polysilicon added with phosphorus at a concentration of about 1 × 10 ¹⁹ cm ^-3 or more is deposited by the LPCVD method, and the polysilicon is patterned by the photolithography and the dry etching method. The electrode 112 is formed directly on the silicon thin plate 107 (FIG. 28D). According to the manufacturing method of the present embodiment, the Fermi level in both electrodes 111 and 112 is made different by changing the doping concentration of impurities between the first electrode 111 and the second electrode 112. It is possible to

Further, as shown in FIGS. 29A and 29B, a second interlayer insulating film 402 is deposited to a thickness of about 200 nm by the LPCVD method, and the first electrode 111 and the first electrode 111 and the first electrode 111 are formed by the photolithography method. A mask pattern having an opening at a position corresponding to the second electrode 112, and CF
₄ and O ₂ gas is used to form the second interlayer insulating film 40 in the opening.
Remove 2. After that, the aluminum film is sputtered to about 1
29 μm thick and further patterned to form FIG.
A third electrode 114 as shown in (a) and (b) is formed.

Subsequent manufacturing steps are the same as the manufacturing steps described with reference to FIGS. 4 (a) to 4 (e) with respect to the first embodiment, and a description thereof will be omitted here.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier consisting of 8 / a quantum well by a silicon thin plate 107 / a second tunnel barrier 401, and a first electrode 111 and a second barrier structure.
The resonant tunneling diode 60 of the sixth embodiment of the present invention is formed, which includes the electrode 112 and the third electrode 114 for controlling the potential of the quantum well.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by chemical vapor deposition or ozone oxidation instead of thermal oxidation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Although the silicon substrate 1 has the (001) plane orientation, it may have any plane orientation as long as it can form an SOI substrate.

Further, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, instead of forming the second electrode 112 of polysilicon, the third electrode 104 which directly contacts the second tunnel barrier 401 may be formed.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

Further, in the configurations described in the second to fifth embodiments of the present invention, the first tunnel barrier and the second tunnel barrier may be formed asymmetrically as described above.

(Seventh Embodiment) A resonant tunneling diode 70 according to a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 30 (a) is a top view of the resonant tunneling diode 70 of the present invention, and FIGS. 30 (b) and 30 (c) are respectively lines XX 'in the top view of FIG. 30 (a).
3 is a cross-sectional view taken along line YY ′. FIG.
(A) and (c), FIG. 32 (a) and (c), and FIG. 33 (a) and (c) show the resonant tunneling diode 7.
31 is a process top view showing a manufacturing process of No. 0, and FIG.
32 (b) and (d), FIGS. 32 (b) and (d), and FIGS. 33 (b) and (d) show FIGS. 31 (a), 31 (c), 32 (a), and 32 (a), respectively. 32 (c), FIG.
(A), FIG. 32 (c), FIG. 33 (a), and FIG.
It is sectional drawing in line XX 'of (c). In the drawings, the same components are designated by the same reference numerals.
Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The resonant tunnel diode 70 of this embodiment.
However, the difference from the resonant tunneling diode 10 of the first embodiment is that the silicon thin plate 107 and the silicon oxide film 108 are different.
In the resonant tunneling diode 10 of the first embodiment, both ends of the double barrier structure 1000 composed of and are supported by the silicon substrate 1, whereas in the resonant tunneling diode 70 of the present embodiment, the double barrier structure 1000 is processed on the mesa. That is, the peripheral portion of the double barrier structure 1000 is covered with an interlayer insulating film 113 such as a silicon oxide film. As a result, the leakage current path is extremely reduced,
It is possible to significantly reduce the valley current, and it is possible to achieve a high PV ratio. Also, by using the mesa structure, mechanical stress that may be applied to the double barrier structure 1000 is also reduced.

Next, FIGS. 31A to 31D and FIG.
A method for manufacturing the resonant tunneling diode 70 of the present embodiment will be described with reference to (a) to (d) and FIGS. 33 (a) to (d). However, among these steps, the steps up to the step corresponding to FIG. 33B are the same as the corresponding steps in the first embodiment described above, and thus the description thereof is omitted here.

In the manufacturing method of the first embodiment, as shown in FIG.
Polysilicon layer 1 described with reference to (a) and (b)
The first and second electrodes 1 by the dry etching of 06.
In the step of forming 11 and 112, the silicon oxide film 10 is formed.
The etching is terminated when 8 is exposed. On the other hand, in the present embodiment, the silicon thin plate 107 and the lower silicon oxide film 108 are formed by the dry etching.
And the cross-sectional shape of the double barrier structure 1000 is processed into a mesa shape.

Subsequent manufacturing steps are the same as the manufacturing steps described with reference to FIGS. 4C and 4D for the first embodiment, and a description thereof will be omitted here.

Through the above series of steps, the silicon oxide film 10 is formed.
Double barrier structure 1000 composed of a tunnel barrier composed of 8 / a quantum well by a silicon thin plate 107 / a tunnel barrier composed of a silicon oxide film 108, and a potential control of a quantum well of the first electrode 111 and the second electrode 112. And a third electrode 114 of
The resonant tunneling diode 70 of the above embodiment is formed.

The silicon oxide film 108 functioning as a tunnel barrier may be formed by a chemical vapor deposition method or an ozone oxidation method instead of the thermal oxidation formation. Alternatively, a nitride film formed by thermal nitriding in a nitrogen atmosphere or a chemical vapor deposition method, a oxynitride film, or a SiGe film formed by crystal growth, a CaF ₂ film, or SiC
It may be a membrane.

Although the silicon substrate 1 having the (001) plane orientation is used, any plane orientation substrate may be used as long as it can form an SOI substrate.

Furthermore, the conductivity type of the upper silicon layer 100 may be p-type, and the first and second electrodes 111 and 112 may be formed of polysilicon in which p-type impurities are diffused.

Further, the third electrode 114 may be formed by using other metal instead of aluminum.

Further, in the above steps, the SOI substrate 90
By oxidizing a part of the upper silicon layer 100 forming the
Alternatively, the upper silicon layer 100 may be processed into a mesa type by a dry etching method using the pattern of the pad oxide film / nitride film multilayer film 101 as a mask, thereby realizing the separation.

Further, as described in the sixth embodiment,
The tunnel barriers may be formed asymmetrically above and below the silicon thin plate.

(Eighth Embodiment) Next, as an eighth embodiment of the present invention, a memory element 4000 to which a resonant tunneling diode constructed according to the present invention is applied will be described with reference to the drawings.

FIG. 34 (a) is a top view of a memory element 4000 to which a resonant tunnel diode is applied in the eighth embodiment of the present invention, and FIG. 34 (b) is shown in FIG.
It is sectional drawing in line XX 'of (a). The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 34B, the memory element 4
000 includes two resonant tunneling diodes 2000 and 3000. The two resonant tunneling diodes 2000 and 3000 each have the configuration of the resonant tunneling diode 10 described in the first embodiment of the present invention, and are insulated and separated from each other by the field oxide film 102. The memory element 4000 is configured by being connected in series via the electrode 111 of FIG. In addition, in FIGS. 34A and 34B, the third electrode 114 is 3
Although they are formed at the locations, they respectively function as a ground (GND) terminal, a power supply voltage (Vdd) terminal, and an applied voltage (Vd) terminal of the memory element 4000.

Memory device 4000 configured as described above
The operation principle of the operation will be described with reference to FIG. FIG. 35 shows a structure between the third electrode 114 for applied voltage (Vd) and the third electrode 114 for ground (GND) in the configuration of the memory element 4000 shown in FIGS. 34 (a) and 34 (b). Is a current-voltage characteristic that shows the relationship between the applied voltage V of 1 and the current I flowing through the memory element 4000.

In this case, the first resonant tunneling diode 2000 exhibits the same current-voltage characteristic (a) as that when it exists alone. On the other hand, the second resonant tunnel diode 3000 functions as a load. Therefore, the voltage-current characteristic (b), that is, the load curve has a shape in which the current-voltage characteristic when existing in a simple substance is inverted. As a result, as shown in FIG. 35, there are three intersections of the voltage-current characteristic curves (a) and (b) of the two resonant tunneling diodes, but the memory element 400
As a whole of 0, from the theorem of minimum entropy generation,
Of these, only two points (S1 and S2) on both sides are realized. The third intersections other than these are unstable points,
If a voltage smaller than the voltage value corresponding to the unstable point is applied, the state of the memory element 4000 changes to the point S1. In addition, if a voltage that is a little higher than the voltage value corresponding to this unstable point is applied, the memory device 4000
State changes to point S2.

As a result, the memory device 4000 functions as a bistable memory.

In the above description, the memory device 400
The two resonant tunneling diodes constituting 0 have the configuration of the resonant tunneling diode 10 of the first embodiment, but the same effect can be obtained by using the resonant tunneling diodes of other embodiments of the present invention. A memory element having the same can be configured.

(Ninth Embodiment) Next, as a ninth embodiment of the present invention, a memory element 5000 to which a resonance tunnel diode constructed according to the present invention is applied will be described with reference to the drawings.

FIG. 36 (a) is a top view of a memory device 5000 to which a resonant tunnel diode is applied in the ninth embodiment of the present invention, and FIG. 36 (b) is shown in FIG.
It is sectional drawing in line XX 'of (a). The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 36B, in the memory device 5000 of this embodiment, one resonance tunnel diode 5100 and the first interlayer insulating film 113 are formed on the first electrode 111 of the resonance tunnel diode 5100. And a polysilicon film 405 which is connected in series via the interposer. The polysilicon film 405 functions as a load resistance. The resonant tunnel diode 5100 has the configuration of the resonant tunnel diode 10 described in the first embodiment of the present invention.

Memory device 5000 configured as described above
The operation principle of the operation will be described with reference to FIG. FIG. 37 shows two third electrodes 1 in the configuration of the memory device 5000 shown in FIGS.
The applied voltage V between 14 and thus the memory device 50
00 is a current-voltage characteristic showing the relationship with the current I flowing through the signal 00.

Between the characteristic (a) of the resonant tunnel diode 5100 exhibiting a negative resistance characteristic and the characteristic (b) of the polysilicon film 405 functioning as a load resistance, there are three locations as shown in FIG. There is an intersection. However, as described above with respect to the eighth embodiment, among these, the two that are actually stable are S1 and S2. Therefore, the memory device 5000 of this embodiment also functions as a bistable memory.

The larger the resistance value of the polysilicon film 405, the smaller the inclination of the graph (b) showing its characteristics.
A large difference between the stable points S1 and S2 can be taken. In the case of this embodiment, the resistance value is set to an arbitrary value by changing the dose amount when the impurity atoms such as phosphorus are ion-implanted into the polysilicon film 405, and the operation characteristics as the memory element 5000 are appropriately set. Can be set.

In the above description, the memory element 500 is used.
The resonant tunneling diode 5100 forming 0 is the first
Although the resonant tunnel diode 10 according to the embodiment has the configuration, the resonant tunnel diode according to another embodiment of the present invention can be used to configure a memory element having a similar effect.

(Tenth Embodiment) Next, the first embodiment of the present invention will be described.
As a No. 0 embodiment, a memory device 6000 to which a resonant tunnel diode configured according to the present invention is applied will be described with reference to the drawings.

FIG. 38 (a) is a top view of a memory device 6000 to which a resonant tunnel diode is applied in the tenth embodiment of the present invention, and FIG. 38 (b) is shown in FIG.
It is sectional drawing in line XX 'of (a). The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 38B, the memory device 6000 of this embodiment has one resonance tunnel diode 6100 and the first interlayer insulating film 113 on the first electrode 111 of the resonance tunnel diode 6100. And a depletion type MOSFET 6200 connected in series via
have. Here, as shown in FIG.
The source terminal 303 and the gate terminal 304 on the first electrode 111 side of the OSFET 6200 are short-circuited and operate in a normally-on type. The resonant tunnel diode 6100 has the configuration of the resonant tunnel diode 10 described in the first embodiment of the present invention.

Memory device 6000 configured as described above
The operation principle of the operation will be described with reference to FIG. FIG. 39 shows two third electrodes 1 in the configuration of the memory device 6000 shown in FIGS.
Applied voltage V between 14 and thereby the memory element 60
00 is a current-voltage characteristic showing the relationship with the current I flowing through the signal 00.

Between the characteristic (a) of the resonant tunnel diode 6100 exhibiting a negative resistance characteristic and the characteristic (b) of the depletion type MOSFET 6200 functioning as a resistance load, there are three points as shown in FIG. There is an intersection of. However, as described above with respect to the eighth embodiment, among these, it is S1 and S that actually become stable.
There are two points. From this, the memory device 6 of the present embodiment
000 also functions as a bistable memory.

In the case of this embodiment, the resonance tunnel diode 6100 and the depletion type MOSFET 6200 are used.
Since and are formed on the same substrate, it is possible to use a CMOS circuit (not shown) to read the signal of the memory element 6000.

In the above description, the depletion type MOSF in which the source electrode and the gate electrode are short-circuited.
Although it is configured to have the ET6200 as a load,
Instead, an enhancement-type MOSFET in which the drain electrode and the gate electrode are short-circuited may be used as a load.

Furthermore, in the above description, the memory element 60 is used.
The resonant tunneling diode 6100 that forms No. 00 has the configuration of the resonant tunneling diode 10 of the first embodiment, but the same effect can be obtained by using the resonant tunneling diode of another embodiment of the present invention. A memory element can be constructed.

[0203]

As described above, in the quantization function device of the present invention, the portion functioning as the quantum well is the SOI.
It corresponds to the upper silicon layer of the substrate. Therefore, the crystallinity of the quantum well is as high in quality as the substrate. Further, since a good quality tunnel barrier can be formed by a silicon oxide film or the like, the height of the potential barrier is as high as about 3.1 eV. Furthermore, the interface between the quantum well and the tunnel barrier can be smoothed at the atomic level.

From the above, in the quantizing function element of the present invention, a very sharp quantizing level is formed in the quantum well, and a good electron resonant tunneling effect is obtained.
Therefore, as described above with reference to the respective embodiments, according to the present invention, it is possible to realize a quantization function element exhibiting excellent operation characteristics.

Further, according to the method for manufacturing a quantizing function element of the present invention, a silicon-based material generally used in a semiconductor element is used, and a quantum is produced by a commonly used semiconductor manufacturing technique such as thermal oxidation. A functionalized element can be manufactured. Furthermore, since the thickness of the quantum well, which greatly influences the device characteristics of the quantization function device, is set by a thermal oxidation process with extremely high controllability, an extremely thin silicon thin plate of about several nm is evenly distributed over the entire wafer surface. It can be installed with good performance. This makes it possible to obtain a high-performance quantization function device with high productivity.

Further, it is possible to easily manufacture an integrated circuit formed by mixing one or more quantization function elements and another semiconductor element such as MOSFET on the same substrate.

[Brief description of drawings]

FIG. 1A is a top view showing a structure of a resonant tunneling diode according to a first embodiment of the present invention,
(B) And (c) is the sectional view.

2A and 2C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 1, and FIGS. 2B and 2D correspond to FIGS. FIG.

3A and 3C are process top views showing a method for manufacturing the resonant tunnel diode of FIG. 1, and FIGS. 3B and 3D correspond to FIGS. 3A and 3C, respectively. FIG.

4 (a) and 4 (c) are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 1, and FIGS. 4 (b) and 4 (d) correspond to (a) and (c), respectively. FIG.

5 is a diagram showing a current-voltage characteristic of the resonant tunneling diode according to the related art and a current-voltage characteristic of the resonant tunneling diode of FIG.

FIG. 6A is a top view showing a structure of a resonant tunneling diode according to a second embodiment of the present invention,
(B) And (c) is the sectional view.

7A and 7C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 6, and FIGS. 7B and 7D correspond to FIGS. FIG.

8A and 8C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 6, and FIGS. 8B and 8D correspond to FIGS. 8A and 8C, respectively. FIG.

9A and 9C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 6, and FIGS. 9B and 9D correspond to FIGS. 9A and 9C, respectively. FIG.

10A is a process top view showing the method of manufacturing the resonant tunneling diode of FIG. 6, and FIG. 10B is a process cross-sectional view corresponding to FIG.

FIG. 11A is a top view showing a structure of a resonant tunnel diode according to a third embodiment of the present invention,
(B) And (c) is the sectional view.

12A and 12C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 11, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

13A and 13C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 11, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

14A and 14C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 11, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

15A is a process top view showing a method of manufacturing the resonant tunneling diode of FIG. 11, and FIG. 15B is a view of FIG.
FIG.

FIG. 16 (a) is a top view showing a structure of a resonant tunnel diode according to a fourth embodiment of the present invention,
(B) And (c) is the sectional view.

17A and 17C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 16, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

18A and 18C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 16, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

19A and 19C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 16, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

20 is a diagram showing current-voltage characteristics of the resonant tunnel diode of FIG.

FIG. 21 (a) is a top view showing a structure of a resonant tunneling diode according to a fifth embodiment of the present invention,
(B) And (c) is the sectional view.

22 (a) and 22 (c) are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 21;
7A and 7D are process cross-sectional views corresponding to FIGS.

23A and 23C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 21, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

24 (a) and 24 (c) are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 21;
7A and 7D are process cross-sectional views corresponding to FIGS.

FIG. 25A is a top view showing a structure of a resonant tunnel diode according to a sixth embodiment of the present invention,
(B) And (c) is the sectional view.

26A and 26C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 25, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

27A and 27C are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 25, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

28A and 28C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 25, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

FIG. 29A is a process top view showing the method of manufacturing the resonant tunneling diode of FIG. 25, and FIG.
FIG.

FIG. 30 (a) is a top view showing the structure of a resonant tunnel diode according to a seventh embodiment of the present invention,
(B) And (c) is the sectional view.

31A and 31C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 30, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

32A and 32C are process top views showing a method for manufacturing the resonant tunneling diode of FIG. 30, and FIG.
7A and 7D are process cross-sectional views corresponding to FIGS.

33 (a) and 33 (c) are process top views showing a method of manufacturing the resonant tunneling diode of FIG. 30;
7A and 7D are process cross-sectional views corresponding to FIGS.

34A is a top view showing a structure of a memory element according to an eighth embodiment of the present invention, and FIG. 34B is a sectional view thereof.

35 is a diagram showing current-voltage characteristics of the memory device of FIG. 34.

36A is a top view showing a structure of a memory element according to a ninth embodiment of the present invention, and FIG. 36B is a sectional view thereof.

FIG. 37 is a diagram showing current-voltage characteristics of the memory device of FIG. 35.

38A is a top view showing the structure of the memory element according to the tenth embodiment of the present invention, and FIG. 38B is a sectional view thereof.

39 is a diagram showing current-voltage characteristics of the memory device of FIG. 38.

40 (a) to 40 (d) are cross-sectional views showing an example of a conventional method for manufacturing a resonant tunnel diode using a compound semiconductor material.

41 (a) to 41 (e) are cross-sectional views showing an example of a conventional method for manufacturing a resonant tunneling diode using a silicon-based material.

[Explanation of symbols]

 1 Silicon Substrate 10 Resonant Tunneling Diode 20 Resonant Tunneling Diode 30 Resonant Tunneling Diode 40 Resonant Tunneling Diode 50 Resonant Tunneling Diode 60 Resonant Tunneling Diode 70 Resonant Tunneling Diode 90 Silicon-on-Insulator (SOI) Substrate 99 Embedded Silicon Oxide Layer 100 Top Silicon Film layer 101 Pad oxide film / nitride film multilayer film 102 Field oxide film 103 Silicon island 104 First resist 105 Resist opening 106 Polysilicon layer 107 Silicon thin plate 108 Silicon oxide film 109 Second resist 111 First electrode 112 Second electrode 113 Interlayer insulating film 114 Third electrode 200 p-type silicon thin plate 201 n-type silicon thin plate 300 Second nitride film 301 Second resist 302 Exposed part of silicon substrate 303 Source / drain 304 Gate electrode 400 Oxidized silicon thin plate 401 Second tunnel barrier 402 Second interlayer insulating film 405 Polysilicon for load resistance 1000 Double barrier structure 2000, 3000 Resonant tunnel diode 4000 Memory element 5000 Memory element 5100 Resonant tunnel diode 6000 Memory element 6100 Resonant tunnel diode 6200 MOSFET

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kiyoyuki Morita 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (33)

[Claims] 1. A silicon thin plate made of a silicon single crystal having first and second faces having predetermined crystal faces and having a thickness sufficiently thin to function as a quantum well, and the silicon thin plates, respectively. A pair of tunnel barriers formed along the first and second faces of the silicon thin plate and the pair of tunnel barriers operatively coupled to each other formed so as to sandwich the silicon thin plate and the pair of tunnel barriers from both sides. A quantization function element comprising: a first electrode and a second electrode. 2. The quantization function element according to claim 1, wherein the silicon thin plate is at least partially a substantially free-standing structure. 3. The quantization function element according to claim 1, further comprising a third electrode operably coupled to the silicon thin plate. 4. The quantization function element according to claim 1, wherein the first and second electrodes are made of polysilicon or single crystal silicon. 5. The structure is formed on a silicon layer having a first conductivity type, and at least a part of the silicon thin plate has a second conductivity type opposite to the first conductivity type. The quantization function element according to any one of claims 1 to 4, to which an impurity having is added. 6. The quantization according to claim 1, wherein at least a part of the silicon thin plate other than a part located immediately below the second electrode is completely oxidized. Functional element. 7. The thickness of the pair of tunnel barriers is different between the side of the first surface and the side of the second surface of the silicon thin plate. Quantization function element. 8. The pair of tunnel barriers comprises SiO ₂ ,
SiN, silicon oxynitride, SiC, CaF ₂ , and S
The quantization function element according to any one of claims 1 to 7, which is a film made of a material selected from the group consisting of iGe. 9. The thin silicon plate has a thickness of about 0.3 nm.
9. The quantization function element according to claim 1, wherein the quantization function element is set in the range of about 100 nm. 10. The quantization function element according to claim 1, which is a resonance tunnel diode. 11. The quantizing functional element according to claim 1, comprising an electrode and a plurality of quantizing functional elements operably coupled in series through the electrode. A quantization function device that is a quantization function element. 12. A quantization function element formed on a silicon-on-insulator substrate, a MOS transistor formed on the silicon-on-insulator substrate, a quantization function element and the MOS transistor. And a conductive layer that operably couples with each other, wherein the quantization function element is the quantization function element according to any one of claims 1 to 10. 13. A quantizing function element formed on a silicon-on-insulator substrate, a MOS type transistor formed on the silicon-on-insulator substrate, the quantizing function element and the MOS-type transistor. And an electrode operably coupled to the quantization function element, wherein the quantization function element is the quantization function element according to any one of claims 1 to 10. 14. The memory device according to claim 11, which is a memory device.
3. The quantization function device according to any one of 3 above. 15. A method of manufacturing a quantization function element, the method comprising: forming a silicon island on a silicon-on-insulator substrate including a silicon substrate, a buried insulating layer, and an upper silicon layer; and functioning as a quantum well. 1st thick enough to
And a step of forming a silicon thin plate having a second surface, a step of forming a pair of tunnel barriers along the first and second surfaces of the silicon thin plate, and the silicon thin plate and the pair of tunnel barriers. Forming a first and a second electrode operatively coupled to each other, sandwiching the tunnel barrier from both sides, and manufacturing a quantization function element. 16. The step of forming the silicon thin plate, a step of removing a part of the buried insulating film layer directly below the silicon island to process the silicon island into the silicon thin plate, and at least one of the silicon thin plates. 16. The method for manufacturing a quantization function element according to claim 15, further comprising a step of forming a portion into a free-standing structure. 17. The step of forming the silicon thin plate, the step of removing a part of the buried insulating film layer directly under the silicon island to form at least a part of the silicon island into a free standing structure, and the free standing. 16. The method for manufacturing a quantization function element according to claim 15, further comprising the step of processing at least a part of a structure into the silicon thin plate. 18. The step of forming the first and second electrodes comprises the step of depositing a polysilicon layer on the surface of the silicon-on-insulator substrate, and the polysilicon layer having the same conductivity type as the upper silicon layer. A step of adding the impurities contained therein in a high concentration, and patterning the polysilicon layer to form the first and second polysilicon layers.
Forming an electrode according to claim 15.
A method for manufacturing a quantization function element according to any one of 1. 19. The step of forming the silicon thin plate includes the step of removing the buried insulating film layer directly under the silicon island to form at least a part of the silicon island into a free-standing structure. In the step of forming the second electrode, a step of exposing a part of the silicon substrate immediately below the free-standing structure and a lateral epitaxial crystal growth using the exposed part as a seed to form a single crystal silicon film. A step of adding an impurity having the same conductivity type as that of the upper silicon layer to the single crystal silicon film, a step of patterning the single crystal silicon film to form the first and second electrodes, 15. Including
7. The method for manufacturing a quantization function element according to any one of 7. 20. The step of forming the pair of tunnel barriers comprises the step of forming the silicon barrier from the second surface of the silicon thin plate.
Forming a first tunnel barrier on the first surface of the silicon sheet proximate to the on-insulator substrate; and forming a second tunnel barrier of the silicon sheet on the opposite side of the first surface of the silicon sheet. Forming a second tunnel barrier on the surface, and forming the first and second electrodes comprises depositing a first polysilicon layer on a surface of the silicon-on-insulator substrate. Adding a high concentration of an impurity having the same conductivity type as the upper silicon layer to the first polysilicon layer; patterning the first polysilicon layer to form a layer on the first tunnel barrier; Forming the first electrode, forming a first insulating film on the surface of the silicon-on-insulator substrate, and forming an opening in the first insulating film directly above the first electrode. Through the opening Exposing a part of the silicon thin plate; depositing a second polysilicon layer on the surface of the silicon-on-insulator substrate; and having the same conductivity type as the upper silicon layer on the second polysilicon layer. A step of adding impurities having a concentration of 2 to a high concentration, and patterning the second polysilicon layer to form a second electrode on the second tunnel barrier formed on the exposed portion. The method for manufacturing a quantization function element according to claim 15, further comprising: 21. In the step of forming the silicon island, a part of the upper silicon layer of the silicon-on-insulator substrate is oxidized to form a silicon oxide film, and the embedded insulating film layer and the silicon oxide film are formed. 21. The method for manufacturing a quantization function element according to claim 15, further comprising the step of forming silicon islands separated by. 22. The quantization function element according to claim 15, wherein the step of forming the silicon islands includes a step of removing the upper silicon layer other than the formation area of the silicon islands by etching. Production method. 23. The method of manufacturing a quantization function element according to claim 15, further comprising the step of forming a third electrode operably coupled to the silicon thin plate. 24. The step of forming the third electrode comprises the step of forming an insulating layer covering the first and second electrodes, and depositing and patterning a conductive layer on the surface of the insulating layer to form the insulating layer. 24. The method of manufacturing a quantization function element according to claim 23, comprising the step of forming an electrode of No. 3. 25. The step of forming the third electrode comprises the step of thermally oxidizing the silicon-on-insulator substrate, the step of forming an insulating layer covering the first and second electrodes, and the insulating layer. 24. A method of manufacturing a quantization function element according to claim 23, further comprising: depositing and patterning a conductive layer on a surface of the substrate to form the third electrode. 26. After the step of forming the first and second electrodes, the silicon thin plate is self-aligned with an impurity having a conductivity type opposite to that of the upper silicon layer by using the second electrode as an implantation mask. 26. The method for producing a quantization function element according to claim 15, further comprising: a step of introducing into the semiconductor device, and a step of performing heat treatment for activating the introduced impurities. 27. The step of forming the pair of tunnel barriers includes a thermal oxidation method, a plasma oxidation method, a thermal nitriding method, a chemical vapor deposition method of a silicon oxide film, a chemical vapor deposition method of a silicon nitride film,
Chemical vapor deposition method of silicon oxynitride film, crystal growth method of SiC film, molecular beam epitaxy method of CaF ₂ film, and SiG
27. The method for manufacturing a quantization function element according to claim 15, wherein a method selected from the group consisting of a crystal growth method of an e film is used. 28. The quantization function element according to claim 15, wherein in the step of forming the silicon thin plate, the thickness of the silicon thin plate is set within a range of about 0.3 nm to about 100 nm. Production method. 29. The method of manufacturing a quantization function element according to claim 15, wherein a resonance tunnel diode is formed. 30. A step of forming a plurality of quantization function elements, and a step of forming an electrode operably coupling the plurality of quantization function elements in series, the formation of the quantization function element. In the process, claims 15 to 29
A method of manufacturing a quantization function device, using the method according to any one of 1. 31. A step of forming a quantization function element, and a step of forming a resistive load operably connected to the quantization function element in series, the step of forming the quantization function element. Then, claims 15 to 29
A method of manufacturing a quantization function device, using the method according to any one of 1. 32. A step of forming a quantization function element on a substrate, a step of forming a MOS type transistor on the substrate, and enabling the quantization function element and the MOS type transistor to operate in series. 30. The step of forming the quantization functional element, the method including the steps of:
A method of manufacturing a quantization function device, using the method according to any one of 1. 33. A memory device is formed.
33. A method of manufacturing a quantization function device according to any one of 1 to 32.