JPH07326737A - Impedance line, filter element, delay element and semiconductor device - Google Patents

Abstract

PURPOSE:To form a delay element and the like without being accompanied by a new layer on an active element by a method wherein a two-dimensional electron gas layer on the junction interface between first and second compound semiconductor layers is left into a linear form, electrodes are provided on parts, which are respectively located on both ends of the linear gas layer, of the second compound semiconductor layer and diffused layers, which reach the gas layer, are respectively formed under the electrodes. CONSTITUTION:A first compound semiconductor layer 13 is laminated on a conductive substrate 11 and a second compound semiconductor layer 14 of a composition different from that of the layer 13 is laminated on the layer 13. A two-dimensional electron gas layer is formed on a junction between the layers 13 and 14. The gas layer is left into a linear form, electrodes 18 and 19 are respectively provided on parts, which are respectively located on both ends of the linear gas layer, of the layer 14 and diffused ohmic layers 17, which reach the gas layer, are respectively formed under the electrodes 18 and 19. Thereby, it is made possible to realize a delay element, which can be formed without being accompanied by a new layer structure on an active element, such as a transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance line, a filter element, a delay element and a semiconductor device using a two-dimensional electron gas layer utilizing a heterostructure of a compound semiconductor as a carrier.

[0002]

2. Description of the Related Art In general, a semiconductor device using a compound semiconductor can be operated at a higher speed and a higher frequency than a device using a silicon semiconductor, and therefore its use is gradually expanding. A semiconductor device is a device in which a plurality of elements are integrated on one substrate, and in a compound semiconductor device,
Due to its excellent characteristics in the high frequency region, there is a semiconductor device in which a transistor such as a high frequency amplifier circuit, a signal delay circuit and a filter circuit are integrated on the same substrate.

The filter circuit includes an active filter composed of only active elements such as transistors and a passive filter composed of resistors and capacitors, and any of them is integrated with a semiconductor device on the same substrate. It is possible to

As an active filter, for example, Japanese Patent Publication No. 55-40189 discloses an active filter in which two kinds of transistors having different cutoff frequencies are formed on the same substrate and the transistor having the lower cutoff frequency is used as a filter. ing. On the other hand, since the passive filter is configured only by resistors and capacitors, it does not include active elements whose element characteristics change due to manufacturing variations, and thus it is easy to obtain desired filter characteristics.

However, forming two types of transistors having different cutoff frequencies on the same substrate of the active filter as described in the above-mentioned publication makes it possible to manufacture the active filter as compared with the case of forming one transistor having one cutoff frequency. There is a problem that I have to do if the process becomes complicated.

In order to construct a passive filter, it is impossible to fabricate an inductor on a semiconductor substrate. Therefore, a passive filter is formed by combining a resistor and a capacitor. The resistor is formed on the semiconductor substrate. In order to achieve this, in the case of a silicon substrate, a layer in which impurities are diffused in silicon can be used, but in the case of a compound semiconductor using a heterostructure, the method of diffusing impurities cannot be used. After forming, an insulating film is once deposited on the substrate, a metal film is laminated on the insulating film, and this is patterned to form a resistor. The reason why the diffusion method is not used is that when the temperature is high enough to diffuse the impurities, the semiconductor composition and the impurity concentration distribution that are made so as to be steep in the portion where the hetero structure is formed are not steep, and the function of the hetero structure is eliminated. Is dropped. Further, in order to form a capacitor on a semiconductor substrate, it is obtained by forming an insulating film or a metal film after forming a transistor or the like. However, in the case of a compound semiconductor device, it is not easy to stack an insulating film and a metal film, unlike a semiconductor device made of a silicon semiconductor, so that the manufacturing process is complicated.

This is because in the case of a silicon semiconductor, a silicon oxide film or a nitride film, which is an insulating film, can be easily formed, and it is a very stable substance having high resistance to acids, alkalis, and heat. While it is easy to form many layers of insulating film and metal film, it is difficult to form the insulating film itself in a compound semiconductor device. For example, in GaAs, which is a typical compound semiconductor, gallium oxide is used. Some Ga ₂ O ₃ are not stable and are also Ga
N is a semiconductor and cannot be used as an insulating film. Therefore SiO ₂ and by the CVD method in many compound semiconductor device _{Si 3 N 4, SiON (Silicon} Oxi-Nitride) is used as the insulating film by depositing the like, SiO ₂ or Si ₃ N ₄ is also at this However, it is still difficult to obtain a multi-layer structure such as a silicon semiconductor device, and the yield is low.

There is also an example in which polyimide is used as an insulating film between wiring layers to perform multilayer wiring (Maya Koyanagi, Yoshiaki Kaneko, Kohei Nagata, Haruo Shimizu, Masaaki Okamoto, Shimizu).
Satoshi: “25K Gate GaAs Gate Array,” IEICE Technical Report MW93-108, (MW93
-105 to 113, pp. 23-29), 1994 1
Month). However, since polyimide has film shrinkage, there is a problem that the polyimide film shrinks by the time it is hardened after application, causing stress in the film and making cracks easily. Further, since polyimide has a hygroscopic property, deterioration of the film itself, the wiring material in the film, and the wiring material between the films over time is large, and there is a problem in reliability.

[0009]

Therefore, a first object of the present invention is to provide an impedance line, a filter element, a delay element, etc., which can be formed on an active element such as a transistor made of a compound semiconductor without a new layer structure. A second object is to provide a semiconductor device in which these passive elements and active elements such as transistors are integrated.

[0010]

According to the present invention for solving the above-mentioned object, a first compound semiconductor layer is provided on a conductive substrate, and the first compound semiconductor layer is provided on the first compound semiconductor layer. And a second compound semiconductor layer having a different composition from each other to form a two-dimensional electron gas layer at the bonding interface between the first compound semiconductor layer and the second compound semiconductor layer, and the two-dimensional electron gas An electrode is provided on the second compound semiconductor layer at both ends of the linear two-dimensional electron gas layer, and a diffusion layer reaching the two-dimensional electron gas layer is formed under the electrode while leaving the layer in a linear shape. Is an impedance line.

The present invention for solving the above-mentioned object provides a second compound having a composition different from that of a first compound semiconductor layer on a conductive substrate and a composition of the first compound semiconductor layer on the first compound semiconductor layer. By stacking the compound semiconductor layer of
A two-dimensional electron gas layer is formed at the junction interface between the compound semiconductor layer and the second compound semiconductor layer, and the two-dimensional electron gas layer is left linearly, and the two-dimensional electron gas layer is formed at both ends of the linear two-dimensional electron gas layer. In the filter element, an electrode is provided on the second compound semiconductor layer, and a diffusion layer reaching the two-dimensional electron gas layer is formed under the electrode.

The present invention for solving the above-mentioned object includes a second compound having a composition different from that of a first compound semiconductor layer on a conductive substrate and a composition of the first compound semiconductor layer on the first compound semiconductor layer. By stacking the compound semiconductor layer of
A two-dimensional electron gas layer is formed at the junction interface between the compound semiconductor layer and the second compound semiconductor layer, and the two-dimensional electron gas layer is left linearly, and the two-dimensional electron gas layer is formed at both ends of the linear two-dimensional electron gas layer. In the delay element, an electrode is provided on the second compound semiconductor layer, and a diffusion layer reaching the two-dimensional electron gas layer is formed under the electrode.

Further, the present invention for solving the above-mentioned object includes
The first compound semiconductor layer and the second compound semiconductor layer formed on the first compound semiconductor layer and the second compound semiconductor layer having a different composition formed on the first compound semiconductor layer and the second compound semiconductor layer on the conductive substrate.
A two-dimensional electron gas field effect transistor in which a two-dimensional electron gas layer is formed at the junction interface with the compound semiconductor layer and the source electrode, drain electrode and gate electrode are formed on the second compound semiconductor layer. In the integrated semiconductor device, the two-dimensional electron gas field effect transistors are left with a two-dimensional electron gas layer in a portion that needs to be electrically connected to each other, and a two-dimensional electron gas layer in a portion that does not need to be connected is formed. It is a semiconductor device characterized by being erased.

According to the present invention, since the two-dimensional electron gas layer of the portion connecting the plurality of two-dimensional field effect transistors is left and the two-dimensional electron gas layer of the portion not requiring the connection is eliminated, the connection is unnecessary. In the semiconductor device, the first compound semiconductor layer and the second compound semiconductor layer in a portion where the two-dimensional electron gas layer is formed are removed by etching.

Further, according to the present invention, since the two-dimensional electron gas layer of the portion connecting the plurality of two-dimensional field effect transistors is left and the two-dimensional electron gas layer of the portion which does not need to be connected disappears, the connection is unnecessary. The semiconductor device is characterized in that an electrode for applying a potential of 0 V or less is formed on the two-dimensional electron gas layer at a certain portion.

Further, according to the present invention, since the two-dimensional electron gas layer in the portion connecting the plurality of two-dimensional field effect transistors is left and the two-dimensional electron gas layer which does not need to be connected is extinguished, the connection becomes unnecessary. In the semiconductor device, oxygen ions are implanted into the first compound semiconductor layer and the second compound semiconductor layer in a portion where a two-dimensional electron gas layer is formed.

Further, the present invention is characterized in that a control electrode is provided on the second compound semiconductor layer in the portion where the two-dimensional electron gas layer of the portion connecting the plurality of two-dimensional field effect transistors is left. And a semiconductor device.

[0018]

According to the present invention configured as described above, the first compound semiconductor layer and the second compound semiconductor layer having a composition different from that of the first compound semiconductor layer are laminated on the conductive substrate to form a first compound semiconductor layer. A two-dimensional electron gas layer is formed at the interface between the first compound semiconductor layer and the second compound semiconductor layer. By using a conductive substrate, this two-dimensional electron gas layer becomes a conductive path having the substrate as a ground (GND) surface.

Therefore, in the present invention, the two-dimensional electron gas layer is linearly formed with an arbitrary width and length to form a transmission line, and electrodes are provided on the second compound semiconductor layers at both ends thereof. Provide as an impedance line.

The characteristics of the transmission line formed by the two-dimensional electron gas layer are a resistance component R, an inductance L component, and a capacitance component C. The resistance component R and the inductance component L are expressed by the following equations (1) and (2): Sheet resistance ρs or sheet inductance Ls and length x between electrodes of transmission line
/ Proportional to width w.

[0021]

## EQU1 ## R = ρs × (x / w) (1)

[0022]

[Equation 2] L = Ls × (x / w) (2) Further, the capacitance component C is proportional to Cs per unit area and the length x × width w between the electrodes of the transmission line as shown in the following equation (3). To do.

[0023]

## EQU3 ## C = Cs.times. (X.times.w) (3) Further, the characteristic impedance Z0 of the line is inversely proportional to the width of the transmission line, and becomes as shown in the following formula (4).

[0024]

[Equation 4]

In the equation (4), R0 is a resistance value per unit length of the transmission line, L0 is an inductance per unit length of the transmission line, and C0 is a capacitance per unit length of the transmission line.

The transmission line of the two-dimensional electron gas layer formed in a linear shape depends on the capacitance component formed between the conductive substrate and the resistance component of the transmission line, and when a high frequency is applied, the capacitance component and the resistance component. Since it functions as a CR filter having a time constant determined by the product of, the filter element functions as a low-pass filter that attenuates frequencies above the cutoff frequency determined by this time constant.

Further, this filter element becomes a delay element whose delay time is equal to the time constant of the filter element at a frequency sufficiently smaller than the cutoff frequency (about 1/10 or less). That is, it becomes a delay element in which the signal waveform on the input side appears on the output side with a delay by a time corresponding to the time constant.

Further, a control electrode is provided above the transmission line formed by the two-dimensional electron gas layer, and a voltage is applied to change the sheet resistance of the transmission line portion. It is possible to change the constant and the delay time of the delay element.

Further, in the present invention, a wiring for connecting the above-mentioned transmission line in which the two-dimensional electron gas layer is linearly formed between transistors in an integrated circuit or between a transistor and another element. By using this wiring portion as the impedance line and changing the width and length of the transmission line to obtain the desired characteristic impedance according to the equation (4), the impedance between the elements can be reduced. By performing matching and functioning as a filter element or a delay element, it is possible to integrate the filter element or the delay element into a semiconductor device in which wiring is incorporated. Of course, also in this case, by providing the control electrode on the transmission line used as the wiring, the characteristic impedance, the time constant of the filter element and the delay time of the delay element can be changed as described above.

[0030]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In addition, the same number is attached to the member having the same function.

Example 1 FIG. 1 shows an example of an impedance line, a filter element and a delay element to which the present invention is applied. FIG. 1a is a plan view thereof, and FIG. 1b is a sectional view taken along line AA in FIG. 1a. It is a figure and FIG. 1c is sectional drawing in the BB line in FIG. 1a.

The element of the first embodiment is an electrically conductive substrate n.
On the silicon substrate 11 having a specific resistance of 1 Ω · cm, a high-resistance buffer layer 12 made of a non-doped GaAs layer, and a non-doped high-purity i which is a first compound semiconductor layer thereon.
-The GaAs layer 13 and the n-AlGaAs layer 14 having a thickness of 500 Å doped with Si serving as an electron donating layer in the second compound semiconductor layer at about 1 × 10 ¹⁸ atoms cm ^-3 are laminated,
A two-dimensional electron gas layer (hereinafter referred to as a 2DEG layer) is formed at the heterojunction interface between the i-GaAs layer 13 and the n-AlGaAs layer 14, and the n-AlGaAs layer 14 is further formed.
On top of the cap layer 1 with a doped n-GaAs layer
5 is formed, AuGe / Ni is used as electrodes 18 and 19
/ Au is formed. Below the electrodes 18 and 19, an ohmic diffusion layer 17 made of an electrode metal reaching the 2DEG layer is formed. In the first embodiment, 2DE
In order to form the G portion in the linear transmission line 20 having an arbitrary width and length, unnecessary portions of the i-GaAs layer 13 and n-A
The lGaAs layer 14 was removed by etching. In addition,
In the first embodiment, the distance between the surface of the silicon substrate 11 and the 2DEG layer is such that the distance from the surface of the silicon substrate 11 to the i-GaAs layer 1
3 to the interface between the n-AlGaAs layer 14 and the n-AlGaAs layer 14, which is approximately 3.8 μm.

The transmission line 20 having the 2DEG layer left and the electrodes 18 and 19 at both ends thereof serve as an impedance line, and when used in a high frequency circuit, serve as a low pass filter element. It becomes a delay element at a frequency of 1/10 or less of the cutoff frequency of the low pass filter element.

The characteristics of the 2DEG layer may change depending on the conductivity type and the specific resistance of the silicon substrate used. Here, the 2D effect of the conductivity type and the specific resistance of this silicon substrate
The change in the EG layer characteristics will be described.

Silicon substrate and buffer layer GaAs
At the interface of the layers, regardless of the conductivity type of the silicon substrate, silicon diffuses into the GaAs layer and the thickness is as thin as about 100Å.
A mold layer is formed. The electrons donated from this n-type layer are G
It diffuses to the aAs layer and the silicon layer. The region in which the electrons are diffused is not a depletion layer but has high conductivity, and therefore acts to shorten the substantial distance between the 2DEG layer and the ground plane. The distance that the electrons diffuse into the GaAs layer is 1000Å, which is roughly 0.1μ.
Although it is about m, the distance to diffuse to the silicon substrate is
It depends on the conductivity type and specific resistance of the substrate.

Therefore, when the conductivity type of the silicon substrate is n-type, only the effect of the electrons from the n-type layer being donated to the GaAs layer is effective, so that the actual ground (GND) surface is the silicon substrate. It is about 0.1 μm into the GaAs layer from the interface of the GaAs layer which is the buffer layer.
Therefore, the distance between the 2DEG layer of Example 1 and the substantial ground plane is about 3.7 μm. In the case of this n-type silicon substrate, the specific resistance itself does not affect the characteristics of the 2DEG layer, so that any specific resistance may be used as long as it is commercially available. The 2DEG layer has a Ga of about 0.1 μm from the interface between the silicon substrate and the GaAs layer which is the buffer layer.
The capacitance component is determined by the distance from the position where it enters the As layer to the 2DEG layer.

On the other hand, when the conductivity type of the silicon substrate is p-type, a depletion layer is formed in the silicon substrate, so that a portion slightly entering the inside of the silicon substrate from the interface between the silicon substrate and the GaAs layer which is the buffer layer. It becomes the actual ground (GND) plane. For example, when the specific resistance of the silicon substrate is 40 Ω · cm, the place where the silicon substrate is about 1.6 μm is the actual ground plane. However, since the electrons donated by the thin n-type layer diffuse and spread near the interface between the GaAs layer and the silicon substrate, the distance between the 2DEG layer and the ground plane is substantially 1.6 μm. It does not increase, and the actual increase is about 1.3 μm. Compared with the case where an n-type silicon substrate is used, the increase in the distance from the 2DEG layer to the ground plane is almost proportional to the square root of the specific resistance of the silicon substrate, and the specific resistance of the silicon substrate is considered to be at the limit. 18 μm at 10,000 Ω · cm
The distance from the 2DEG layer to the ground plane increases. Generally, a commercially available silicon substrate has a diameter of 3 inches and a thickness of 400 μm, and a diameter of 4 to 6 inches has a thickness of 625 μm. There is no problem even if it becomes.

As described above, when the conductivity type of the silicon substrate is p-type, the ground plane of the silicon substrate and the buffer layer G
Since it enters from the interface of the aAs layer, the distance between the 2DEG layer and the ground plane increases accordingly, and the capacitance component and the inductance component of the 2DEG layer are different from those when an n-type silicon substrate is used. Therefore, the conductivity type of the silicon substrate used is p.
In the case of a mold, it is necessary to find the increase in the distance between the 2DEG layer and the actual ground plane from the value of the specific resistance to find the capacitance component and the inductance component of the 2DEG layer. Specifically, since GaAs and silicon have almost the same relative permittivity value, the capacitance component Cs increases substantially in inverse proportion to the distance between the 2DEG layer and the ground plane. Incidentally, the product of the values of Cs and Ls is almost constant regardless of the distance between the 2DEG layer and the ground plane.

Sheet resistance ρs of the 2DEG layer of the first embodiment
Is about 1 kΩ / □, the sheet inductance Ls is about 4.9 pH / □, and the capacitance Cs per square area of 10 μm is about 3.2 fF. As the characteristics of the formed transmission line 20 of the 2DEG layer, the length x and the width w of the transmission line 20 are arbitrarily patterned, and thus ρs, Ls, and Cs are given in the above equations (1) to (4). Is the value obtained by substituting. From the values of these Rs, Ls, and Cs and the equation (4), this transmission line 20 is approximately 30 THz (3 × 1).
It is understood that a CR line can be considered below 0 ¹³ Hz), and the characteristic impedance in this case is expressed by the following equation (5).

[0040]

[Equation 5]

Therefore, when impedance matching is performed, the width of the transmission line 20 is determined by equation (5) so that a desired characteristic impedance can be obtained. When functioning as a low pass filter or a delay element, the length of the transmission line 20 is determined so that the product of the resistance component and the capacitance component of the entire transmission line 20 has a desired time constant or delay time.

The impurity concentration and thickness of each layer of the compound semiconductor may be appropriately changed according to the conductivity type and the specific resistance of the silicon substrate as described above to obtain desired device characteristics. For example, high purity i -It is preferable that the impurity concentration of the GaAs layer 13 is low, and at most 1 × 10 ¹⁶ atoms cm
^-3 or less is preferable, and if possible, 1 × 10 ¹⁵ atoms cm ^-3 or less is more preferable. The thickness is preferably about 500 to 1000Å. Although the impurity concentration of the n-AlGaAs layer 14 varies depending on desired characteristics (particularly sheet resistance), it is approximately 1 × 10 ¹⁷ atoms cm ⁻³ to 1 × 10 ¹⁹ atoms.
The number of atoms is about cm ⁻³ , and the thickness varies depending on the desired characteristics, but it is preferably about 100 Å to 1000 Å, more preferably about 300 Å to 500 Å. Further, the n-GaAs layer that is the cap layer 15 preferably has a high impurity concentration, and 1 × 10 ¹⁸ atoms cm ^-3.
The thickness is preferably not less than about 500, not too thin or too thick.
It is preferably about 2000 Å. The thickness of the buffer layer 12 affects the characteristics of the capacitance component and may be changed according to the desired characteristics. However, the thickness of the buffer layer 12 is too thin because it affects the crystallinity of each compound semiconductor layer formed thereon. This is not preferable, and the thickness is preferably about 1 μm or more. Also, in terms of crystallinity, this buffer layer 1
The thicker the number 2, the better. However, since the internal stress acts on the GaAs layer crystal-grown on the silicon substrate, it cannot be made too thick, and the limit is about 4 μm. Therefore, the buffer layer 12, the i-GaAs layer 13, the n-AlGaAs layer 1
4. The thickness of the buffer layer 12 is determined so that the sum of the thicknesses of the n-GaAs layers 15 does not exceed 4 μm.

Next, a method of manufacturing the element of the first embodiment will be described. First, a non-doped GaAs layer to be the buffer layer 12 and a non-doped i-GaAs layer 13 of extremely high purity are sequentially epitaxially grown on the silicon substrate 11 by a vapor phase growth method, and then Si as an impurity is grown.
N-Al while introducing SiH ₄ and Si ₂ H ₆ as the source
The GaAs layer 14 is epitaxially grown, and then the n-GaAs layer is epitaxially grown while introducing SiH ₄ and Si ₂ H ₆ as the cap layer 15 in the same manner.

After that, a mask material is formed by photolithography so that a portion to be the transmission line 20 is left, and mesa etching is performed, so that an unnecessary portion of the transmission line 20 is i-
The GaAs layer 13, the n-AlGaAs layer 14 and the cap layer 15 are removed. The etching solution for this mesa etching is, for example, a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution, a mixed solution of hydrofluoric acid / water / hydrogen peroxide solution, a mixed solution of sulfuric acid / water / hydrogen peroxide solution, or Use a mixture of phosphoric acid, water and hydrogen peroxide.

Next, after AuGe / Ni / Au is vapor-deposited and lifted off, alloying heat treatment (for example, 450 ° C.) is performed to form electrodes 18 and 19. At this time, the ohmic diffusion layer 17 reaching the 2DEG layer under each electrode
Can be done naturally.

Although the n-type silicon substrate is used in the first embodiment, it is not limited to this.
A p-type silicon substrate may be used in consideration of the influence of the silicon substrate according to desired device characteristics.

Second Embodiment A second embodiment to which the present invention is applied is the same as the above-mentioned first embodiment except that an unnecessary portion of nA is required to form the transmission line 20.
In contrast to the case where 1 GaAs was removed by mesa etching, an electrode for element isolation was provided around this transmission line 20 to deplete the 2DEG layer under the electrode, and
And a peripheral portion are separated into elements to function as an impedance line, a filter element and a delay element. 2A and 2B are drawings for explaining the device structure of the second embodiment, FIG. 2A is a plan view thereof, FIG. 2B is a sectional view taken along line AA in FIG. 2A, and FIG. It is sectional drawing in the BB line.

In the second embodiment, a p-type silicon substrate 11 having a specific resistance of 30 Ω · cm is used as a conductive substrate, and non-doped GaAs is formed on the silicon substrate 11.
Buffer layer 12 having a high resistance and a non-doped high-purity i-GaAs layer 1 which is a first compound semiconductor layer thereon
3 and S which becomes the electron donating layer in the second compound semiconductor layer
Thickness of 2 × 10 ¹⁸ atoms cm ^-3 doped with 1000 Å
The n-AlGaAs layer 14 is laminated to form a 2DEG layer. After forming the cap layer 15 of the doped n-GaAs layer on the n-AlGaAs layer 14, the electrode 1 is formed.
8 and 19 are made of AuGe / Ni / Au,
Further, the element isolation electrode 2 is provided around the portion to be the transmission line 20.
5 is formed, and a voltage of 0 V or less is applied to the element isolation electrode 25 with the lowest voltage as a reference, thereby depleting the 2DEG layer below the element isolation electrode 25, and the transmission line 2
0 and the peripheral part are separated. The distance from the surface of the silicon substrate 11 to the 2DEG layer is about 3.8 μm as in Example 1, but a p-type silicon substrate is used and the specific resistance is 30 Ω · cm.
So the actual distance from the 2DEG layer to the ground plane is
It is about 4.7 μm.

This allows the electrodes 18 and 19 and the 2DEG to
It is formed by the layer transmission line 20, and becomes an impedance line, a filter element and a delay element as in the first embodiment.

In the second embodiment, the p-type silicon substrate is used, and the influence of this on the characteristics of the 2DEG layer is as described in detail in the first embodiment. Therefore, the substantial distance from the 2DEG layer to the ground plane is about 4.7 μm as described above. The sheet resistance ρs of the 2DEG layer in the second embodiment is about 250Ω.
/ □, the sheet inductance Ls is about 6.3 pH
/ □, and the capacitance Cs per square area of 10 μm is about 2.6 fF. The formed 2DEG layer transmission line 20
As for the characteristic of, the length x of the transmission line 20 is the same as in the first embodiment.
The desired characteristics can be obtained by arbitrarily patterning the width w.

Although the p-type silicon substrate is used in the second embodiment, an n-type silicon substrate may be used depending on desired device characteristics. In that case, the distance between the 2DEG layer and the ground plane is about 0.1 μm shorter than the distance to the interface between the silicon substrate surface and the GaAs layer which is the buffer layer.

Further, the device characteristics can be changed by changing the impurity concentration and the thickness of each layer of the compound semiconductor layer as in the first embodiment, and the high-purity i-GaAs layer 13 is 1 × 1.
It is preferably 0 ¹⁶ atoms / cm ^-3 or less, more preferably 1 × 10 ¹⁵ atoms / cm ^-3 or less, and the thickness is preferably about 500 to 1000Å. The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10 ¹⁷ atoms cm ⁻³ to 1 × 10 ¹⁹ atoms c.
m ^-3 , the thickness is about 100 ~ 1000Å,
More preferably, it is about 300 to 500Å. In addition, the impurity concentration of the n-GaAs layer serving as the cap layer 15 is 1 ×
10 ¹⁸ atoms cm ^-3 or more is preferable, and the thickness is 500
It is preferably about 2000 Å. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, GaAs crystal-grown on a silicon substrate
Since internal stress acts on the layer, it cannot be made too thick, and the limit is about 4 μm. Therefore, the buffer layer 12, i-G
aAs layer 13, n-AlGaAs layer 14, n-GaAs
The thickness of the buffer layer 12 is determined so that the total thickness of the layers 15 does not exceed 4 μm.

A method of manufacturing the device of the second embodiment will be described. First, as in Example 1, on the silicon substrate 11,
A non-doped GaAs layer to be the buffer layer 12 and a non-doped high-purity i-GaAs layer 13 are epitaxially grown by a vapor phase growth method to form Si as an impurity Si source.
N-AlGaAs layer 1 while introducing H ₄ and Si ₂ H ₆
4 is epitaxially grown, and then the cap layer 15
Similarly, while introducing SiH ₄ and Si ₂ H ₆ , an n-GaAs layer is epitaxially grown as described above.

Then, AuGe / Ni / Au is vapor-deposited and lift-off is performed, and then alloying heat treatment (for example, 450 ° C.) is performed to form electrodes 18 and 19, and at this time,
An ohmic diffusion layer 17 reaching the 2DEG layer is naturally formed under each electrode.

Next, the element isolation electrode 25 is formed by vapor deposition of the element isolation electrode material and lift-off. The element isolation electrode may be formed by removing the cap layer 15.

Third Embodiment A third embodiment to which the present invention is applied is the same as the above-described first embodiment except that the i-G of an unnecessary portion is formed to form the transmission line 20.
While the aAs layer 13 and the n-AlGaAs layer 14 are formed by removing them by mesa etching, and the transmission line 20 is formed by providing the element isolation electrode in the second embodiment, the periphery of the transmission line 20 is formed. I-GaAs layer 1
Ion implantation into the 3 and n-AlGaAs layer 14 portions so as to eliminate its crystallinity and eliminate the semiconductor properties.
Specifically, by implanting oxygen (O) ions, the 2DEG layer in the portion other than the transmission line 20 is eliminated, and the transmission line 20 is formed to function as an impedance line, a filter element, and a delay element. The structure of other parts is the same as that of the first embodiment.

FIG. 3 is a drawing for explaining the device structure of the third embodiment, FIG. 3a is its plan view, and FIG. 3b is FIG.
3a is a cross-sectional view taken along the line AA in FIG.
4 is a cross-sectional view taken along line BB in FIG.

In Example 3, the laminated structure of the compound semiconductor is the same as in Examples 1 and 2 described above, but the conductive substrate is an n-type and has a specific resistance of 1000 Ω · cm.
The high-resistance buffer layer 12 made of a non-doped GaAs layer, the non-doped high-purity i-GaAs layer 13 as the first compound semiconductor layer, and the second 1.5 × 10 ¹⁸ atoms of Si serving as an electron donating layer in the compound semiconductor layer of c
m ⁻³ doped n-AlGaAs layer 14 having a thickness of 300 Å
Are stacked to form a 2DEG layer, and oxygen ions are implanted into unnecessary portions 21 other than the transmission line 20 to form unnecessary portions 2
1 i-GaAs layer 13 and n-AlGaAs layer 14
Of the semiconductor, the cap layer 15 of the doped n-GaAs layer is formed on the n-AlGaAs layer 14, and then the electrodes 18 and 19 are formed of AuGe / Ni / Au. The distance from the surface of the silicon substrate 11 to the 2DEG layer is about 3.9 μm, and since the n-type silicon substrate is used in the third embodiment, the substantial distance between the 2DEG layer and the ground plane is about. 3.8μ
m. This is as described in Example 1, and there is no effect due to the specific resistance of the silicon substrate.

This allows the electrodes 18 and 19 and the 2DEG to
The element formed by the layer transmission line 20 functions as an impedance line, a filter element and a delay element as in the first and second embodiments. The sheet resistance ρs of the 2DEG layer in the third embodiment is about 2.
2 kΩ / □, and the sheet inductance Ls is about 5.
1 pH / □, capacity Cs per square area of 10 μm
Is about 3.2 fF. The characteristics of the formed transmission line 20 of the 2DEG layer can be set to desired characteristics by arbitrarily patterning the length x and the width w of the transmission line 20, as in the first embodiment.

In the third embodiment as well, a p-type silicon substrate may be used in consideration of the effect of the silicon substrate, as described in the first embodiment, depending on the desired device characteristics. Further, the device characteristics can be changed by changing the impurity concentration and the thickness of each layer of the compound semiconductor layer in the same manner as in Example 1, and the high-purity i-GaAs layer 13 is 1 × 1.
It is preferably 0 ¹⁶ atoms / cm ^-3 or less, more preferably 1 × 10 ¹⁵ atoms / cm ^-3 or less, and the thickness is preferably about 500 to 1000Å. The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10 ¹⁷ atoms cm ⁻³ to 1 × 10 ¹⁹ atoms c.
m ^-3 , the thickness is about 100 ~ 1000Å,
More preferably, it is about 300 to 500Å. In addition, the impurity concentration of the n-GaAs layer serving as the cap layer 15 is 1 ×
10 ¹⁸ atoms cm ^-3 or more is preferable, and the thickness is 500
It is preferably about 2000 Å. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, GaAs crystal-grown on a silicon substrate
Since internal stress acts on the layer, it cannot be made too thick, and the limit is about 4 μm. Therefore, the buffer layer 12, i-G
aAs layer 13, n-AlGaAs layer 14, n-GaAs
The thickness of the buffer layer 12 is determined so that the total thickness of the layers 15 does not exceed 4 μm.

A method of manufacturing the device of Example 3 will be described. First, as in the first embodiment, on the silicon 11,
A non-doped GaAs layer to be the buffer layer 12 and a non-doped high-purity i-GaAs layer 13 are epitaxially grown by a vapor phase growth method to form Si as an impurity Si source.
N-AlGaAs layer 1 while introducing H ₄ and Si ₂ H ₆
4 is epitaxially grown, and then a mask material is formed on the portion to be the transmission line 20 by photolithography, and oxygen ions are implanted into the unnecessary portion 21. The dose of oxygen ion implantation is about 1 × 10 ¹⁷ atoms cm ^−2. The above is preferably 1 × 10 ¹⁸ atoms cm ⁻² or more, and the accelerating voltage is appropriately selected so as to reach the inside of the i-GaAs layer 13 depending on the thickness of each layer. Thereby, the n-AlGaAs layer 14 and the i-Ga in the region where the oxygen ions are implanted are formed.
The As layer 13 no longer exhibits semiconductor characteristics, and the 2DEG layer 16 cannot exist in this region.

Then, while introducing SiH ₄ or Si ₂ H ₆ as the cap layer 15, an n-GaAs layer is epitaxially grown in the same manner as described above. Then AuGe / Ni /
After Au deposition and lift-off, alloying heat treatment (for example, 4
By carrying out 50 ° C.), the electrodes 18 and 19 are formed, and at this time, the ohmic diffusion layer 17 reaching the 2DEG layer is naturally formed under each electrode.

Example 4 In Example 4 to which the present invention is applied, a control electrode 26 is provided on the transmission line 20 formed according to Example 1, Example 2 or Example 3 described above, and FIG. A plan view of the fourth embodiment, FIG. 4b is a sectional view taken along line AA in FIG. 4a, and FIG. 4c is a sectional view taken along line BB in FIG. 4a.

By applying a voltage to the control electrode 26 on the transmission line 20, the potential in the 2DEG layer which is the transmission line 20 changes, and the sheet resistance ρs of the 2DEG layer is changed.
Is changed, and the resistance value R of the transmission line 20 can be changed arbitrarily. Although the configuration other than the control electrode is the same as that of the first embodiment in the illustrated case, the configuration other than the control electrode may be the configuration of the second or third embodiment. The conductivity type and the specific resistance of the silicon substrate used are as described in Example 1, and may be n-type or p-type. Further, the impurity concentration and thickness of each layer of the compound semiconductor can be changed according to desired element characteristics as in the case of the first, second and third embodiments. Good to choose.

As described above, the fourth embodiment can be used as a variable impedance matching circuit, and when it is used as a filter element, its time constant τ (τ = C).
R) (or the cutoff frequency) can be changed, and when the delay element is used, its delay time can also be changed, resulting in a delay element having a variable delay time.
That is, when it is desired to reduce the sheet resistance ρs, if a high voltage of, for example, about 0.1 to 2 V is applied to the control electrode 26 with reference to the lower potential of the electrode 18 or the electrode 19, the 2DEG layer is formed. The sheet resistance decreases and the resistance value R decreases. In addition, when it is desired to increase the resistance value R, when a low voltage of about −0.1 to −2 V is applied to the control electrode 26 with reference to the lower potential of the electrodes 18 or 19, the 2DEG layer is formed. Sheet resistance increases.

The manufacturing method of the element of the fourth embodiment is similar to the first embodiment, the second embodiment or the third embodiment. First, on the silicon substrate 11 which is a conductive substrate, a non-doped GaAs layer to be the buffer layer 12, Non-doped high-purity i-GaAs
The layer 13 is epitaxially grown by the vapor phase growth method, and the n-AlGaAs layer 14 is epitaxially grown while introducing SiH ₄ and Si ₂ H ₆ which are Si sources as impurities. Here, when forming the transmission line 20 by oxygen ion implantation, oxygen ion implantation is performed as in the third embodiment. Then, while introducing SiH ₄ or Si ₂ H _{6 serving} as a Si source as an impurity as the cap layer 15, n-
Epitaxially grow the GaAs layer.

Then, the transmission line 20 is subjected to mesa etching.
In this case, the mesa etching is performed as in the first embodiment to remove unnecessary portions of the i-GaAs layer 13, the n-AlGaAs layer 14, and the cap layer 15. (In the drawing, the unnecessary portion is removed by this mesa etching.) Next, after AuGe / Ni / Au is vapor-deposited and lifted off, alloying heat treatment (for example, 450 ° C.) is performed. As a result, electrodes 18 and 19 are formed, and at this time, 2DE is formed under each electrode.
The ohmic diffusion layer 17 reaching the G layer can be formed naturally.

Next, in order to provide the control electrode 26, sulfuric acid.
N-Ga of the cap layer 15 at the place where the control electrode 26 is formed by etching using a mixed liquid of water and hydrogen peroxide
The As layer is selectively removed by etching. After that, the control electrode 26 is formed by vapor deposition of electrode material and lift-off.
The transmission line 20 is connected to the element isolation electrode 25 as in the second embodiment.
In this case, since the element isolation electrode 25 can be formed simultaneously with the formation of the control electrode 26, it is not necessary to separately form the control electrode 25 and the element isolation electrode 26.

The etching of the n-GaAs layer is performed by using a mixed solution of phosphoric acid / water / hydrogen peroxide solution, a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution, or a reaction with CCl ₂ F ₂ gas. It can also be carried out by means of a characteristic ion etching or the like.

Embodiment 5 Embodiment 5 is an embodiment of a semiconductor device to which the present invention is applied. In this semiconductor device, two two-dimensional electron gas field effect transistors are adjacent to each other, and the above-described semiconductor element transmission line is used as an inter-element wiring path for connecting the two two-dimensional electron gas field effect transistors. Is.
5a is a plan view thereof, FIG. 5b is a sectional view taken along line AA in FIG. 5a, and FIG. 5c is a sectional view taken along line BB in FIG. 5a. The formed field effect transistor (FET) is an E-FET (enhancement type F
ET), one source electrode of the two FETs and the drain electrode of the other FET are electrically connected.

In the fifth embodiment, the two-dimensional electron gas field effect transistor portions 1 and 2 are made of a non-doped GaAs layer having a high resistance on a p-type silicon substrate 11 which is a conductive substrate and has a specific resistance of 3000 Ω · cm. Buffer layer 12, a non-doped high-purity i-GaAs layer 13 which is the first compound semiconductor layer, and 5 × 10 ¹⁷ Si as an impurity which becomes the electron donating layer in the second compound semiconductor layer.
N-AlGaA with a thickness of 100 Å doped with atoms cm ^-3
The s layer 14 is laminated, and the i-GaAs layer 13 and n-Al are laminated.
The 2DEG layer 16 is formed at the heterojunction interface with the GaAs layer 14, and the distance between the surface of the silicon substrate 11 and the 2DEG layer is about 3.9 μm, but the silicon substrate is p-type and the specific resistance is 3000 Ω · cm. Therefore, the substantial distance between the 2DEG layer and the ground plane is about 13.5 μm. Further n-A
After forming a cap layer 15 of a doped n-GaAs layer on the 1GaAs layer 14, the source electrodes 1S, 2S,
The drain electrodes 1D and 2D and the gate electrodes 1G and 2G are formed. The source electrodes 1S and 2S and the drain electrodes 1D and 2D are made of AuGe / Ni / Au, and an ohmic diffusion layer 17 made of an electrode metal reaching the 2DEG layer 16 is formed thereunder.

In the fifth embodiment, only the 2DEG layer is left as the transmission line 20 for electrically connecting the sources and drains of the two E-FETs, and the i-G of the portion unnecessary for the connection is left.
The aAs layer 13 and the n-AlGaAs layer 14 were removed by etching.

As a result, the drain 1D and the source 2S of the adjacent E-FETs are electrically connected by the transmission line 20 of the 2DEG layer, and this transmission line 20 portion is connected to the impedance line, the delay element or the delay line as in the first embodiment. It can function as a low-pass filter element.

The characteristics of the 2DEG layer formed in this Example 5 are that the sheet resistance ρs is about 10 kΩ / □ and the sheet inductance Ls is about 18 pH / □.
The capacitance Cs per square area of μm is about 0.89 fF. The characteristics of the transmission line 20 are the same as those of the first embodiment described above, and are obtained by the above equations (1) to (4) and (5).

The characteristics of the 2DEG layer may vary depending on the conductivity type and the specific resistance of the silicon substrate, as in the case of the first embodiment, and the interface between the silicon substrate and the GaAs layer of the buffer layer may be changed. The silicon diffuses into the GaAs layer to form a thin n-type layer with a thickness of about 100 Å. The electron donation from this n-type layer causes the GaAs layer to have a thickness of about 0.1 μm and the silicon substrate side Electron diffusion regions that differ depending on the conductivity type and the specific resistance are formed.
This electron diffusion region acts to shorten the substantial distance between the 2DEG layer and the ground plane.

Therefore, when the conductivity type of the silicon substrate is n-type, the part of the silicon substrate and the GaAs layer of the buffer layer that has entered the GaAs layer by about 0.1 μm is the actual ground (GND) plane, and the silicon substrate The specific resistance itself does not affect the device characteristics.

On the other hand, when the conductivity type of the silicon substrate is p-type, a depletion layer is formed on the silicon substrate, so that a portion slightly entering the inside of the silicon substrate from the interface between the silicon substrate and the GaAs layer which is the buffer layer. It becomes the actual ground (GND) plane. For example, when the specific resistance of the silicon substrate is 40 Ω · cm, the place where the silicon substrate is about 1.6 μm is the actual ground plane. However, since the electrons donated by the thin n-type layer diffuse and spread near the interface between the GaAs layer and the silicon substrate, the distance between the 2DEG layer and the ground plane is substantially 1.6 μm. It does not increase, and the actual increase is about 1.3 μm. Compared with the case where an n-type silicon substrate is used, the increase in the distance from the 2DEG layer to the ground plane is almost proportional to the square root of the specific resistance of the silicon substrate, and the specific resistance of the silicon substrate is considered to be at the limit. 18 μm at 10,000 Ω · cm
The distance from the 2DEG layer to the ground plane increases. Generally, a commercially available silicon substrate has a diameter of 3 inches and a thickness of 400 μm, and a diameter of 4 to 6 inches has a thickness of 625 μm. There is no problem even if it becomes.

As described above, when the conductivity type of the silicon substrate is p-type, the ground plane of the silicon substrate and the G of the buffer layer are G.
Since it enters from the interface of the aAs layer, the distance between the 2DEG layer and the ground plane increases accordingly, and the capacitance component and the inductance component of the 2DEG layer are different from those when an n-type silicon substrate is used. Therefore, the conductivity type of the silicon substrate used is p.
In the case of a mold, it is necessary to find the increase in the distance between the 2DEG layer and the actual ground plane from the value of the specific resistance to find the capacitance component and the inductance component of the 2DEG layer. Specifically, since GaAs and silicon have almost the same relative permittivity value, the capacitance component Cs increases substantially in inverse proportion to the distance between the 2DEG layer and the ground plane. Incidentally, the product of the values of Cs and Ls is almost constant regardless of the distance between the 2DEG layer and the ground plane.

As described above, the characteristics of the 2DEG layer are affected by the conductivity type and the specific resistance of the silicon substrate.
It is necessary to keep in mind when obtaining the characteristics of the 2DEG layer and designing it. However, if this is taken into consideration, the conductivity type and the specific resistance of the silicon substrate should be selected according to the characteristics of the FET to be formed. Then there is no problem.

The impurity concentration and thickness of each layer of the compound semiconductor may be appropriately selected according to the desired characteristics. For example, the high-purity i-GaAs layer 13 is 1 × 10 ¹⁶ atoms / cm ^-3 or less, and more preferably. 1 x 10 ¹⁵ atoms cm ^-3
It is below, and the thickness is preferably about 500 to 1000Å. The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10 ¹⁷ atoms cm ⁻³ to 1 × 10 ¹⁹ atoms cm ⁻³ , and the thickness thereof is approximately 100 to 1000 Å, more preferably 300 to It is about 500Å. The impurity concentration of the n-GaAs layer which will be the cap layer 15 is 1 × 10 ^18.
The number of atoms is preferably cm ^-3 or more, and the thickness is 500 to 20.
About 00Å is preferable. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, since the internal stress acts on the GaAs layer crystal-grown on the silicon substrate, it cannot be made too thick, and the limit is about 4 μm. Therefore, the buffer layer 12, i-GaAs
Layer 13, n-AlGaAs layer 14, n-GaAs layer 15
Of the buffer layer 12 so that the total thickness of the layers does not exceed 4 μm.
Determine the thickness of.

A method of manufacturing the semiconductor device of the fifth embodiment will be described. First, a non-doped GaAs layer to be the buffer layer 12 and a non-doped i-GaAs layer 13 of extremely high purity are sequentially epitaxially grown on the silicon substrate 11 by a vapor phase growth method, and then Si as an impurity is grown.
N-Al while introducing SiH ₄ and Si ₂ H ₆ as the source
The GaAs layer 14 is epitaxially grown, and then the cap layer 15 is replaced by SiH serving as an Si source as an impurity.
_The n-GaAs layer is epitaxially grown while introducing ₄ and Si ₂ H ₆ .

After that, a mask material is formed by photolithography so as to leave a portion to be the element forming region and the transmission line 20, and mesa etching is performed to form the transmission line 20.
I-GaAs layer 13 and n-AlGaAs in unnecessary portions
Layer 14 and cap layer 15 are removed. The etching solution for this mesa etching is, for example, a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution, hydrofluoric acid / water /
Use a mixed solution of hydrogen peroxide water, a mixed solution of sulfuric acid / water / hydrogen peroxide solution or a mixed solution of phosphoric acid / water / hydrogen peroxide solution.

Next, after depositing AuGe / Ni / Au and lifting off, an alloying heat treatment (for example, 450 ° C.) is performed to form the source electrodes 1S, 2S and the drain electrodes 1D, 2D. At this time, 2DEG under each electrode
The ohmic diffusion layer 17 reaching the layer 16 is naturally formed.

Next, the n-GaAs layer of the cap layer 15 at the place where the gate electrode is formed is selectively removed by etching using a mixed solution of sulfuric acid / water / hydrogen peroxide solution. After that, the gate electrodes 1G and 2G are formed by vapor deposition and lift-off of the gate electrode material.

The etching of the n-GaAs layer is not limited to etching with a mixed solution of sulfuric acid / water / hydrogen peroxide solution, but may be performed with a mixed solution of phosphoric acid / water / hydrogen peroxide solution or ammonia / sodium hydroxide / water. Etching with a mixed solution of hydrogen peroxide solution or reactive ion etching with CCl ₂ F ₂ gas can also be performed.

Although the n-type silicon substrate is used in the fifth embodiment, the present invention is not limited to this.
A p-type silicon substrate may be used in consideration of the influence of the silicon substrate according to desired device characteristics.

Example 6 In the semiconductor device of Example 6 to which the present invention is applied, the transmission line 20 for connecting two two-dimensional electron gas layer field effect transistors is formed as in Example 2 described above. The semiconductor device is made by using the separation electrode 25, and the other structure is the same as that of the fifth embodiment.

6A and 6B are drawings for explaining a semiconductor device according to the sixth embodiment. FIG. 6A is its plan view and FIG. 6B is FIG. 6A.
6C is a cross-sectional view taken along line AA in FIG. 6C, and FIG. 6C is a cross-sectional view taken along line BB in FIG. 6A. The formed FET is an E-FET like the fifth embodiment, and two FETs are formed.
One of the source electrodes and the drain electrode of the other FET are electrically connected.

In the sixth embodiment, the two-dimensional electron gas field effect transistor portions 1 and 2 have a high resistance due to a non-doped GaAs layer on a silicon substrate 11 which is an n-type conductive substrate and has a specific resistance of 8000 Ω · cm. Buffer layer 12, a non-doped high-purity i-GaAs layer 13 which is the first compound semiconductor layer, and Si as an impurity which becomes an electron donor layer in the second compound semiconductor layer 1 × 10 ¹⁸
N-AlGaA with a thickness of 400 Å doped with atoms cm ^-3
The s layer 14 is laminated, and the i-GaAs layer 13 and n-Al are laminated.
The 2DEG layer 16 is formed at the heterojunction interface with the GaAs layer 14. The distance between the 2DEG layer 16 and the surface of the silicon substrate 11 is about 3.8 μm. Since the n-type silicon substrate is used, the substantial distance between the 2DEG layer and the ground plane is about 3.7 μm. Then, the n-AlGaAs layer 14
On top of the cap layer 1 with a doped n-GaAs layer
After forming 5, the source electrodes 1S and 2S, the drain electrode 1
D, 2D and gate electrodes 1G, 2G are formed. Source electrodes 1S, 2S and drain electrodes 1D,
2D is formed of AuGe / Ni / Au, and an ohmic diffusion layer 17 made of an electrode metal reaching the 2DEG layer is formed thereunder.

In the sixth embodiment, the transmission line 20 that electrically connects the sources and drains of two E-FETs is used as the transmission line 20.
In order to leave only the DEG layer, the transmission line 20 and a portion of the 2DEG layer which is not necessary for connection are separated, an electrode 25 is provided around the transmission line 20 for element isolation, and the element isolation electrode 25 is provided with an FET. By applying a voltage of 0 V or less with reference to the lowest voltage among the voltages supplied to the 2DEG layer, the 2DEG layer under the element isolation electrode 25 is depleted, and the transmission line 20 and the peripheral portion are separated. . In addition, in order to apply a potential of 0 V or less, the element isolation electrode 25 is coupled to a wiring supplying the lowest voltage, or if there is another power source of 0 V or less, wiring is performed with the power source. Well, it is not necessary to provide a power source for element isolation.

As a result, similarly to the fifth embodiment, the drain 1D and the source 2S of the adjacent E-FETs are electrically connected by the transmission line 20 of the 2DEG layer, and this transmission line 20 portion is an impedance line and a delay element. Alternatively, it functions as a low-pass filter element.

The characteristic of the 2DEG layer of the sixth embodiment is that the sheet resistance ρs is about 1.3 kΩ / □, the sheet inductance Ls is about 4.9 pH / □, and the capacitance Cs per square area of 10 μm is about. It is 3.2 fF. The characteristic of the transmission line 20 is the same as that of the above-described first embodiment, and the above-mentioned (1)
˜ (4) and (5).

The conductivity type and the specific resistance of the silicon substrate are not limited to the n-type substrate, and as described in the fifth embodiment, the FETs formed simultaneously while taking into consideration the influence of the conductivity type and the specific resistance of the silicon substrate. The p-type substrate can be used by appropriately selecting it according to the desired characteristics of the compound semiconductor, and the impurity concentration and thickness of each layer of the compound semiconductor may be selected according to the desired characteristics, for example, a high-purity i-GaAs layer. Thirteen
Is 1 × 10 ¹⁶ atoms cm ^-3 or less, more preferably 1 × 1
0 ¹⁵ atoms cm ^-3 or less, and a thickness of 500 to 1000
Å is preferable. The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10 ¹⁷ atoms cm ⁻³ to 1 × 10 ^19.
The number of atoms is about cm ⁻³ , and the thickness is about 100 to 1000.
It is about Å, more preferably about 300 to 500 Å.
The impurity concentration of the n-GaAs layer serving as the cap layer 15 is preferably about 1 × 10 ¹⁸ atoms cm ⁻³ or more, and the thickness is preferably about 500 to 2000 Å. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, G grown on the silicon substrate
Since internal stress acts on the aAs layer, it cannot be made too thick.
The limit is about μm. Therefore, the buffer layer 12,
i-GaAs layer 13, n-AlGaAs layer 14, n-G
The thickness of the buffer layer 12 is determined so that the total thickness of the aAs layer 15 does not exceed 4 μm.

A method of manufacturing the semiconductor device of the sixth embodiment will be described. First, a non-doped GaAs layer to be the buffer layer 12 and a non-doped high-purity i-GaAs layer 13 are epitaxially grown on the silicon substrate 11 by a vapor phase epitaxy method, and SiH ₄ and S serving as Si sources as impurities are grown.
The n-AlGaAs layer 14 is epitaxially grown while introducing i ₂ H ₆ , and then the n-GaAs layer is epitaxially grown in the same manner as described above while introducing SiH ₄ or Si ₂ H _{6 serving} as an Si source as an impurity as the cap layer 15. Let

Next, after AuGe / Ni / Au is vapor-deposited and lifted off, alloying heat treatment (for example, 450 ° C.) is performed to form the source electrodes 1S and 2S and the drain electrodes 1D and 2D. At this time, 2DEG under each electrode
The ohmic diffusion layer 17 reaching the layer 16 is naturally formed.

Next, the gate electrode and the element separation electrode 2 are etched by etching with a mixed solution of sulfuric acid, water and hydrogen peroxide.
The n-GaAs layer of the cap layer 15 where 5 is formed is selectively removed by etching. After that, the gate electrodes 1G and 2G and the element isolation electrode 25 are formed by vapor deposition and lift-off of the gate electrode material.

Incidentally, the etching of the n-GaAs layer is carried out in the same manner as in Example 5 by etching with a mixed solution of phosphoric acid / water / hydrogen peroxide solution or a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution. It can also be performed by reactive ion etching with CCl ₂ F ₂ gas.

Example 7 In the semiconductor device of Example 7 to which the present invention is applied, the formation of the transmission line 20 for connecting the two two-dimensional electron gas field effect transistors is unnecessary as in Example 3 described above. This is a semiconductor device in which oxygen ions are implanted into the semiconductor device, and the other structures are the same as those in the fifth embodiment.

7A and 7B are drawings for explaining a semiconductor device according to the seventh embodiment. FIG. 7A is its plan view and FIG. 7B is FIG. 7A.
7A is a cross-sectional view taken along line AA in FIG. 7C, and FIG. 7C is a cross-sectional view taken along line BB in FIG. 7A. The formed FET is an E-FET like the fifth embodiment, and two FETs are formed.
One of the source electrodes and the drain electrode of the other FET are electrically connected.

In the seventh embodiment, the two-dimensional electron gas field effect transistor portions 1 and 2 are formed on a p-type silicon substrate 11 having a specific resistance of 300 Ω · cm, which is a conductive substrate.
High-resistance buffer layer 1 made of non-doped GaAs layer 1
2, a non-doped high-purity i-GaAs layer 13 that is the first compound semiconductor layer, and Si as an impurity that serves as an electron donor layer in the second compound semiconductor layer, 9.5 × 10 5.
^17- atom cm ^-3 doped n-AlGa 700 Å thick
The As layer 14 is laminated, and the i-GaAs layer 13 and the n-A layer are stacked.
The 2DEG layer 16 is formed at the heterojunction interface with the 1GaAs layer 14.
To form. The 2DEG layer 16 and the silicon substrate 11
The distance from the surface is about 3.8 μm. Since the silicon substrate is p-type and has a specific resistance of 300 Ω · cm, the substantial distance between the 2DEG layer and the ground plane is about 7.1 μm.

Then, oxygen ions are implanted into the unnecessary portion 21 of the i-GaAs layer 13 and the n-AlGaAs layer 14 other than the transmission line 20, and on the n-AlGaAs layer 14,
After forming the cap layer 15 of the doped n-GaAs layer, the source electrodes 1S and 2S, the drain electrodes 1D and 2D, and the gate electrodes 1G and 2G are formed. The source electrodes 1S and 2S and the drain electrodes 1D and 2D are A
Formed by uGe / Ni / Au with 2DE underneath
An ohmic diffusion layer 17 is formed by the electrode metal that reaches the G layer 16.

As a result, like the fifth and sixth embodiments, the drain 1D and the source 2S of the adjacent D-FETs are formed.
Are electrically connected by the transmission line 20 of the 2DEG layer, and this transmission line 20 portion functions as an impedance line, a delay element or a low pass filter element.

The characteristics of the 2DEG layer formed in Example 7 are that the sheet resistance ρs is about 750 Ω / □, the sheet inductance Ls is about 9.5 pH / □, and
The capacitance Cs per square area of 0 μm is about 1.7 fF. The characteristics of the transmission line 20 are similar to those of the first embodiment described above.
It is obtained by the above equations (1) to (4) and equation (5).

The conductivity type and the specific resistance of the silicon substrate are not limited to the p-type substrate also in the seventh embodiment, and as described in the fifth embodiment, the influence of the conductivity type and the specific resistance of the silicon substrate is taken into consideration. The n-type substrate can be used by appropriately selecting it according to the desired characteristics of the FETs formed at the same time, and the impurity concentration and thickness of each layer of the compound semiconductor can be adjusted to a desired value, for example, high. Purity i-G
The aAs layer 13 is 1 × 10 ¹⁶ atoms cm ⁻³ or less, more preferably 1 × 10 ¹⁵ atoms cm ⁻³ or less, and has a thickness of 50.
About 0 to 1000Å is preferable. In addition, n-AlGaA
The impurity concentration of the s layer 14 is about 1 × 10 ¹⁷ atoms cm ^-3.
~ 1 × 10 ¹⁹ atoms cm ^-3 , thickness is about 10
0 to 1000Å, more preferably 300 to 500Å
It is a degree. In addition, n-GaAs that becomes the cap layer 15
The impurity concentration of the layer is preferably about 1 × 10 ¹⁸ atoms cm ⁻³ or more, and the thickness is preferably about 500 to 2000 Å. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, since the internal stress acts on the GaAs layer crystal-grown on the silicon substrate, it cannot be made too thick, and the limit is about 4 μm. Therefore, the thickness of the buffer layer 12 is determined so that the sum of the thicknesses of the buffer layer 12, the i-GaAs layer 13, the n-AlGaAs layer 14, and the n-GaAs layer 15 does not exceed 4 μm.

A method of manufacturing the semiconductor device of the seventh embodiment will be described. First, a non-doped GaAs layer to be the buffer layer 12 and a non-doped high-purity i-GaAs layer 13 are epitaxially grown on the silicon substrate 11 by a vapor phase epitaxy method, and SiH ₄ and S serving as Si sources as impurities are grown.
The n-AlGaAs layer 14 is epitaxially grown while introducing i ₂ H ₆ , and a mask material is formed on the portion to be the transmission line 20 by photolithography, and n-AlGaA is formed.
Oxygen ion implantation is performed on an unnecessary portion of the s layer 14. The dose of oxygen ion implantation is 1 × 10 ¹⁷ atoms cm ⁻² or more, preferably 1 × 10 ¹⁸ atoms cm ⁻² or more.

Then, as the cap layer 15, an n-GaAs layer is epitaxially grown in the same manner as described above while introducing SiH ₄ or Si ₂ H _{6 serving} as an Si source as an impurity.

Next, after AuGe / Ni / Au is vapor-deposited and lifted off, alloying heat treatment (for example, 450 ° C.) is performed to form the source electrodes 1S, 2S and the drain electrodes 1D, 2D. At this time, 2DEG under each electrode
The ohmic diffusion layer 17 reaching the layer 16 is naturally formed.

Next, the n-GaAs layer of the cap layer 15 at the place where the gate electrode is formed is selectively removed by etching using a mixed solution of sulfuric acid / water / hydrogen peroxide solution. After that, the gate electrodes 1G and 2G are formed by vapor deposition and lift-off of the gate electrode material.

Incidentally, the etching of the n-GaAs layer is carried out in the same manner as in Example 5 by etching with a mixed solution of phosphoric acid / water / hydrogen peroxide solution or a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution. It can also be performed by reactive ion etching with CCl ₂ F ₂ gas.

Example 8 The semiconductor device of Example 8 to which the present invention is applied is similar to Example 5, 6, or 7 in that two two-dimensional electron gas layer field effect transistors are connected by a transmission line 20. However, here, one drain electrode of the two E-FETs and the gate electrode of the other E-FET are electrically connected. FIG. 8a is its plan view, FIG.
8b is a sectional view taken along line AA in FIG. 8a, and FIG.
[Fig. 8] is a sectional view taken along line BB in Fig. 8a.

In the eighth embodiment, in the two-dimensional electron gas field effect transistor portions 1 and 2, the silicon substrate used as the conductive substrate is a p-type silicon substrate 11 having a specific resistance of 0.1 Ω · cm. , Undoped GaA
The high-resistance buffer layer 12 formed of the s layer, the non-doped high-purity i-GaAs layer 13 which is the first compound semiconductor layer, and Si (1 ×) as the impurity which becomes the electron donating layer in the second compound semiconductor layer. 10 ¹⁸ atoms pieces cm ^-3 doped n-AlGaAs layer 14 having a thickness of 500Å were stacked, the 2DEG layer 16 is formed on the heterojunction interface between the i-GaAs layer 13 and the n-AlGaAs layer 14. This 2DE
The distance between the G layer and the surface of the silicon substrate 11 is about 3.8 μm. Although a p-type silicon substrate is used, the thickness of the depletion layer in the silicon substrate is less than 0.1 μm, so 2DEG
The substantial distance between the layers and the ground plane is also about 3.8 μm. Further, on the n-AlGaAs layer 14, doped n-G
After forming the cap layer 15 of the aAs layer, the source electrode 1
S, 2S, drain electrodes 1D, 2D and gate electrode 1
G and 2G are formed. Source electrodes 1S, 2S
And the drain electrodes 1D and 2D are AuGe / Ni / A
An ohmic diffusion layer 17 made of u and made of an electrode metal reaching the 2DEG layer 16 is formed thereunder.

The transmission line 20 is formed in the same manner as in the fifth embodiment.
The method of removing the unnecessary portion by mesa etching, the method of providing the element isolation electrode 26 as in the sixth embodiment, or the method of implanting oxygen ions into the unnecessary portion as in the seventh embodiment is used. In the case shown in the figure, the i-GaA of a portion unnecessary for connection is formed by mesa etching.
The case where the s layer 13 and the n-AlGaAs layer 14 are removed by etching is shown.

In the eighth embodiment, the transmission line 20 is further added.
An ohmic electrode 30 for contacting the gate electrode 2G with the gate electrode 2G, and 2D is provided under the ohmic electrode 30.
An ohmic diffusion layer 17 reaching the transmission line 20 is formed by the EG layer.

As a result, the drain 1D and the gate 2G of the adjacent E-FETs are electrically connected by the transmission line 20 of the 2DEG layer, and this transmission line 20 portion is the impedance line and the delay element as in the first embodiment. Alternatively, it can function as a low-pass filter.
The characteristics of the 2DEG layer formed in this Example 8 are that the sheet resistance ρs is about 1.0 kΩ / □, the sheet inductance Ls is about 5.1 pH / □, and the capacitance Cs per square area of 10 μm is about. It is 3.2 fF. Transmission line 2
The characteristics of 0 are the same as those of the above-described first embodiment (1).
˜ (4) and (5).

The conductivity type and the specific resistance of the silicon substrate are
In the eighth embodiment as well, as described in the fifth embodiment, it is possible to make an appropriate selection in accordance with the desired characteristics of the simultaneously formed FET while considering the influence of the conductivity type and the specific resistance of the silicon substrate. , N-type substrate may be used. Also, regarding the impurity concentration and thickness of each compound semiconductor layer,
Depending on the desired characteristics, for example, a high-purity i-GaAs layer 1
3 is 1 × 10 ¹⁶ atoms cm ⁻³ or less, more preferably 1 ×
10 ¹⁵ atoms cm ^-3 or less and a thickness of 500 to 100
About 0Å is preferable. The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10 ¹⁷ atoms / cm ^-3 to 1 × 10.
It is about ¹⁹ atoms cm ^-3 and the thickness is about 100 to 100.
It is about 0Å, more preferably about 300 to 500Å. Further, the impurity concentration of the n-GaAs layer serving as the cap layer 15 is preferably about 1 × 10 ¹⁸ atoms cm ⁻³ or more,
The thickness is preferably about 500 to 2000Å. Also, the thickness of the buffer layer 12 is preferably about 1 μm or more. Also, from the viewpoint of crystallinity, this buffer layer 12
The thicker the better However, since the internal stress acts on the GaAs layer crystal-grown on the silicon substrate, it cannot be made too thick, and the limit is about 4 μm. Therefore, the buffer layer 12, the i-GaAs layer 13, the n-AlGaAs layer 14,
The thickness of the buffer layer 12 is determined so that the total thickness of the n-GaAs layers 15 does not exceed 4 μm.

A method of manufacturing the semiconductor device of the eighth embodiment will be described. First, a non-doped GaAs layer to be the buffer layer 12 and a non-doped high-purity i-GaAs layer 13 are sequentially epitaxially grown on the silicon substrate 11 by a vapor phase growth method to form SiH ₄ as an Si source as an impurity.
Or Si ₂ H ₆ is introduced to epitaxially grow the n-AlGaAs layer 14, and then the n-GaAs layer is epitaxially grown while introducing SiH ₄ or Si ₂ H _{6 serving} as an Si source as an impurity for the cap layer 15.

After that, a mask material is formed by photolithography so as to leave a portion to be the element forming region and the transmission line 20, and mesa etching is performed to form the transmission line 20.
I-GaAs layer 13 and n-AlGaAs in unnecessary portions
Layer 14 and cap layer 15 are removed. The etching solution for this mesa etching is, for example, a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution, hydrofluoric acid / water /
Use a mixed solution of hydrogen peroxide water, a mixed solution of sulfuric acid / water / hydrogen peroxide solution or a mixed solution of phosphoric acid / water / hydrogen peroxide solution.

After that, AuGe / Ni / Au to be the source and drain electrodes and the ohmic electrode 30 is vapor-deposited,
After the lift-off, an alloying heat treatment (for example, 450 ° C.) is performed, so that the source electrodes 1S and 2S and the drain electrode 1 are formed.
D, 2D and ohmic electrodes 30 are formed. At this time, the ohmic diffusion layer 17 reaching the 2DEG layer 16 under each electrode is naturally formed.

Next, similarly to the fifth, sixth and seventh embodiments, the cap layer 1 is formed at the place where the gate electrode is formed by etching using the mixed solution of sulfuric acid / water / hydrogen peroxide solution.
5 is selectively removed by etching, and then the gate electrodes 1G and 2G are formed by vapor deposition of the gate electrode material and lift-off.
To form. When the transmission line 20 is formed by element isolation, the element isolation electrode 25 is formed here together with the formation of the gate electrode.

Ninth Embodiment A semiconductor device according to a ninth embodiment to which the present invention is applied is the semiconductor device according to any of the fifth to eighth embodiments, in which a control electrode is provided on the transmission line 20 and the transmission line 20 is connected to a variable impedance matching circuit. It can be used as a low-pass filter with a variable time constant and a variable delay time delay element.

FIG. 9a is a plan view of the ninth embodiment in which the source and drain of two FETs are connected by a transmission line 20 and a control electrode 26 is provided on this transmission line, and FIG. 9b is shown in FIG. 9a. 9A is a cross-sectional view taken along line AA in FIG. 9C, and FIG. 9C is a cross-sectional view taken along line BB in FIG. 9A. In the illustrated case, the two-dimensional electron gas field effect transistor is an E-FET, and the transmission line 20 is formed in the same manner as in Example 5, but in Example 9, the following will be described. As will be described, only the control electrode is formed on the transmission line 20, and other configurations are the same as those in the fifth to eighth embodiments.
It is possible to form the transmission line 20 by element isolation electrodes or oxygen ion implantation as in the above-described respective embodiments.

In the two-dimensional electron gas field effect transistor parts 1 and 2 of the ninth embodiment, the buffer layer 12 is formed on the n-type silicon substrate 11 having a specific resistance of 0.01 Ω · cm, which is a conductive substrate. On top of that, as the impurity which becomes the electron donating layer in the non-doped high-purity i-GaAs layer 13 which is the first compound semiconductor layer and the second compound semiconductor layer,
By laminating an n-AlGaAs layer 14 having a thickness of 300Å doped with 8 × 10 ¹⁷ atoms cm ^-3 , the i
The 2DEG layer 16 is formed at the heterojunction interface between the -GaAs layer 13 and the n-AlGaAs layer 14. This 2DEG layer 1
The distance between 6 and the surface of the silicon substrate 11 is about 3.9 μm. Since the n-type silicon substrate is used, the substantial distance between the 2DEG layer and the ground plane is about 3.8 μm. Then, on the n-AlGaAs layer 14, doped n-G
After forming the cap layer 15 of the aAs layer, the source electrode 1
S, 2S and drain electrodes 1D, 2D are formed, and gate electrodes 1G, 2G are formed on the cap layer 15. Source electrodes 1S, 2S and drain electrode 1
D and 2D are formed of AuGe / Ni / Au,
An ohmic diffusion layer 17 made of an electrode metal reaching the 2DEG layer 16 is formed thereunder.

Then, as in the fifth embodiment, two E-FETs are used.
2DEG layer which becomes the transmission line 20 for connecting between the source and the drain is left and the other part is removed by mesa etching, and the drain 1D and the source 2S of the adjacent E-FETs are formed by the transmission line 20 by the 2DEG layer. It is electrically connected.

Further, in the ninth embodiment, the control electrode 26 is formed on the n-AlGaAs layer 14 on the transmission line 20 and a voltage is applied to the control electrode 26, whereby the 2DEG layer of the transmission line 20 is formed. It was possible to control the resistance value by changing the sheet resistance of. That is, when it is desired to reduce the resistance value of the transmission line 20, a high voltage of, for example, about 0.1 to 2 V is applied to the control electrode 26 with reference to the lower potential of the drain electrode 1D or the source electrode 1S. The sheet resistance of the 2DEG layer becomes small and the resistance value becomes small. In addition, when it is desired to increase the resistance value, when a low voltage of about −0.1 to −2 V is applied to the control electrode 26 with reference to the lower potential of the drain electrode 1D or the source electrode 1S, the sheet of the 2DEG layer is formed. The resistance increases and the resistance value increases.

By thus changing the sheet resistance ρs of the 2DEG layer, the resistance R of the transmission line 20 can be arbitrarily changed. Therefore, it becomes possible to use the transmission line 20 formed of the 2DEG layer as a variable impedance matching circuit, and also to change the time constant τ (τ = CR) (or cutoff frequency) when used as a filter element. Further, when the delay element is used, the delay time thereof is changed to form a delay element having a variable delay time.

The characteristic of the 2DEG layer formed in this Example 9 is that the sheet resistance ρs is about 2.1 kΩ / □,
The sheet inductance Ls is about 5.1 pH / □,
The capacitance Cs per square area of 10 μm is about 3.2 fF. The characteristics of the transmission line 20 are similar to those of the first embodiment described above.
It is obtained by the above equations (1) to (4) and equation (5).

The conductivity type and the specific resistance of the silicon substrate are
In the ninth embodiment as well, as described in the fifth embodiment, it is possible to make an appropriate selection in accordance with the desired characteristics of the simultaneously formed FET while considering the influence of the conductivity type and the specific resistance of the silicon substrate. , N-type substrate or p
It may be a mold substrate. Also, regarding the impurity concentration and thickness of each compound semiconductor layer, for example, the high-purity i-GaAs layer 13 is 1 × 10 ¹⁶ atoms cm ⁻³ or less, and more preferably 1 × 10 ¹⁵ atoms according to a desired characteristic range. It is preferably cm ^-3 or less, and the thickness is preferably about 500 to 1000Å. Also,
The impurity concentration of the n-AlGaAs layer 14 is approximately 1 × 10.
¹⁷ atoms cm ^-3 to 1 × 10 ¹⁹ atoms cm ^-3 ,
The thickness is about 100 to 1000Å, more preferably 3
It is about 00 to 500Å. Further, the impurity concentration of the n-GaAs layer serving as the cap layer 15 is 1 × 10 ¹⁸ atoms cm
^-3 or more is preferable, and the thickness is preferably 500 to 2000 Å. The thickness of the buffer layer 12 is also 1
It is preferably about μm or more. In terms of crystallinity, the thicker the buffer layer 12, the better. However, since the internal stress acts on the GaAs layer crystal-grown on the silicon substrate, it cannot be made too thick, and the limit is about 4 μm.
Therefore, the buffer layer 12, the i-GaAs layer 13, n
The thickness of the buffer layer 12 is determined so that the sum of the thicknesses of the -AlGaAs layer 14 and the n-GaAs layer 15 does not exceed 4 μm.

Now, a method of manufacturing the semiconductor device as shown in the figure will be described. The E-FET type is a silicon substrate 1 which is a conductive substrate, as in the fifth to eighth embodiments.
1, a non-doped GaAs layer serving as the buffer layer 12,
The undoped high-purity i-GaAs layer 13 is epitaxially grown by a vapor phase growth method, and n-AlGa is introduced while introducing SiH ₄ and Si ₂ H ₆ which are Si sources as impurities.
The As layer 14 is epitaxially grown, and then, as the cap layer 15, SiH _{4 serving} as an Si source as an impurity is formed.
The n-GaAs layer is epitaxially grown in the same manner as described above while introducing Si or H ₂ H ₆ .

Thereafter, a mask material is formed by photolithography so as to leave a portion to be the element forming region and the transmission line 20, and mesa etching is performed to form the transmission line 20.
I-GaAs layer 13 and n-AlGaAs in unnecessary portions
Layer 14 and cap layer 15 are removed. The etching solution for this mesa etching is, for example, a mixed solution of ammonia / sodium hydroxide / hydrogen peroxide solution, hydrofluoric acid / water /
Use a mixed solution of hydrogen peroxide water, a mixed solution of sulfuric acid / water / hydrogen peroxide solution or a mixed solution of phosphoric acid / water / hydrogen peroxide solution.

Next, after AuGe / Ni / Au is vapor-deposited and lift-off, alloying heat treatment (for example, 450 ° C.) is performed to form the source electrodes 1S, 2S and the drain electrodes 1D, 2D. At this time, 2DEG under each electrode
The ohmic diffusion layer 17 reaching the layer 16 can be naturally formed (F
When connecting to the ET gate, the ohmic electrode 30 is simultaneously formed. See Example 8).

Next, n-G of the cap layer 15 at the place where the gate electrode is formed and the place where the control electrode 26 is formed by etching with a mixed solution of sulfuric acid / water / hydrogen peroxide solution.
The aAs layer is selectively removed by etching. After that, the gate electrodes 1G and 2G and the control electrode 26 are formed by vapor deposition and lift-off. Although the control electrode 26 is provided by removing the cap layer 15 in Example 9, it may be provided on the control electrode 26 without removing the cap layer 15.

In Examples 1 to 9 described above, the silicon substrate was used as the conductive substrate. However, other semiconductor substrates such as germanium having a band gap of about 1.3 eV or less, or metal substrates may be used. Further, GaAs is used as the first compound semiconductor layer and AlGaAs is used as the second compound semiconductor layer. However, the present invention is also applicable to other compound semiconductors as shown in Table 1 below. It can be carried out.

[0133]

[Table 1]

In addition to the materials used in Examples 1 to 9, the materials shown in Tables 2 and 3 below can be used as the electrode material, depending on the compatibility with each compound semiconductor and the required device characteristics. It is recommended to select and use it appropriately.

[0135]

[Table 2]

[0136]

[Table 3]

In the fifth to ninth embodiments, the two two-dimensional electron gas field effect transistors are connected by the transmission line of the 2DEG layer, but the two two-dimensional electron gas field effect transistors are not necessarily connected. Of course, more than one element can be connected by a transmission line formed by the 2DEG layer, and the transmission line can function as an impedance line, a filter element, and a delay element as described above. The type of the two-dimensional electron gas field effect transistor is not limited to the E type as described above, and may be the D type (depletion type), or the E type and the D type are mixed. In the case of the D-FET, the gate electrode is directly formed on the cap layer 15 without removing the cap layer 15 under the gate electrode in each of Examples 5 to 9.

[0138]

As described above, according to the present invention, the 2DEG layer formed at the interface between the first compound semiconductor layer and the second compound semiconductor layer laminated on the conductive substrate is used as a linear transmission line. By forming electrodes at both ends of this transmission line, the capacitance component between the 2DEG layer and the conductive substrate and the 2DE
An impedance line, a filter element, and a delay element can be formed by utilizing the resistance component of the G layer. Further, in the semiconductor device of the present invention, the transmission line formed by the two-dimensional electron gas layer is used as a wiring for connecting the transistors in the semiconductor device, and the wiring itself is an impedance line,
Since the filter element and the delay element can be used, it is not necessary to separately manufacture the capacitor and the impedance line. Therefore, the structure of the semiconductor device is simplified, the degree of integration is improved, and the manufacturing process can be simplified.

[Brief description of drawings]

1A and 1B are drawings for explaining an element structure of Example 1 to which the present invention is applied, FIG. 1A is a plan view, FIG. 1B is a sectional view taken along line AA in FIG. 1A, and FIG. Figure 1
It is sectional drawing in the BB line in a.

2A and 2B are views for explaining an element structure of Example 2 to which the present invention is applied, FIG. 2A is a plan view, FIG. 2B is a sectional view taken along line AA in FIG. 2A, and FIG. Is Figure 2
It is sectional drawing in the BB line in a.

3A and 3B are drawings for explaining an element structure of Example 3 to which the present invention is applied, FIG. 3A is a plan view, FIG. 3B is a sectional view taken along line AA in FIG. 3A, and FIG. Figure 3
It is sectional drawing in the BB line in a.

4A and 4B are drawings for explaining an element structure of Example 4 to which the present invention is applied, FIG. 4A is a plan view, FIG. 4B is a sectional view taken along line AA in FIG. 4A, and FIG. Is Figure 4
It is sectional drawing in the BB line in a.

5A and 5B are drawings for explaining a structure of a semiconductor device according to a fifth embodiment of the present invention, FIG. 5A is a plan view, and FIG. 5B is a sectional view taken along line AA in FIG. 5A. Figure 5
5c is a sectional view taken along line BB in FIG. 5a.

6A and 6B are drawings for explaining a structure of a semiconductor device according to a sixth embodiment of the present invention, FIG. 6A is a plan view, and FIG. 6B is a sectional view taken along line AA in FIG. 6A. Figure 6
6c is a sectional view taken along line BB in FIG. 6a.

7A and 7B are drawings for explaining the structure of a semiconductor device according to a seventh embodiment of the present invention, FIG. 7A is a plan view, and FIG. 7B is a sectional view taken along line AA in FIG. 7A. Figure 7
FIG. 7c is a sectional view taken along line BB in FIG. 7a.

8A and 8B are drawings for explaining the structure of a semiconductor device of Example 8 to which the present invention is applied, FIG. 8A is a plan view, FIG. 8B is a cross-sectional view taken along line AA in FIG. 8A, Figure 8
8c is a sectional view taken along line BB in FIG. 8a.

9A and 9B are drawings for explaining the structure of a semiconductor device according to a ninth embodiment of the present invention, FIG. 9A is a plan view, and FIG. 9B is a cross-sectional view taken along line AA in FIG. 9A; Figure 9
9c is a sectional view taken along line BB in FIG. 9a.

[Explanation of symbols]

1, 2 ... Two-dimensional electron gas field effect transistor, 1
S, 2S ... Source electrode, 1D, 2D ... Drain electrode,
1G, 2G ... Gate electrode, 11 ... Substrate, 12 ... Buffer layer, 13 ... GaAs layer (first compound semiconductor layer), 1
4 ... AlGaAs layer (second compound semiconductor layer), 15 ...
Cap layer, 16 ... 2D
EG layer, 17 ... Ohmic diffusion layer,
18, 19 ... Electrodes, 20 ... Transmission lines,
25 ... Element isolation electrode, 26 ... Control electrode, 30 ... Ohmic electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/095 9171-4M H01L 29/80 R

Claims (20)

[Claims] 1. Laminating a first compound semiconductor layer on a conductive substrate and a second compound semiconductor layer having a composition different from that of the first compound semiconductor layer on the first compound semiconductor layer. To form a two-dimensional electron gas layer at the junction interface between the first compound semiconductor layer and the second compound semiconductor layer, and leave the two-dimensional electron gas layer in a linear shape. An impedance line, characterized in that an electrode is provided on the second compound semiconductor layer at both ends of the layer, and a diffusion layer reaching the two-dimensional electron gas layer is formed under the electrode. 2. The first compound semiconductor layer and the second compound semiconductor layer are etched in portions where an unnecessary two-dimensional electron gas layer is formed in order to leave the two-dimensional electron gas layer linear. The impedance line according to claim 1, wherein the impedance line is removed by. 3. An electrode for applying a potential of 0 V or less is formed on an unnecessary portion of the two-dimensional electron gas layer in order to leave the two-dimensional electron gas layer in a linear shape. The impedance line according to 1. 4. Oxygen is added to portions of the first compound semiconductor layer and the second compound semiconductor layer where unnecessary two-dimensional electron gas layers are formed in order to leave the two-dimensional electron gas layers linear. The impedance line according to claim 1, wherein ions are implanted. 5. A control electrode is provided on a portion of the second compound semiconductor layer where the two-dimensional electron gas layer is left linearly, and a control electrode is provided. Impedance line described. 6. Laminating a first compound semiconductor layer on a conductive substrate, and a second compound semiconductor layer having a composition different from that of the first compound semiconductor layer on the first compound semiconductor layer. To form a two-dimensional electron gas layer at the junction interface between the first compound semiconductor layer and the second compound semiconductor layer, and leave the two-dimensional electron gas layer in a linear shape. An electrode is provided on the second compound semiconductor layer at both ends of the layer, and a diffusion layer reaching the two-dimensional electron gas layer is formed under the electrode. 7. The first compound semiconductor layer and the second compound semiconductor layer are etched in a portion where an unnecessary two-dimensional electron gas layer is formed in order to leave the two-dimensional electron gas layer in a linear shape. The filter element according to claim 6, wherein the filter element is removed by. 8. An electrode for applying a potential of 0 V or less is formed on an unnecessary portion of the two-dimensional electron gas layer in order to leave the two-dimensional electron gas layer in a linear shape. 6. The filter element according to item 6. 9. Oxygen is added to the portions of the first compound semiconductor layer and the second compound semiconductor layer where unnecessary two-dimensional electron gas layers are formed in order to leave the two-dimensional electron gas layers linear. The filter element according to claim 6, wherein ions are implanted. 10. The control electrode is provided on a portion of the second compound semiconductor layer where the two-dimensional electron gas layer is left linearly, and a control electrode is provided on the second compound semiconductor layer. The described filter element. 11. Laminating a first compound semiconductor layer on a conductive substrate, and a second compound semiconductor layer having a composition different from that of the first compound semiconductor layer on the first compound semiconductor layer. Thereby forming a two-dimensional electron gas layer at the junction interface between the first compound semiconductor layer and the second compound semiconductor layer,
The two-dimensional electron gas layer is left in a linear shape, electrodes are provided on the second compound semiconductor layers at both ends of the linear two-dimensional electron gas layer, and diffusion to reach the two-dimensional electron gas layer is formed under the electrode. A delay element comprising a layer. 12. The first compound semiconductor layer and the second compound semiconductor layer are etched in a portion where an unnecessary two-dimensional electron gas layer is formed in order to leave the two-dimensional electron gas layer in a linear shape. 12. The delay element according to claim 11, wherein the delay element is removed by. 13. An electrode for applying a potential of 0 V or less is formed on an unnecessary portion of the two-dimensional electron gas layer in order to leave the two-dimensional electron gas layer in a linear shape. 11. The delay element according to item 11. 14. Oxygen is contained in a portion of the first compound semiconductor layer and the second compound semiconductor layer where an unnecessary two-dimensional electron gas layer is formed in order to leave the two-dimensional electron gas layer in a linear shape. Ions are implanted, and
1. The delay element according to 1. 15. The control electrode is provided on a portion of the second compound semiconductor layer where the two-dimensional electron gas layer is left in a linear shape, according to any one of claims 11 to 14. The described delay element. 16. A first compound semiconductor layer and a second compound semiconductor layer having a different composition formed on the first compound semiconductor layer and the first compound semiconductor layer on a conductive substrate. A two-dimensional electron gas electric field effect in which a two-dimensional electron gas layer is formed at a junction interface with the second compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode are formed on the second compound semiconductor layer. In a semiconductor device in which a plurality of transistors are integrated, the two-dimensional electron gas field effect transistors are electrically connected to each other, leaving a two-dimensional electron gas layer in a portion where the two-dimensional electron gas field effect transistors are electrically connected, A semiconductor device characterized by extinguishing a gas layer. 17. The connection becomes unnecessary because the two-dimensional electron gas layer in the portion connecting the plurality of two-dimensional field effect transistors is left and the two-dimensional electron gas layer in the portion not needing connection disappears. 17. The semiconductor device according to claim 16, wherein the first compound semiconductor layer and the second compound semiconductor layer in a portion where the dimensional electron gas layer is formed are removed by etching. 18. In order to leave the two-dimensional electron gas layer in the portion connecting the plurality of two-dimensional field effect transistors and to eliminate the two-dimensional electron gas layer in the portion not requiring the connection, 0V on the two-dimensional electron gas layer
The semiconductor device according to claim 16, wherein an electrode for applying the following potential is formed. 19. Two-dimensional electrons which do not require connection because the two-dimensional electron gas layer of the portion connecting the plurality of two-dimensional field effect transistors is left and the two-dimensional electron gas layer which does not need to be connected disappears. 17. The semiconductor device according to claim 16, wherein oxygen ions are implanted into the first compound semiconductor layer and the second compound semiconductor layer in a portion where a gas layer is formed. 20. A control electrode is provided on the portion of the second compound semiconductor layer where the two-dimensional electron gas layer of the portion connecting the plurality of two-dimensional field effect transistors is left. 20. The semiconductor device according to any one of items 16 to 19.