JP3087278B2 - Monolithic integrated circuit device - Google Patents
Monolithic integrated circuit deviceInfo
- Publication number
- JP3087278B2 JP3087278B2 JP01339683A JP33968389A JP3087278B2 JP 3087278 B2 JP3087278 B2 JP 3087278B2 JP 01339683 A JP01339683 A JP 01339683A JP 33968389 A JP33968389 A JP 33968389A JP 3087278 B2 JP3087278 B2 JP 3087278B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- integrated circuit
- monolithic integrated
- circuit device
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はモノリシック集積回路素子に関し、特に、よ
り優れた低雑音用トランジスタを能動素子とし、バイア
ス回路の一体化をも含めたモノリシック集積回路素子に
関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic integrated circuit device, and more particularly, to a monolithic integrated circuit device in which a better low-noise transistor is used as an active device and a bias circuit is integrated. About.
近年、半導体トランジスタについては超高周波域での
性能向上と共に、整合回路や保護回路，又電源回路をも
半導体基板上に一体構成したモノリシック集積回路素子
が各所で検討されている。とりわけ、GaAsは半絶縁性基
板が容易に得られる事や高速性に適している事から、1G
Hz以上のより超高周波帯域で、増幅器，発振器，位相
器，あるいは分周器等のモノリシック素子が検討されて
いる。In recent years, with respect to semiconductor transistors, monolithic integrated circuit elements in which a matching circuit, a protection circuit, and a power supply circuit are integrally formed on a semiconductor substrate have been studied in various places along with the improvement in performance in an ultra-high frequency range. In particular, GaAs is suitable for 1S because it can easily obtain semi-insulating substrates and is suitable for high-speed operation.
Monolithic devices such as amplifiers, oscillators, phase shifters, and frequency dividers are being studied in the ultra-high frequency band above Hz.
このようなモノリシック集積回路素子としては、例え
ば今井らが1983年に電子通信学会技術報告（ED82−11
6）において報告している。これは第３図に示すよう
に、能動素子として、GaAs MESFETを、又、受動素子と
して抵抗，容量およびインダクタを用いたものである。As such a monolithic integrated circuit device, for example, Imai et al. In 1983, IEICE Technical Report (ED82-11).
6). As shown in FIG. 3, this uses GaAs MESFETs as active elements and resistors, capacitors and inductors as passive elements.
すなわち、半絶縁性基板31上にFETの能動層33,コンタ
クト層34,更に抵抗層32がイオン注入法により形成され
た後に、FETのゲート電極36およびソース電極37,ドレイ
ン電極38のオーミック電極，更に、第１層電極39に接続
するキャパシタ下部電極42と誘電体膜43と第２層電極41
から構成される平行平板型のキャパシタ部、又、第２層
電極41を用いてインダクタ部を設ける事によって、モノ
リシック集積回路素子が得られていた。That is, after the active layer 33, the contact layer 34, and the resistance layer 32 of the FET are formed on the semi-insulating substrate 31 by the ion implantation method, the ohmic electrodes of the gate electrode 36, the source electrode 37, and the drain electrode 38 of the FET are formed. Further, the capacitor lower electrode 42 connected to the first layer electrode 39, the dielectric film 43, and the second layer electrode 41
A monolithic integrated circuit device has been obtained by providing an inductor portion using a parallel plate type capacitor portion composed of the above-mentioned and a second layer electrode 41.
一方、超高周波帯でより高性能な素子として、高純度
半導体層と、電子親和力の異なるドーピングされた半導
体層のヘテロ接合を用いたFETが、従来のMESFETを凌駕
する素子として、注目され、一部は、低雑音用として製
品化されている。このようなより優れたヘテロ接合FET
（以下HJFETと称する）を用いたモノリシック素子は、
開発が始まった段階であり、従来例としては、綾木らが
1988年に電子通信学会技術報告（CPM88−８）におい
て、報告している。第４図にその低雑音増幅素子の断面
図を示す。On the other hand, FETs using a heterojunction of a high-purity semiconductor layer and a doped semiconductor layer having a different electron affinity as a device with higher performance in an ultra-high frequency band have attracted attention as a device that surpasses conventional MESFETs. The unit is commercialized for low noise. Such a better heterojunction FET
(Hereinafter referred to as HJFET)
At the stage when development has begun, Ayaki et al.
This was reported in the Technical Report of the Institute of Electronics and Communication Engineers (CPM88-8) in 1988. FIG. 4 is a sectional view of the low-noise amplifier.
これは半絶縁性基板31上に高純度半導体層45,電子親
和力が異なるドーピングされた半導体層46,高濃度キャ
ップ層47がMBE法で順次成長された後に、ソース電極37,
ドレイン電極38のオーミック電極，およびゲート電極3
6,更にキャパシタ下部電極42と誘電体膜43および第２層
電極41からなるキャパシタ部，又、第２層電極41を用い
てインダクタ部を設ける事によってモノリシック集積回
路素子が得られていた。尚、この時、抵抗層32として
は、高濃度キャップ層47を用いて形成している。This is because a high-purity semiconductor layer 45, a doped semiconductor layer 46 having a different electron affinity, and a high-concentration cap layer 47 are sequentially grown on the semi-insulating substrate 31 by MBE, and then the source electrode 37,
Ohmic electrode of drain electrode 38 and gate electrode 3
6, a monolithic integrated circuit device has been obtained by providing a capacitor portion comprising a capacitor lower electrode 42, a dielectric film 43 and a second layer electrode 41, and an inductor portion using the second layer electrode 41. At this time, the resistance layer 32 is formed using the high concentration cap layer 47.
従来のこのようにして得られたモノリシック集積回路
素子では、確かに所望の利得−周波数特性が、MESFETよ
り優れたものが達成されているが、抵抗素子を高濃度キ
ャップ層47を用いて形成している為に、100Ω以下の抵
抗は実現できるが、電源バイアスフィードに用いる様な
約1KΩの抵抗を実現するのは困難である。従って、バイ
アス回路はモノリシック集積化できず、外付けしなけれ
ばならないという欠点がある。In the conventional monolithic integrated circuit device obtained in this way, although the desired gain-frequency characteristic is certainly better than that of the MESFET, the resistive element is formed by using the high-concentration cap layer 47. Therefore, it is possible to realize a resistance of 100Ω or less, but it is difficult to realize a resistance of about 1KΩ used for a power supply bias feed. Therefore, there is a disadvantage that the bias circuit cannot be monolithically integrated and must be externally provided.
上述した従来のモノリシック集積回路素子に対し、本
発明は高濃度キャップ層の抵抗と共に、高純度層とドー
ピング層とのヘテロ接合の抵抗をモノリシック回路の抵
抗素子として用いるという相違点を有する。Compared with the conventional monolithic integrated circuit device described above, the present invention has a difference in that the resistance of the heterojunction between the high-purity layer and the doping layer is used as the resistance element of the monolithic circuit, in addition to the resistance of the high-concentration cap layer.
本発明のモノリシック集積回路素子は、高純度の第１
の半導体層と不純物がドーピングされた第２の半導体層
からなるヘテロ接合構造を用いた電界効果トランジスタ
を能動素子とするモノリシック集積回路素子であって、
前記ヘテロ接合構造上に形成された高濃度キャップ層か
ら前記第２の半導体層にかけて掘り込むことによって形
成されたヘテロ接合界面の抵抗からなる抵抗素子を有す
ることを特徴としている。The monolithic integrated circuit device of the present invention has a high purity
A monolithic integrated circuit device using a field-effect transistor using a heterojunction structure comprising a semiconductor layer and a second semiconductor layer doped with impurities as an active device,
The semiconductor device is characterized by having a resistance element formed by digging from the high-concentration cap layer formed on the heterojunction structure to the second semiconductor layer, the resistance element being formed at a heterojunction interface.
次に、本発明の典型的な一実施例である抵抗，インダ
クタ，キャパシタを整合回路素子とし、AlGaAs/GaAsヘ
テロ接合FETを能動素子とするモノリシック増幅器素子
の場合について図面を参照して説明する。Next, a description will be given of a typical embodiment of a monolithic amplifier device in which a resistor, an inductor, and a capacitor are used as matching circuit devices and an AlGaAs / GaAs heterojunction FET is used as an active device, with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。 FIG. 1 is a sectional view of a first embodiment of the present invention.
まず第１図（ａ）に示すように、半絶縁性GaAs基板11
上に、第１の半導体層として高純度のアンドープGaAs1
2,電子親和力の異なる不純物がドーピングされた第２の
半導体層としてn+AlGaAs（Nd＝２×1018cm-3）13,アン
ドープGaAs14,更にキャップ層であるn+GaAs15を順次MBE
法により成長させる。次に、ソース電極16,ドレイン電
極17,抵抗電極18,キャパシタ下部電極19をAuGeNi/Ti/Pt
/AuをスペーサSiO222を用いたリフトオフ法により形成
した後、第１の抵抗20をn+GaAsキャップ層15を窓開けす
る事で、又第２の抵抗21をn+AlGaAs13に到達するように
掘り込む事によって形成する。First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 11 is formed.
On top, high-purity undoped GaAs1 is used as the first semiconductor layer.
2, n + AlGaAs (Nd = 2 × 10 18 cm −3 ) 13, undoped GaAs 14 as a second semiconductor layer doped with impurities having different electron affinities, and n + GaAs 15 as a cap layer are successively formed by MBE.
Grow by the method. Next, the source electrode 16, the drain electrode 17, the resistance electrode 18, and the capacitor lower electrode 19 were
After the / Au is formed by the lift-off method using the spacer SiO 2 22, the first resistor 20 is opened in the n + GaAs cap layer 15 so that the second resistor 21 reaches the n + AlGaAs 13. It is formed by digging into.
次に第１図（ｂ）に示すように、電流値をモニターし
ながらアンドープGaAs14,n+GaAs15を掘り込んだのち、A
lを真空蒸着法により被着しリフトオフ法によりゲート
電極25を形成する。更に窒化膜からなる誘電体膜24を表
面保護膜を兼ねて設けた後、Ti/Pt/Au/Auメッキ層から
なるキャパシタ上部電極27および配線金属26を形成し
て、FET部、第1,第２抵抗部、キャパシタ部及びインダ
クタ部よりなるモノリシック増幅素子を完成させる。Next, as shown in FIG. 1 (b), undoped GaAs14 and n + GaAs15 were dug while monitoring the current value.
is deposited by a vacuum evaporation method, and a gate electrode 25 is formed by a lift-off method. Further, after a dielectric film 24 made of a nitride film is provided also as a surface protection film, a capacitor upper electrode 27 made of a Ti / Pt / Au / Au plating layer and a wiring metal 26 are formed, and the FET portion, A monolithic amplifying device including the second resistor, the capacitor, and the inductor is completed.
このように第１の実施例によれば、100Ω／□以下の
比抵抗をもつキャップ層の抵抗と約1KΩ／□の比抵抗を
もつヘテロ接合の抵抗が得られる。As described above, according to the first embodiment, the resistance of the cap layer having a specific resistance of 100 Ω / □ or less and the resistance of the heterojunction having the specific resistance of about 1 KΩ / □ can be obtained.
第２図は本発明の第２の実施例の断面図である。 FIG. 2 is a sectional view of a second embodiment of the present invention.
半絶縁性GaAs基板11上に高純度のアンドープInGaAs層
28,n+InAlAs層（Nd２×1018cm-3）29,アンドープGaAs
層14,n+GaAsキャップ層15をそれぞれMBE法に成長させ
る。次で第１の実施例と同様に、FET部、第1,第２抵抗
部、キャパシタ部及びインダクタ部を形成する事によっ
てモノリシック集積回路素子が得られる。High purity undoped InGaAs layer on semi-insulating GaAs substrate 11.
28, n + InAlAs layer (Nd2 × 10 18 cm -3 ) 29, undoped GaAs
The layer 14 and the n + GaAs cap layer 15 are respectively grown by MBE. Next, as in the first embodiment, a monolithic integrated circuit device can be obtained by forming the FET section, the first and second resistance sections, the capacitor section, and the inductor section.
この第２の実施例ではInAlAs/InGaAsのヘテロ接合を
用いることによって、飽和速度が1.5倍と大きくなるた
めに、超高周波で雑音特性のすぐれたモノリシック増幅
素子が得られるという利点がある。In the second embodiment, the use of an InAlAs / InGaAs heterojunction has an advantage that a monolithic amplifying element having excellent noise characteristics at an ultrahigh frequency can be obtained because the saturation speed is increased to 1.5 times.
以上説明したように本発明は、ヘテロ接合FETを能動
素子とし、そのヘテロ接合の抵抗及びキャップ層の抵抗
を用いる事によって、整合回路用の低抵抗と共に、バイ
アスフィード用の高抵抗を実現でき、電源バイアス回路
をも一体化でき、超高周波で高性能なモノリシック集積
回路素子が実現できるという効果を有する。As described above, according to the present invention, a heterojunction FET is used as an active element, and by using the resistance of the heterojunction and the resistance of the cap layer, a low resistance for a matching circuit and a high resistance for a bias feed can be realized. The power supply bias circuit can also be integrated, and there is an effect that a monolithic integrated circuit element with high frequency and high performance can be realized.
第１図及び第２図は本発明の第１及び第２の実施例を説
明するための半導体チップの断面図、第３図及び第４図
は従来のモノリシック集積回路の断面図である。 11……半絶縁性GaAs基板、12……アンドープGaAs、13…
…n+AlGaAs,14……アンドープGaAs、15……n+GaAs、16,
37……ソース電極、17,38……ドレイン電極、25,36……
ゲート電極、18……抵抗電極、20……第１の抵抗、21…
…第２の抵抗、22……スペーサSiO2、24……誘電体膜、
26……配線金属、27……キャパシタ上部電極、28……ア
ンドープInGaAs、29……n+InAlAs、31……半絶縁性基
板、32……抵抗層、33……能動層、34……コンタクト
層、39……第１層電極、40……層間絶縁膜、41……第２
層電極、42……キャパシタ下部電極、43……誘電体膜、
44……スペーサ層、45……高純度半導体層、46……ドー
ピング層、47……高純度キャップ層、56……アンドープ
層。FIGS. 1 and 2 are sectional views of a semiconductor chip for explaining the first and second embodiments of the present invention, and FIGS. 3 and 4 are sectional views of a conventional monolithic integrated circuit. 11 ... Semi-insulating GaAs substrate, 12 ... Undoped GaAs, 13 ...
… N + AlGaAs, 14 …… undoped GaAs, 15 …… n + GaAs, 16,
37 …… Source electrode, 17,38 …… Drain electrode, 25,36 ……
Gate electrode, 18 ... Resistance electrode, 20 ... First resistance, 21 ...
... second resistor, 22 ...... spacer SiO 2, 24 ...... dielectric film,
26 ... wiring metal, 27 ... capacitor upper electrode, 28 ... undoped InGaAs, 29 ... n + InAlAs, 31 ... semi-insulating substrate, 32 ... resistive layer, 33 ... active layer, 34 ... contact Layer 39, first layer electrode 40 interlayer insulating film 41 second
Layer electrode, 42: capacitor lower electrode, 43: dielectric film,
44 ... spacer layer, 45 ... high-purity semiconductor layer, 46 ... doping layer, 47 ... high-purity cap layer, 56 ... undoped layer.
Claims (2)
ングされた第２の半導体層からなるヘテロ接合構造を用
いた電界効果トランジスタを能動素子とするモノリシッ
ク集積回路素子であって、前記ヘテロ接合構造上に形成
された高濃度キャップ層から前記第２の半導体層にかけ
て掘り込むことによって形成されたヘテロ接合界面の抵
抗からなる抵抗素子を有することを特徴とするモノリシ
ック集積回路素子。1. A monolithic integrated circuit device having a field effect transistor using a heterojunction structure comprising a high-purity first semiconductor layer and a second semiconductor layer doped with impurities as an active device, wherein A monolithic integrated circuit device, comprising: a resistance element having a resistance at a heterojunction interface formed by digging from a high-concentration cap layer formed on a junction structure to the second semiconductor layer.
あり、前記第２の半導体層はAlGaAsまたはInAlAsである
請求項１記載のモノリシック集積回路素子。2. The monolithic integrated circuit device according to claim 1, wherein said first semiconductor layer is made of GaAs or InGaAs, and said second semiconductor layer is made of AlGaAs or InAlAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01339683A JP3087278B2 (en) | 1989-12-26 | 1989-12-26 | Monolithic integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01339683A JP3087278B2 (en) | 1989-12-26 | 1989-12-26 | Monolithic integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03198373A JPH03198373A (en) | 1991-08-29 |
| JP3087278B2 true JP3087278B2 (en) | 2000-09-11 |
Family
ID=18329809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01339683A Expired - Fee Related JP3087278B2 (en) | 1989-12-26 | 1989-12-26 | Monolithic integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3087278B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233147A (en) * | 2019-05-08 | 2019-09-13 | 福建省福联集成电路有限公司 | A kind of stacked inductance and production method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844299A (en) * | 1997-01-31 | 1998-12-01 | National Semiconductor Corporation | Integrated inductor |
| US6326314B1 (en) | 1997-09-18 | 2001-12-04 | National Semiconductor Corporation | Integrated inductor with filled etch |
| JP5211421B2 (en) * | 2005-08-22 | 2013-06-12 | 三菱電機株式会社 | Cascode connection circuit |
| JP5457292B2 (en) * | 2010-07-12 | 2014-04-02 | パナソニック株式会社 | Nitride semiconductor device |
-
1989
- 1989-12-26 JP JP01339683A patent/JP3087278B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233147A (en) * | 2019-05-08 | 2019-09-13 | 福建省福联集成电路有限公司 | A kind of stacked inductance and production method |
| CN110233147B (en) * | 2019-05-08 | 2021-03-09 | 福建省福联集成电路有限公司 | Stacked inductor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03198373A (en) | 1991-08-29 |
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