JP2822498B2 - Dual gate FET - Google Patents

Description

The present invention relates to a dual-gate FET which is used for high-frequency amplification and has excellent power gain and noise figure, and which uses a fixed second gate voltage. Things.

[Summary of the Invention] Dual gate FE using fixed voltage of second gate
At T, a voltage equal to the threshold voltage of the second gate is extracted from the first resistance and the second resistance connected in series between the drain electrode and the source electrode, and the second gate is connected via the dump resistance. This is a dual-gate FET set to apply a fixed bias to. If the voltage of the second gate is equal to the threshold voltage, the power gain, the noise figure, and the intermodulation characteristics are excellent, and the stability such as amplification can be improved by the dump resistor.

[Conventional technology]

Dual-gate FETs include 4-pole MOSFETs and 4-pole junction FETs
And 4-pole Schottky gate type FET. Since it is a dual gate, the mirror effect can be reduced, so that it has excellent high frequency characteristics. In particular, a 4-pole Schottky gate FET is used to obtain a high power gain and noise figure.

As shown in FIG. 7, this 4-pole Schottky gate FET (hereinafter referred to as a 4-pole MESFET) is activated by using an insulating film 2 such as a nitride film on the surface of a semi-insulating semiconductor substrate 1 such as GaAs. After the layer 3 and the source region 5a and the drain region 5b are formed by ion implantation or the like, a Schottky barrier is formed with a Schottky metal 8 such as Al, and
A gate metal 9a and a second gate metal 9b are formed. After the ohmic metal 6 is deposited on the source and drain regions, a source electrode 7a and a drain electrode 7b are formed.

When a predetermined voltage is applied between the drain electrode and the source electrode of the dual gate FET formed as described above and an input signal is applied to the first gate electrode to operate, the respective regions of the active layer 3 in FIG. The depletion layer 4 depending on the gate voltage is generated, and the current can be controlled. When the drain voltage is 0 V, the gate voltage is the threshold voltage when the elongation of the depletion layer is equal to the thickness of the active layer. Therefore, if the active layer pressure is low, the depletion type is used. Easy to be.

On the other hand, if the second gate electrode is used by grounding or by applying a fixed bias, the Miller effect is small and the power gain and the noise figure are excellent.
It is often used in a state where it is AC grounded by a fixed bias or a variable bias. The conventional 4 shown in FIG.
As shown in the circuit diagram of the polar MESFET, when the source electrode 7a is grounded, a drain voltage is applied to the drain electrode 7b, and an input signal is applied to the first gate electrode 9a, the second gate electrode 9b is biased. There is an apparatus in which an optimum operating voltage is applied via the control circuit 10 (JP-A-64-49409).

[Problems to be solved by the invention]

When the second gate electrode is grounded, components such as external resistors are unnecessary, but the high frequency characteristics are not sufficiently exhibited.
In order to improve the power gain and the noise figure and to have excellent intermodulation characteristics, it is necessary to optimally set the bias voltage of the second gate, and a resistor or a branch resistor for applying the bias voltage is required. It had to be formed integrally with the FET. In addition, when a bias voltage is applied, it is necessary to remove oscillation or instability due to impedance mismatch or the like.

[Means for solving the problem]

According to the present invention, in order to solve the above-mentioned problem, a first resistor and a second resistor are connected between a drain electrode and a source electrode, and the connection point is connected to a second gate via a third resistor. ,
By setting the ratio of the first resistor to the second resistor so that a voltage equal to the threshold value is applied, excellent characteristics are realized.

[Action]

If the bias voltage of the second gate is too low compared to the threshold voltage, the power gain is small and the noise figure is high. If the bias voltage is too high, the power gain has a saturated value. The noise figure is poor, and the linearity is poor due to the saturation region, and therefore the cross-modulation characteristics are poor. If the third resistor is used as a dump resistor, oscillation and instability can be reduced.

〔Example〕

A typical example of the dual gate FET of the present invention is a 4-pole M
The ESFET will be described with reference to FIGS.

First, FIG. 1 shows an equivalent circuit diagram of a four-pole MESFET of the present invention. A dual-gate FET having a source electrode 7a and a drain electrode 7b, and a first gate electrode 9a and a second gate electrode 9b. In order to apply a voltage equal to a threshold value to the second gate electrode 9b, Electrode 7b and source electrode
A first resistor R ₁ 11 a second resistor R ₂ 12 is connected in series between the 7a. In this case the resistance ratio R ₂ / R ₁ + R ₂ is, the threshold voltage V
_P, the value of R ₂ / R ₁ + R ₂ when the drain voltage is V _D is V _P / V _D
Set the ratio between R ₁ and R ₂ to be equal to Normally, increasing the value of R ₁ and R ₂ than the value of the channel resistance, to set, for example, in a range of several tens of ohms to several kilo-ohms desirable. This first resistor 11 from a connecting point of the second resistor 12, a third resistor R ₃ 13 through the second gate electrode 9b, applies a voltage substantially equal to the threshold.

Next, the structure of the above-described four-pole MESFET incorporating a resistor will be described with reference to FIGS. FIG. 2 is a plan view of a four-pole MESFET of the present invention, FIG.
The figure shows a BB sectional view.

As shown in FIG. 2, the source electrode 7a and the drain electrode 7b form a pattern arranged on both sides of the first gate electrode 9a and the second gate electrode 9b on the surface of the semiconductor substrate 1. FIG. 3 is a sectional view taken along line AA of the fixed bias resistor portion, which is a main portion of the present invention, and FIG. 4 is a sectional view taken along line BB of the dump resistor portion.

As shown in FIG. 3, the drain region 5b and the first resistor 11
The region of the second resistor 12 is formed by ion implantation or diffusion, and the ohmic metal 6 at the drain portion and the drain electrode 7b are formed. The first resistor 11 and the second resistor 12 can be formed simultaneously with the active layer region as a lower concentration of N ⁻ than the source and drain regions. A portion near the drain is referred to as a first resistor 11 and a portion near the source is referred to as a second resistor 12.

Next, as shown in FIG.
One end of the resistor 13 is connected to the first resistor 11 and the second resistor 12 described above.
At a predetermined position, and the other end is connected to the second gate electrode 9b.
Connect to The connection is preferably made via the ohmic electrode 6.

The high-frequency characteristics of the 4-pole MESFET thus formed are
This is shown in FIG. 5 and FIG.

FIG. 5 is a diagram showing the power gain with respect to the first gate voltage using the second gate voltage as a parameter.
The power gain increases as the gate voltage increases, but the power gain becomes saturated near 1.5 V exceeding the threshold voltage.

FIG. 6 is a diagram showing the noise figure with respect to the first gate voltage using the second gate voltage as a parameter.
The noise figure tends to decrease as the gate voltage increases, but the noise figure becomes saturated near 1.5 V exceeding the threshold voltage. Since the linearity is not good in the saturated state, the cross-modulation characteristic is also deteriorated.

Although the embodiment of the present invention has been described using the 4-pole MESFET,
It is preferable to use a similar structure in a pole MOSFET and a quadrupole junction FET. Also, the connection may be made by using a resistor such as polysilicon instead of the diffusion resistor.

〔The invention's effect〕

If a dual-gate FET such as the four-pole MESFET of the present invention is used, the first and second resistors for setting the fixed bias voltage applied to the second gate to an optimum value, and further as a dump resistor Since the second gate voltage is fixed via the third resistor, a large power gain and a low noise figure at a high frequency can be obtained, and since it is used in a range with good linearity, the intermodulation characteristics are excellent and the dump resistor is used. Stable operation can be realized.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of the four-pole MESFET of the present invention, FIG. 2 is a plan view of the four-pole MESFET of the present invention, FIG. 3 is a cross-sectional view taken along the line AA of FIG. 2, and FIG. 5 is a diagram showing the power gain of the four-pole MESFET of the present invention, FIG. 6 is a diagram showing the noise figure of the four-pole MESFET of the present invention, and FIG. 7 is a conventional four-pole MESFET.
FIG. 8 is a circuit diagram of a conventional 4-pole MESFET. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating film 3 ... Active layer 4 ... Depletion layer 5a ... Source region 5b ... Drain region 6 ... Ohmic metal 7a ... Source electrode 7b ... Drain electrode 8 ... Schottky Gate metal 9a First gate electrode 9b Second gate electrode 10 Bias resistor 11 First resistor 12 Second resistor 13 Third resistor

──────────────────────────────────────────────────の Continued on the front page (58) Surveyed fields (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/336 H01L 29/76 H01L 29/772 H01L 29/78

Claims (1)

(57) [Claims] In a dual gate FET using a fixed voltage of a second gate, a first resistor and a second resistor are connected in series between a drain electrode and a source electrode, and the first gate and the second resistor are connected in series. When a fixed bias is applied to the second gate from a connection point between a resistor and a second resistor via a third resistor, the voltage at the connection point is equal to the threshold voltage of the second gate. A dual gate FET, wherein a ratio between a first resistance and a second resistance is provided.