JP2798051B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor using a compound semiconductor such as GaAs.

[0002]

2. Description of the Related Art A GaAs field-effect transistor is used as a high-power amplifier. FIG. 2 shows a conventional GaAs.
1 shows a field effect transistor (refer to Japanese Patent Application Laid-Open No. 3-201)
448). 2A is an overall plan view, FIG. 2B is an enlarged plan view of a portion B of FIG. 2A, and FIG. 2C is a cross-sectional view of FIG. In FIG. 2, an N-type Ga as a carrier transit layer is provided on a semi-insulating GaAs substrate 2 of a chip 1.
An As electron transit layer 3 is formed, and a recess region 4 is formed in a part thereof. A gate electrode 5 is formed in the recess region 4 on the N-type GaAs electron transit layer 3, and a source electrode 6 and a drain electrode 7 are formed on both sides of the recess region 4 on the N-type GaAs electron transit layer 3. I have. Further, a gate pad 8, a source pad 9, and a drain pad 10 are connected to the gate electrode 5, the source electrode 6, and the drain electrode 7, respectively.

FIG. 3 is an equivalent circuit diagram of the simplicity viewed from the drain pad 10 of FIG.
A negative resistance R by the respective patterns of the source electrode 6 and drain electrode 7 is the inductance L and capacitance C and GaAs field-effect transistor are connected in series, a load resistance R _L is connected in parallel with tuned circuit in this series circuit Is composed.

In the tuning circuit of FIG. 3, when R _L <| R |, even if a signal is input to the drain pad 10, the tuning circuit loses the oscillation due to the loss of the tuning circuit, so that unnecessary oscillation does not occur.

On the other hand, in the tuning circuit of FIG. 3, when R _L ≧ | R |, when a signal is input to the drain pad 10, the loss of the tuning circuit is compensated by the negative resistance R. Occurs. Here, the inductance L and the capacitance C in FIG. 3 are parameters for determining the frequency condition, the gain, and the positive feedback amount of the unnecessary oscillation. For example, the frequency of the unnecessary oscillation is a frequency when the resistance of the impedance viewed from the drain pad 10 becomes negative and the reactance of the impedance becomes zero. When the product of the gain of the field effect transistor and the amount of positive feedback (in-phase feedback) from the drain electrode 7 to the gate electrode 5 due to the inductance L and the capacitance C is 1 or more, the impedance seen from the drain pad 10 is Becomes negative. In addition,
As shown in FIG. 2, as the number of fins of the multi-finger increases and the layout of each electrode pattern increases, the inductance L and the capacitance C increase. .

[0006]

As described above, the field effect transistor having the negative resistance characteristic has a problem that unnecessary oscillation occurs. Therefore, an object of the present invention is to provide a field effect transistor having a negative resistance characteristic in which unnecessary oscillation is suppressed.

[0007]

According to the present invention, there is provided a field effect transistor having a negative resistance characteristic, wherein a drain pad of the field effect transistor has a length of １ ／ of the wavelength of the unnecessary oscillation frequency. A stub with an open end is connected.

[0008]

FIG. 1 shows an embodiment of a GaAs field effect transistor according to the present invention. 1A is an overall plan view, FIG. 1B is an enlarged plan view of a portion B of FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. In FIG. 1, the open-end stub 1 is connected to the drain pad 10 of FIG.
1 is connected. Length a + of this open end stub 11
b is １ ／ of the wavelength (λ _S ) of the unnecessary oscillation frequency. As a result, the open end at the end X of the open end stub 11 is in an open state, and the end Y of the drain pad 10 is in a short circuit state.
The load resistance R _L of FIG. 3 can be reduced. As a result, occurrence of unnecessary oscillation can be suppressed.

[0009]

As described above, according to the present invention, occurrence of unnecessary oscillation can be suppressed.

[Brief description of the drawings]

1A and 1B show an embodiment of a GaAs field effect transistor according to the present invention, wherein FIG. 1A is an overall plan view, FIG. 1B is an enlarged plan view of a portion B of FIG. 1A, and FIG. It is sectional drawing.

FIG. 2 shows a conventional GaAs field effect transistor;
(A) is an overall plan view, (B) is an enlarged plan view of a B portion of (A), and (C) is a cross-sectional view of (B).

FIG. 3 is an equivalent circuit diagram of impedance as viewed from a drain pad 10 of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip 2 ... Semi-insulating GaAs substrate 3 ... N-type GaAs electron transit layer 4 ... Recess area 5 ... Gate electrode 6 ... Source electrode 7 ... Drain electrode 8 ... Gate pad 9 ... Source pad 10 ... Drain pad 11 ... Open end Stub L ... Inductance due to electrode pattern C ... Capacitance due to electrode pattern R ... Negative resistance _RL ... Load resistance

Claims (4)

(57) [Claims] 1. An equivalent circuit viewed from a drain pad, comprising :
A series consisting of conductance, capacitance and negative resistance
A column circuit and a load resistor connected in parallel to the series circuit.
Field-effect transistor that is a tuning circuit
Thus, the length of the wavelength of the drain pad unnecessary oscillation frequency is ４.
Field-effect transistor with an open-end stub directly connected . 2. The method according to claim 1, wherein the load resistance is equal to or less than an absolute value of the negative resistance.
The field effect transistor according to claim 1, being above. 3. The method of claim 2, wherein the unnecessary oscillation frequency is equal to the drain frequency.
The impedance of the impedance seen from the pad becomes negative and
The frequency at which the reactance of the impedance becomes zero
2. The field effect transistor according to claim 1, which is a number. 4. A tuning circuit, comprising : a semi-insulating substrate; and a capacitor provided on the semi-insulating substrate and having a recess region.
A rear transit layer and a gate electrode provided on a recess region of the carrier transit layer.
Pole and the carrier so as to sandwich the recess region of the carrier transit layer.
Source and drain electrodes provided on the rear transit layer
Comprising the door, the drain pad is connected to the drain electrode請
The field-effect transistor according to claim 1.