JPH08274347A - Semiconductor device and circuit using it - Google Patents

Abstract

PURPOSE: To obtain a bicontrol-electrode semiconductor device whose perfor mance can be enhanced at a high frequency and a high output and to obtain an amplifier circuit using the semiconductor device. CONSTITUTION: A second control electrode 54 in a semiconductor device in which a carrier injection electrode 51, a lead-out electrode 52, a first control electrode 53 and the second control electrode 54 are provided on a substrate 1 is connected to the carrier injection electrode 51 directly or by a pattern via a passive element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low noise, a large gain or a high output and a high efficiency, and an amplifier circuit using the semiconductor device.

[0002]

2. Description of the Related Art Instead of a normal single gate field effect transistor (FET) in order to improve circuit characteristics,
A dual-gate FET is used which has two gates between the source and drain and is capable of stable high-gain high-frequency amplification. A conventional dual gate FET is described in, for example, Japanese Patent Application Laid-Open No. 57-181169, and its planar shape is as shown in FIG. 8, and in the case of a dual gate FET having a large gate width, it is as shown in FIG. A flat structure is used. Such a dual gate FET
Conventionally, when used in a mixer circuit, it is often the case that different signals or different series potentials are applied to the two gates.
However, for example, when a dual gate FET is applied to a low noise amplifier, there is a case where a high frequency signal is not given only by giving a series potential to the second gate, and also in a mixer circuit, a high frequency signal is given to the second gate. It may not be.

[0003]

In the case where a high frequency signal is not applied to the second gate as described above, the presence of the second gate causes a capacitance for the wiring which gives a series potential, or the wiring is not provided. Since the complexity increases the circuit area, the cost increases, which is disadvantageous for downsizing. In addition, there is a problem such as the need to use a special package, and further, a pattern having good symmetry cannot be formed due to the wiring of the second gate, resulting in extreme deterioration of characteristics in a high frequency band. In addition, in order to supply a voltage or current to the second gate, in order to suppress an increase in parasitic capacitance,
The pattern shown in Fig. 2 is used. However, when it is used for a high output amplifier in a high frequency band in particular, it is necessary to increase the gate width of the FET, so that a voltage or current is supplied to the second gate. Due to the wiring for this purpose, there was a delay in the phase, and the characteristics were significantly degraded.

An object of the present invention is to solve a wiring problem caused by using a semiconductor device having first and second control electrodes such as a dual gate FET, to obtain a high performance semiconductor device and to provide the semiconductor device of the present invention. It is to obtain a high-performance amplifier circuit using.

[0005]

The above object is to provide a carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and the channel region. In a semiconductor device having a first control electrode and a second control electrode provided above a channel region in order to control a flowing current, one of the first and second control electrodes, which is closer to the carrier injection part, is the first control electrode. When the first control electrode is used, it is achieved by electrically connecting the second control electrode directly to the electrode of the carrier injection part.

In the above semiconductor device, the first
Of the second control electrode and the second control electrode, the one closer to the carrier injection part is the first control electrode, and the electrode of the carrier injection part is the first control electrode.
When one set of the control electrode, the second control electrode, and the electrode of the carrier extraction portion arranged in this order is used as a control unit, the control units arranged in the above order or the reverse order are repeatedly arranged in parallel. This is achieved by forming a pattern and electrically connecting the second control electrode in the control unit directly to the electrode of the carrier injection part.

The second control electrode has a resistance, a capacitance,
The second control electrode is electrically connected to the electrode of the carrier injecting portion via a passive element such as an inductance, or is the second control electrode in the control unit forming the comb pattern, and the resistance, capacitance, inductance It is achieved by being electrically connected to the electrode of the carrier injecting section via a passive element such as.

Further, the second control electrode is connected to the electrode of the carrier injecting portion through a passive element such as resistance, capacitance and inductance in a block including one or more control units forming the comb pattern. By being electrically connected or by having a means for supplying voltage or current through passive elements such as resistors, capacitors, inductances etc. arranged in the control unit forming the comb pattern Alternatively, it can be achieved by having a means for supplying a voltage or a current through a passive element such as a resistor, a capacitor, or an inductance arranged in a block including one or more of the control units.

Alternatively, the first control electrode is arranged so as to face the electrode of the carrier lead-out portion, and the electrode pattern is arranged with respect to the center line of the electrode of the first control electrode-carrier lead-out portion that faces the first control electrode. Are arranged symmetrically, and the semiconductor device is an n-channel,
Since the threshold voltage of the first control electrode has a value higher than the threshold voltage of the second control electrode, the semiconductor device has p
Channel, which is achieved by having the threshold voltage of the first control electrode have a value less than that of the second control electrode.

Alternatively, the first and second control electrodes are arranged above a heterojunction formed by a plurality of different semiconductor layers, and the channel region does not contain ionized impurities and supplies carriers. Further, since the semiconductor layer is arranged above or below the channel region and separated from the channel region, carriers flowing in the channel region when a voltage is applied between the first control electrode and the carrier injection portion are further provided. Each of these is achieved by including an ionized impurity of the same type as the polarity of.

Alternatively, the semiconductor substrate is a GaAs substrate, and the channel region is GaAs, InGaAs, Ga.
The semiconductor layer made of either AsSb or InGaAsSb for supplying the carrier is GaAs or AlGaA.
s, InAlAs, or GaAsP, or the semiconductor substrate is an InP substrate, and the channel region is made of any of InGaAs, GaAsSb, and InGaAsSb, and the semiconductor layer for supplying carriers is It is achieved by comprising InAlAs.

A semiconductor device according to any one of claims 1 to 15, means for inputting a signal to the first control electrode of the semiconductor device, and means for grounding the carrier injection part. And an amplifier circuit can be obtained by configuring a circuit for outputting from the carrier extraction unit.

That is, the carrier injection portion and the extraction portion on the semiconductor substrate, the channel region provided between them,
In a semiconductor device having first and second control electrodes provided on the channel region for controlling a current in the channel region, the second control electrode is previously provided with a passive element such as a resistor, a capacitor, and an inductance. The first object can be achieved by directly connecting to the electrode of the carrier injecting section or by connecting the pattern through a passive element such as resistance, capacitance, or inductance. Here, of the two control electrodes, the one closer to the carrier injecting portion is defined as the first control electrode, but the same applies to the case described below. The connection may be made, in particular, for each unit control finger arranged in a comb shape or for each block of one or more unit control fingers. Further, in order to achieve the above-mentioned object, the semiconductor device of the present invention is configured such that each unit finger, or one or more unit finger blocks,
The semiconductor device is connected to an external second control electrode pad via a passive element such as resistance, capacitance, and inductance. Further, in the semiconductor device, the first control electrode and the electrode of the carrier extraction portion face each other, and the first control The pattern of the semiconductor device is symmetrically arranged with respect to the center line of the electrode of the electrode-carrier extraction part, or the second control electrode is short-circuited to the electrode of the carrier injection part for each unit control finger. Further, in order to obtain a high-performance amplifier circuit, the present invention uses the semiconductor device having the first and second control electrodes as described above.

[0014]

In a high-frequency single-gate FET, a 4-pin package is usually used. In this package, the source electrode to be ground is taken from two opposite sides of a rectangular package, and the source and drain electrodes to be input and output are packaged. This is because it is taken from the other two sides facing each other, and in terms of stability at high frequencies in the GHz band and above, this is a prerequisite that is difficult to avoid in terms of package characteristics. However, in the case of a dual gate FET, since it is a 4-terminal element consisting of a source, a drain, a first gate, and a second gate, in order to obtain stability at high frequencies as described above, 5 or more pins are required. You have to use a special package. Not only is such a package expensive, but the characteristics cannot be improved so much, so that the merit of using the dual gate FET is diminished. Further, the pattern is increased by arranging the electrodes of the element, which causes a problem of high cost and increase of parasitic capacitance.
However, if the potential of the second gate can be fixed by some method, it can be regarded as a three-terminal element in appearance, and a single-gate type package can be used.

As a method of fixing the potential of the second gate, there is a method of directly connecting the second gate to the source electrode as shown in FIG. In FIG. 10, simple straight line intersections are not electrically connected, and black circles at the intersections are electrically connected. Further, in FIG. 10 described above, the case where there are four unit gate fingers is described corresponding to FIG. 1,
The same applies to the following. In this case, the pattern becomes very simple, so that the parasitic capacitance hardly occurs and the element characteristics become good. However, there is a problem in that the output impedance becomes too high and oscillation easily occurs.

Next, as shown in FIG. 10C, there is a method of connecting the second gate to the source electrode via a resistor. Also in this case, since the pattern is very simple, the parasitic capacitance hardly occurs and the element characteristics become good. Further, there is an advantage that the resistance stabilizes and makes oscillation difficult. However, losses such as output power and gain due to resistance also occur. The magnitude of the resistance in the case of the above pattern can be controlled also by the length and width of the resistance used, but instead of connecting the second gate to the source electrode via the resistance with only a single finger, as shown in FIG. It can also be controlled by bundling several fingers as shown, and then connecting the fingers to the source electrode via a resistor. In the figure, the case of bundling two wires is described, but in this case, the pattern becomes slightly more complicated than the case where each single finger is connected to the source electrode via a resistor, but the resistance value can be made large. There are merits. Further, as shown in FIGS. 11 (a) and 11 (b), it may be installed on the source electrode through a capacitance, an inductance, a diode or the like instead of the resistance.

When independently controlling the second gate potential,
As shown in FIG. 10 (d) or FIG. 11 (d), there is a method of connecting a pattern for each finger through a resistor and then connecting the pattern to the second gate pad. In this case, there is a problem that the parasitic capacitance is easily attached because the pattern is not as simple as the above pattern. However, in the case of a pattern having many gate fingers, the phase generated in the conventional pattern as shown in FIG. Problems such as delay can be reduced.

Further, a first gate electrode for inputting a high frequency signal and a drain electrode for outputting a high frequency signal are arranged to face each other, and the FET pattern is symmetrical with respect to the center line of the first gate-drain electrode. When they are arranged, useless reflection and interference of high frequency signals are less likely to occur, and therefore characteristic deterioration at high frequencies is less likely to occur.

When an ideal dual gate FET is used in the amplifier circuit, the circuit performance is improved by the effect of reducing the feedback capacitance and drain conductance due to the presence of the second gate. However, when the conventional dual-gate FET is used, the characteristics are significantly deteriorated particularly in applications such as high frequency and high output, and in some cases, the performance may be worse than when the single-gate FET is used. When the dual gate FET of the present invention is used in this amplifier circuit, the amplifier circuit has good performance at high frequency and high output, resulting in an excellent performance circuit.

[0020]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a view showing an amplifier circuit of a second embodiment using the semiconductor device, and FIG. 3 is a third embodiment of the present invention. FIG. 4 is a diagram showing a high output amplifier, FIG. 4 is a diagram showing a circuit of the high output amplifier, FIG. 5 is a diagram showing a high output amplifier which is a fourth embodiment of the present invention, and FIG. 6 is a circuit of the high output amplifier. It is a figure. As a description of the material of the present invention, AlGaAs is Ga
In in which some of the Ga atoms in As are replaced by Al, In
GaAs means one in which some of the Ga atoms in GaAs are replaced by In, and InAlAs means that in which some of the Al atoms in AlAs are replaced by In.

First Embodiment A first embodiment of a semiconductor device according to the present invention is shown in a plan view in FIG. 1, and a sectional view taken along the line AA ′ of FIG. 1 is shown in FIG. First, molecular beam epitaxy (MBE) is performed on the semi-insulating GaAs substrate 1.
Undoped GaAs buffer layer (thickness: 500 n
m) 2, undoped InGaAs channel layer (In composition:
0.25, thickness: 8 nm) 3, undoped AlGaAs spacer layer (Al composition: 0.25, thickness: 2 nm) 4, n-Al
GaAs carrier supply layer (Al composition: 0.25, thickness: 15
nm, Si concentration: 2 × 10 ¹⁸ / cm ³ ) 5, undoped Al
GaAs barrier layer (Al composition: 0.25, thickness: 10 nm)
6, undoped GaAs cover layer (thickness: 50 nm) 7,
Undoped AlGaAs etching stopper layer (Al composition:
0.25, thickness: 3 nm) 8 is grown, and finally n-Ga
As cap layer (Si concentration: 7 × 10 ¹⁸ / cm ³ , thickness: 1
00 nm) 9 is deposited.

After the region including the channel layer 3 is etched into a mesa type to separate elements (the etched portion is not shown), an insulating film is vapor-deposited from SiO.
The source electrode 51, which is an electrode of the carrier injection portion, and the drain electrode 52, which is an electrode of the carrier extraction portion, are formed by the lift-off method described below. First, an opening is formed in the insulating film by a normal photolithography process,
Use a lift-off mask. The opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. Furthermore, the n-GaAs cap layer 9 is etched by wet etching to about 40 nm. AuGe / Mo / Au is used as the source and drain electrode materials, and heat treatment is performed at 400 ° C. for 5 minutes in a nitrogen atmosphere after the material deposition.

Next, a photoresist pattern having an opening for the second gate electrode which is the second control electrode is formed by the same photolithography process, and an opening is provided in the insulating film by dry etching. Then, the n-GaAs cap layer 9 is removed by dry etching. At this time, side etching is performed by isotropic etching to remove a region larger than the opening by etching. Next, a second gate electrode 54 having a gate length of 0.5 μm is formed on the undoped AlGaAs layer 8 by lift-off. Mo / Al is used as the gate electrode material.

Next, a new resist is applied to form a photoresist pattern having an opening for the first gate electrode which is the first control electrode, and an opening is provided in the insulating film by dry etching. And dry etching is used.
-Remove the GaAs cap layer 9. At this time, side etching is performed by isotropic etching to remove a region larger than the opening by etching. Then, the gate length is 0.3 μm
The first gate electrode 53 of is formed on the undoped AlGaAs barrier layer 6 by lift-off. Mo / Al is used as the gate electrode material. Thus, the semiconductor device having the structure shown in FIG. 2 was realized.

The semiconductor device according to this embodiment has a source resistance of 0.42 Ω · mm, a gate resistance of 0.3 Ω · mm,
The saturated output was 33 dBm at 1.9 GHz, the gain at the output 1 dB compression point was 19 dB, and the power added efficiency was 60%, showing high performance.

The conditions in this embodiment may be changed as follows. Regarding the epitaxial crystal growth in the manufacturing process, although the thickness of the undoped AlGaAs spacer layer 4 was set to 2 nm in this embodiment, good results were obtained in the range of 1 to 4 nm. Further, the concentration of ionized impurities in the n-AlGaAs carrier supply layer 5 is not limited to the above, but may be 0.3 × 6
Good results are obtained in the range of × 10 ¹⁸ / cm ³ .
Furthermore, the conditions in this embodiment may be changed as follows. That is, the material of the source electrode and the drain electrode or the material of the gate electrode is not limited to the above, and other materials such as Al, Pt / Ti / Pt / Au are used as the material of the gate electrode.
As a material for the source and drain electrodes, a non-alloy ohmic material such as Ti / Au may be used. The same result can be obtained by using a method capable of controlling the growth in atomic layer units, such as a metal organic chemical vapor deposition (MOCVD) method, instead of the MBE method as the epitaxial crystal growth method in the manufacturing process. Further, the n-GaAs cap layer 9 is not limited to GaAs but may be a substance that easily makes ohmic contact, such as InGaAs. Further, the undoped AlGaAs layer 6 and the undoped GaAs cover layer 7 immediately below the gate electrode are 1 × so that the breakdown voltage is not reduced.
You may use n-AlGaAs etc. of 10 < ¹⁷ > / cm < ³ > or less. In addition, ion implantation or the like may be used together to reduce parasitic resistance. Although the HEMT structure in which the channel and the ion impurity layer are spatially separated is used in the present embodiment, the present invention is not limited to this, and the carrier HE layer has a reverse HEMT on the substrate side and the channel is arranged on both sides. The same effect can be obtained with other crystal structures such as a double hetero HEMT that has been used and a HIGFET in which the channel is doped with ionized impurities. Further, not only the heterojunction FET but also a homojunction FET or an FET formed by ion implantation
Similar results can be obtained with. Further, although an example of the N-channel semiconductor device is shown in this embodiment, the same applies to the case of the P-channel semiconductor device. In this case, a P-type material such as carbon, beryllium, or magnesium may be used as the ionized impurities. The material is not limited to the GaAs / AlGaAs / InGaAs system used in this embodiment,
The characteristics are further improved by using an Sb-based material such as GaAsSb or InGaAsSb. Needless to say, the same effect can be obtained by using a material such as InP as the substrate material. At this time, the characteristics are further improved by using InGaAs as the channel layer and InAlAs as the carrier supply layer.

Second Embodiment A high power amplifier using a dual gate FET as shown in the above embodiment is used as a second embodiment, and its circuit diagram is shown in FIG.
Shown in Dual gate F as described in the first embodiment
The ET 100 is formed on a semiconductor substrate together with a matching circuit using a resistor 107, a capacitor 108, and an inductance 109. The high-power amplifier thus obtained has an output power of 30 dBm, a power addition efficiency of 60%, and a small-signal input / output VSWR2 under the conditions that the drain voltage 106 of the FET 100 is 3 V, the input signal power is 10 dBm, and the frequency is 1.9 GHz. The following good performances were obtained.

Third Embodiment FIG. 4 is a plan view of a high power amplifier according to a third embodiment of the present invention.
5 and its circuit diagram is shown in FIG. The dual gate FET 100 as described in the first embodiment is formed on the semiconductor substrate together with the matching circuit using the resistor 107, the capacitor 108 and the inductance 109. The second gate is connected to the source electrode 51 via the resistor 55 in each unit finger as shown in FIG. Although only four gate fingers are shown in this plan view for simplification, 126 gate fingers are used in this embodiment. The high output amplifier thus obtained has an output power of 28 dBm, a power added efficiency of 55%, and a small signal input / output VSWR1 under the conditions that the drain voltage 106 of the FET 100 is 3 V, the input signal power is 10 dBm, and the frequency is 1.9 GHz. Good performance of less than 0.5 was obtained. Since the resistor 55 is present in the above circuit configuration, the output and the efficiency are slightly deteriorated as compared with the second embodiment, but the oscillation of the element is less likely to occur, so that the resistor 107, the capacitor 108, and the inductance in the matching circuit are less likely to occur. The restriction on the value of 109 is small, and the circuit design is easy.

Fourth Embodiment FIG. 6 is a plan view of a high power amplifier according to a fourth embodiment of the present invention.
7 and a circuit diagram thereof is shown in FIG. The dual gate FET 100 described in the first embodiment is formed on a semiconductor substrate together with a matching circuit using a resistor 107, a capacitor 108, and an inductance 109. The second gate is shown in FIG.
As shown in, each unit finger is connected to the second gate potential supply pad 58 via the resistor 55. Although only four gate fingers are shown in this plan view for simplification, 126 gate fingers are used in this embodiment. The high-power amplifier thus obtained has the drain voltage 106 of the FET 100 and the second
Under the conditions that the gate voltage 105 is 3 V and 1 V, the input signal power is 10 dBm, and the frequency is 1.9 GHz, the output power is 31 dBm, the power added efficiency is 62%, and the input / output VSWR of the small signal is 1.8 or less, which is good performance. It was

In each of the second to fourth embodiments, the conditions may be as follows. In this embodiment, an example of a so-called monolithic IC in which the matching circuit is on the same substrate has been shown. However, even if the performance of the hybrid IC is slightly degraded, that is, even if the matching circuit is not on the same substrate, Good results are obtained. Further, although the circuit in which the frequency band is 1.9 GHz is described, good characteristics are obtained in other frequency bands by changing the matching circuit. The number of gate fingers is not limited to this, and may be set according to the required output power. In addition, operating current and operating voltage are smaller,
For example, good characteristics were obtained even when low power consumption operation of a car phone or a mobile phone was required. In this case, the required cell size could be reduced to half or less in order to obtain the same characteristics that could be realized when the conventional element was used.
This is because the element obtained by the present invention has better performance than the conventional element, so that a high-performance amplifier can be obtained even if the circuit is configured with a small number of elements. Further, the semiconductor device of the present invention may be used for other circuits.

Although the resistor 55 is used in the third and fourth embodiments, the present invention is not limited to this, and a passive element such as a capacitor, an inductance, or a diode may be used.
Further, in each of these embodiments, a resistor is used for each unit finger, but it is also possible to bundle several unit fingers and then connect them via a resistor or the like.

Fifth Embodiment FIG. 6 is a plan view of a high power amplifier according to a third embodiment of the present invention.
And the circuit diagram is shown in FIG. The dual gate FET 100 described in the first embodiment is used as a resistor 107 and a capacitor 1.
It is formed on a semiconductor substrate together with a matching circuit using 08 and the inductance 109. Second gate electrode 5
As shown in FIG. 6, each unit finger 4 is connected to a second potential supply pad 58 via a resistor 55. Although only four gate fingers are shown in this plan view for simplification, a 126 gate finger with a finger length of 250 μm was used in this example. The high power amplifier thus obtained is FET1
00 has a drain voltage 106 and a second gate voltage 105
Under the conditions of 3V and 1V, input signal power of 10 dBm and frequency of 1.9 GHz, output power of 31 dBm, power added efficiency of 65%, small signal input / output VSWR1.
Good performance of 8 or less could be obtained.

[0033]

As described above, the semiconductor device and the circuit using the same according to the present invention are provided between the carrier injection part and the carrier extraction part provided in a desired region of the semiconductor substrate and the carrier injection part and the extraction part. In the semiconductor device having a channel region provided and a first control electrode and a second control electrode provided above the channel region for controlling a current flowing through the channel region, the first and second semiconductor devices are provided.
Of the control electrodes, when the one closer to the carrier injection part is the first control electrode, the second control electrode is directly electrically connected to the electrode of the carrier injection part.
A low-cost semiconductor device having a simple pattern, small size, and good performance can be obtained, and the performance of a high-output amplifier or the like using the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a plan structural view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

FIG. 3 is a circuit diagram of an amplifier shown as a second embodiment using the above embodiment.

FIG. 4 is a plan view of a high power amplifier according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of the high-power amplifier of the above embodiment.

FIG. 6 is a plan view of a high power amplifier according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of the high output amplifier according to the embodiment.

FIG. 8 is a plan view showing a conventional dual gate field effect transistor.

FIG. 9 is a plan view of a conventional dual gate field effect transistor having a large gate width.

FIG. 10 is an equivalent circuit diagram of a semiconductor device showing an operation of the present invention, and FIGS. 10A to 10D are diagrams showing a method of connecting a second control electrode and a carrier injection electrode, respectively.

FIG. 11 is an equivalent circuit diagram of a semiconductor device showing the operation of the present invention, and FIGS. 11A to 11D are diagrams showing a method of connecting a second control electrode and a carrier injection electrode, respectively.

[Explanation of symbols]

 1 ... Semiconductor substrate 3 ... Channel region 51 ... Carrier injection part electrode 52 ... Carrier extraction part electrode 53 ... First control electrode 54 ... Second control electrode 55, 107 ... Resistor 56, 108 ... Capacitance 57, 109 ... Inductance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Nakamura 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Metropolitan Research Center, Hitachi, Ltd. (72) Satoshi Tanaka 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Center

Claims (16)

[Claims] 1. A carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and a current flowing through the channel region, In a semiconductor device having a first control electrode and a second control electrode provided above a channel region, when one of the first and second control electrodes closer to the carrier injection part is the first control electrode, A semiconductor device, wherein the second control electrode is directly electrically connected to the electrode of the carrier injection part. 2. A carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and a current flowing through the channel region, In a semiconductor device having a first control electrode and a second control electrode provided above a channel region, one of the first and second control electrodes that is closer to the carrier injection portion is the first control electrode,
When one set of the carrier injection part electrode, the first control electrode, the second control electrode, and the carrier extraction part electrode arranged in this order is used as a control unit, the control units arranged in the above order or the reverse order are , Forming a comb-shaped pattern repeatedly arranged in parallel, and forming a second pattern in the control unit.
A semiconductor device, wherein a control electrode is directly electrically connected to an electrode of the carrier injection part. 3. The semiconductor according to claim 1, wherein the second control electrode is electrically connected to the electrode of the carrier injecting portion via a passive element such as resistance, capacitance, or inductance. apparatus. 4. The second control electrode is a second control electrode in a control unit forming the comb pattern, and is electrically connected to an electrode of the carrier injecting portion via a passive element such as resistance, capacitance, or inductance. 3. The semiconductor device according to claim 2, wherein the semiconductor devices are electrically connected. 5. The second control electrode is connected to an electrode of the carrier injection part via a passive element such as resistance, capacitance, and inductance in a block including one or more control units forming the comb pattern. The semiconductor device according to claim 2, wherein the semiconductor device is electrically connected. 6. The second control electrode has means for supplying a voltage or a current through a passive element such as a resistor, a capacitor or an inductance arranged in the control unit forming the comb pattern. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. 7. The second control electrode has means for supplying a voltage or current through a passive element such as a resistor, a capacitor or an inductance arranged in a block including one or more of the control units. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. 8. The first control electrode is disposed so as to face the electrode of the carrier extraction portion, and the electrode is disposed with respect to the center line of the opposing first control electrode-electrode of the carrier extraction portion. 8. The semiconductor device according to claim 1, wherein the patterns are arranged symmetrically. 9. The semiconductor device according to claim 1, wherein the semiconductor device is an n-channel device, and the threshold voltage of the first control electrode is larger than the threshold voltage of the second control electrode. The semiconductor device according to any one of 1. 10. The semiconductor device is a p-channel,
9. The semiconductor device according to claim 1, wherein the threshold voltage of the first control electrode has a value smaller than that of the second control electrode. 11. The first and second control electrodes are provided on a heterojunction formed by a plurality of heterogeneous semiconductor layers,
It is arranged, It is characterized by the above-mentioned.
0. The semiconductor device according to any one of 0. 12. The channel region does not contain ionized impurities, and a semiconductor layer for supplying carriers is arranged above or below the channel region and spatially separated from the channel region. Claim 1 characterized by the above-mentioned.
Alternatively, the semiconductor device according to claim 2. 13. The method according to claim 1, wherein the channel region contains ionized impurities of the same type as the polarities of the carriers flowing in the channel region when a voltage is applied between the first control electrode and the carrier injection part. Item 2 or claim 12
13. The semiconductor device according to claim 1. 14. The semiconductor substrate is a GaAs substrate,
The channel region is composed of GaAs, InGaAs, GaAsSb, I.
The semiconductor layer made of any one of nGaAsSb for supplying the carrier is GaAs, AlGaAs, InAl.
3. The semiconductor device according to claim 1, wherein the semiconductor device is made of either As or GaAsP. 15. The semiconductor substrate is an InP substrate,
The channel regions are InGaAs, GaAsSb, and InGaAs.
3. The semiconductor device according to claim 1, wherein any one of Sb and the semiconductor layer for supplying the carrier is made of InAlAs. 16. A semiconductor device according to claim 1, a means for inputting a signal to a first control electrode of the semiconductor device, and a means for grounding the carrier injection part. And an amplifier circuit comprising: and a circuit for outputting from the carrier extraction unit.