JPH0216587B2 - - Google Patents
Info
- Publication number
- JPH0216587B2 JPH0216587B2 JP57115114A JP11511482A JPH0216587B2 JP H0216587 B2 JPH0216587 B2 JP H0216587B2 JP 57115114 A JP57115114 A JP 57115114A JP 11511482 A JP11511482 A JP 11511482A JP H0216587 B2 JPH0216587 B2 JP H0216587B2
- Authority
- JP
- Japan
- Prior art keywords
- gallium arsenide
- substrate
- gaas
- aluminum gallium
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 34
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004338 Dichlorodifluoromethane Substances 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 2
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 2
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- TXFYZJQDQJUDED-UHFFFAOYSA-N germanium nickel Chemical compound [Ni].[Ge] TXFYZJQDQJUDED-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関する。特
に、ヒ化ガリウム(GaAs)基板に形成されるキ
ヤパシタ及び/または抵抗の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a capacitor and/or resistor formed on a gallium arsenide (GaAs) substrate.
半導体装置においては、ダイオード、トランジ
スタ等の能動素子とともに、抵抗、キヤパシタ等
の受動素子が欠くことのできない構成要素である
ことは周知である。また、これらの有する値、す
なわち、抵抗値R(Ω)、静電容量C(F)は、それぞ
れ、下記に示す(1)式及び(2)式により規定される。
It is well known that passive elements such as resistors and capacitors are indispensable components in semiconductor devices, along with active elements such as diodes and transistors. Further, these values, that is, the resistance value R (Ω) and the capacitance C (F) are defined by the following equations (1) and (2), respectively.
R=ρL/S ……(1) 但し、上記(1)式において、 ρは抵抗率(Ωm)であり、 Sは断面積(m2)であり、 Lは長さ(m)である。 R=ρL/S...(1) However, in the above equation (1), ρ is resistivity (Ωm), S is cross-sectional area (m 2 ), and L is length (m).
また、 C=εS/d ……(2) 但し、上記(2)式において、 εは誘電率(F/m)であり、 dは極間距離(m)であり、 Sは電極の断面積(m2)である。 Also, C=εS/d...(2) However, in the above formula (2), ε is the dielectric constant (F/m), d is the distance between electrodes (m), and S is the cross-sectional area of the electrodes. (m 2 ).
従来技術において、上記キヤパシタ、抵抗等の
受動素子は、半導体チツプ表面に平面的に形成さ
れていた。すなわち、それぞれの素子がそれぞれ
の専用面積を必要としていた。また、キヤパシタ
を構成する誘電体としては、二酸化シリコンま
た、窒化シリコンが、主として使用されていた。 In the prior art, passive elements such as capacitors and resistors are formed planarly on the surface of a semiconductor chip. That is, each element required its own dedicated area. Furthermore, silicon dioxide or silicon nitride has been mainly used as the dielectric material constituting the capacitor.
ところが、昨今の高度に集積化された半導体装
置においては、これらの受動素子が占有する面積
が看過し難い大きさとなるため、集積度の向上を
妨げる原因となつている。そこで、キヤパシタ、
抵抗等の受動素子を立体的な構造となし、もし可
能であればそれぞれの専用面積を必要とせず、他
の素子と同一の領域に立体的な構造として形成
し、さらに、製造工程数の低減にも有効に寄与し
うる構造を有する半導体装置に対する要請が高ま
つている。
However, in today's highly integrated semiconductor devices, the area occupied by these passive elements is so large that it is hard to overlook, which is a cause of hindering the improvement of the degree of integration. Therefore, Capacita,
Create a three-dimensional structure for passive elements such as resistors, and if possible, do not require a dedicated area for each element, but form the three-dimensional structure in the same area as other elements, and further reduce the number of manufacturing steps. There is an increasing demand for a semiconductor device having a structure that can effectively contribute to the development of semiconductor devices.
また、近年、ヒ化ガリウム(GaAs)は易動度
が高いので、高速半導体装置、特に高速FET、
HEMT等の材料として、高く評価されるように
なつてきている。したがつて、半導体装置を構成
するキヤパシタ等の受動素子もヒ化ガリウム
(GaAs)基板上に形成することが必要になつて
きた。 In recent years, gallium arsenide (GaAs) has also been used in high-speed semiconductor devices, especially high-speed FETs, due to its high mobility.
It is becoming highly valued as a material for HEMTs, etc. Therefore, it has become necessary to form passive elements such as capacitors that constitute a semiconductor device on a gallium arsenide (GaAs) substrate.
従来、キヤパシタを構成する誘電体には、上記
のとうり、二酸化シリコン、または、窒化シリコ
ンが一般に使用されているが、これらの材料とヒ
化ガリウム(GaAs)とは格子定数が極めて大幅
に相違するため、ヒ化ガリウム(GaAs)基板上
に二酸化シリコン層、または、窒化シリコン層よ
りなる誘電体層を形成すると、誘電体層に歪みが
生じ、これがリーク電流の原因となつて半導体装
置の信頼性が低下するので、二酸化シリコン、ま
たは、窒化シリコンをヒ化ガリウム(GaAs)基
板上に形成するキヤパシタを構成する誘電体とし
ては困難である。 Conventionally, as mentioned above, silicon dioxide or silicon nitride has generally been used as the dielectric material constituting the capacitor, but these materials and gallium arsenide (GaAs) have extremely different lattice constants. Therefore, when a dielectric layer made of silicon dioxide or silicon nitride is formed on a gallium arsenide (GaAs) substrate, distortion occurs in the dielectric layer, which causes leakage current and reduces the reliability of semiconductor devices. Since silicon dioxide or silicon nitride has low properties, it is difficult to use silicon dioxide or silicon nitride as a dielectric material for forming a capacitor formed on a gallium arsenide (GaAs) substrate.
本発明の目的は、この欠点を解消することにあ
り、ヒ化ガリウム(GaAs)基板上に、抵抗、キ
ヤパシタ等の受動素子を形成することにある。特
に、立体構造を有し、他の素子と同一の領域に形
成されてチツプ表面に専用面積を必要とすること
がなく、しかも、キヤパシタを構成する誘電体層
または抵抗を構成する誘電体層に歪みが発生する
ことがなく、信頼性の高いキヤパシタまたは抵抗
を形成することにある。 An object of the present invention is to eliminate this drawback, and to form passive elements such as resistors and capacitors on a gallium arsenide (GaAs) substrate. In particular, it has a three-dimensional structure, is formed in the same area as other elements, does not require a dedicated area on the chip surface, and is suitable for use in dielectric layers constituting capacitors or dielectric layers constituting resistors. The purpose is to form a highly reliable capacitor or resistor without distortion.
上記の目的は、半絶縁性または絶縁性のヒ化ガ
リウム(GaAs)基板1の一方の主面上に、アル
ミニウムガリウムヒ素層2を形成する工程と、前
記の基板1を、他方の主面から選択的にエツチン
グして、前記のアルミニウムガリウムヒ素層2が
露出した時点でエツチングを停止して開口3を形
成する工程と、この開口3を埋めて前記の基板1
の他方の主面上に導出される背面電極4を形成す
る工程と、前記のアルミニウムガリウムヒ素層2
上に、前記の開口3に対応して、上部電極5を形
成する工程とを含んでいる半導体装置の製造方法
によつて達成される。
The above purpose is to form an aluminum gallium arsenide layer 2 on one main surface of a semi-insulating or insulating gallium arsenide (GaAs) substrate 1, and to separate the substrate 1 from the other main surface. A step of selectively etching and stopping the etching when the aluminum gallium arsenide layer 2 is exposed to form an opening 3; and a step of filling the opening 3 to form the substrate 1.
a step of forming a back electrode 4 led out on the other main surface of the aluminum gallium arsenide layer 2;
This is achieved by a method of manufacturing a semiconductor device, which includes the step of forming an upper electrode 5 corresponding to the opening 3 above.
なお、前記のアルミニウムガリウムヒ素を絶縁
性物質とすればキヤパシタを構成することがで
き、また、前記のアルミニウムガリウムヒ素を導
電性物質とすれば抵抗を構成することができる。 Note that if the aluminum gallium arsenide is used as an insulating material, a capacitor can be constructed, and if the aluminum gallium arsenide is used as a conductive material, a resistor can be constructed.
従来技術において、ヒ化ガリウム(GaAs)基
板の上下面間に貫通孔を形成し、その貫通孔を通
してアース線を基板裏面のヒートシンク等に接続
して立体構造となす、いわゆる、貫通孔式
(viahole式)接地方式が実用化されているが、こ
れを拡張して、キヤパシタ、抵抗等を同様の立体
構造となすには、基板に対し、表面に所望の厚さ
を有する領域を残して裏面からエツチング法等を
使用して、基板に開口を開け、その開口に導電性
物質を充填する方法を使用して、基板表面に所望
の厚さに残留する領域に不純物を含有させておけ
ば抵抗が得られ、一方、不純物を含有させず絶縁
性のままに保てばキヤパシタが得られる。
In the conventional technology, a through hole is formed between the upper and lower surfaces of a gallium arsenide (GaAs) substrate, and a ground wire is connected to a heat sink on the back side of the substrate through the through hole to create a three-dimensional structure. The grounding method (formula) has been put into practical use, but in order to expand this and create a similar three-dimensional structure for capacitors, resistors, etc., it is necessary to Resistance can be increased by making an opening in the substrate using an etching method or the like and filling the opening with a conductive material to contain impurities in a region that remains on the substrate surface to a desired thickness. On the other hand, if it is kept insulating without containing impurities, a capacitor can be obtained.
ところが、抵抗にせよ、キヤパシタにせよ、そ
の値が厳密に制御される必要があり、そのために
は上記のイオン注入等の不純物導入や、所望の厚
さを残して基板に開口を形成するためのエツチン
グ等を正確に制御しなくてはならないが、現在の
技術水準では上記のような正確な制御が必ずしも
容易ではない。 However, whether it is a resistor or a capacitor, its value needs to be strictly controlled, and for this purpose, it is necessary to introduce impurities such as the above-mentioned ion implantation, and to form an opening in the substrate while leaving a desired thickness. Etching etc. must be accurately controlled, but with the current state of the art, such accurate control is not necessarily easy.
そこで、本発明の発明者は、ヒ化ガリウム
(GaAs)よりなる基板上に、このヒ化ガリウム
(GaAs)とはエツチングレートの異なる他の化
合物半導体であるアルミニウムガリウムヒ素
(AlGaAs)よりなる層を形成したのち、上記の
基板の裏面からエツチングをなし、このとき、こ
のエツチングの進行を、上記の基板をなすヒ化ガ
リウム(GaAs)と上記他の化合物半導体層をな
すアルミニウムガリウムヒ素(AlGaAs)とのエ
ツチングレートの差を利用して上記他の化合物半
導体層(アルミニウムガリウムヒ素(AlGaAs)
層)の下面にて止め、ヒ化ガリウム(GaAs)よ
りなる基板の裏面に設けられたこの開口には、ヒ
ートシンク等と兼用される背面配線を伸延してお
き、一方、上記の他の化合物半導体層をなすアル
ミニウムガリウムヒ素(AlGaAs)層の厚さを正
確に制御しておけば、抵抗、キヤパシタ等の値を
正確に制御できるので、容易に立体構造を有する
受動素子を形成することができるとの着想にもと
づき、この着想を具体化して、本発明を完成した
ものである。 Therefore, the inventor of the present invention created a layer made of aluminum gallium arsenide (AlGaAs), which is another compound semiconductor with a different etching rate from gallium arsenide (GaAs), on a substrate made of gallium arsenide (GaAs). After the formation, etching is performed from the back side of the above substrate, and at this time, the progress of this etching is controlled between the gallium arsenide (GaAs) forming the above substrate and the aluminum gallium arsenide (AlGaAs) forming the above other compound semiconductor layer. The other compound semiconductor layer (aluminum gallium arsenide (AlGaAs)) is
This opening is provided on the back side of the substrate made of gallium arsenide (GaAs), and the back side wiring, which also functions as a heat sink, etc., is extended through the opening. By accurately controlling the thickness of the aluminum gallium arsenide (AlGaAs) layer, it is possible to accurately control the values of resistance, capacitor, etc., making it possible to easily form passive elements with three-dimensional structures. Based on this idea, the present invention was completed by embodying this idea.
すなわち、半絶縁性のヒ化ガリウム(GaAs)
基板上に、ヒ化ガリウム(GaAs)と格子定数の
マツチングが可能であるアルミニウムガリウムヒ
素(AlGaAs)層を形成することゝし、また、基
板のエツチング法としてジクロロジフルオロメタ
ン(CCl2F2)等を反応性物質としてなすリアク
テイブスパツタエツチング等を使用することゝし
て、本発明を完成したものである。 i.e. semi-insulating gallium arsenide (GaAs)
An aluminum gallium arsenide (AlGaAs) layer whose lattice constant can be matched with gallium arsenide (GaAs) is formed on the substrate, and dichlorodifluoromethane (CCl 2 F 2 ) or the like is used as an etching method for the substrate. The present invention has been completed by using reactive sputter etching, etc., which uses a material as a reactive substance.
以下、図面を参照しつゝ、本発明の一実施例に
係る半導体装置の製造方法について説明し、本発
明の構成と特有の効果とを明らかにする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings, and the structure and unique effects of the present invention will be clarified.
一例として、半絶縁性のヒ化ガリウム
(GaAs)よりなる基板上に立体構造を有するキ
ヤパシタを形成する工程について述べる。 As an example, a process of forming a capacitor having a three-dimensional structure on a substrate made of semi-insulating gallium arsenide (GaAs) will be described.
第1図参照
厚さ400μm程度の半絶縁性ヒ化ガリウム
(GaAs)基板1上に、有機金属気相成長法(メ
タルオーガニツク−CVD法)または分子線エピ
タキシヤル結晶成長法(MBE法)等を使用して、
半絶縁性アルミニウムガリウムヒ素(Al0.3Ga0.7
As)よりなる層2を所望の厚さに形成する。こ
の層2の厚さは、製造すべき抵抗の値、キヤパシ
タの容量等によつて決定される。Refer to Figure 1. On a semi-insulating gallium arsenide (GaAs) substrate 1 with a thickness of about 400 μm, metal organic vapor phase epitaxy (metal organic CVD method) or molecular beam epitaxial crystal growth method (MBE method), etc. using,
Semi-insulating aluminum gallium arsenide (Al 0.3 Ga 0.7
A layer 2 consisting of As) is formed to a desired thickness. The thickness of this layer 2 is determined by the value of the resistor to be manufactured, the capacitance of the capacitor, etc.
なお、この半絶縁性アルミニウムガリウムヒ素
(AlGaAs)層2下には、必要に応じてn型アル
ミニウムガリウムヒ素層(図示せず)を配設して
もよい。 Note that an n-type aluminum gallium arsenide layer (not shown) may be provided under the semi-insulating aluminum gallium arsenide (AlGaAs) layer 2 if necessary.
第2図参照
前記の半絶縁性ヒ化ガリウム(GaAs)基板1
を裏面から機械的及び/または化学的に研磨し、
この半絶縁性ヒ化ガリウム(GaAs)基板1の厚
さを10〜300μm所望の値に設定する。See Figure 2 The semi-insulating gallium arsenide (GaAs) substrate 1
mechanically and/or chemically polished from the back side,
The thickness of this semi-insulating gallium arsenide (GaAs) substrate 1 is set to a desired value of 10 to 300 μm.
上記の半絶縁性ヒ化ガリウム(GaAs)基板1
の下(裏)面から、アルミニウムガリウムヒ素
(Al0.3Ga0.7As)層2の下面に達する開口3を形
成する。この工程は、ジクロロジフルオロメタン
(CCl2F2)等を反応性ガスとなすリアクテイブス
パツタエツチング法を使用して実行できる。この
とき、ヒ化ガリウム(GaAs)とアルミニウムガ
リウムヒ素(Al0.3Ga0.7As)との上記エツチング
法におけるエツチングレートの比は200:1程度
であるから、ヒ化ガリウム(GaAs)のみの選択
的エツチングが可能となる。 The above semi-insulating gallium arsenide (GaAs) substrate 1
An opening 3 reaching the lower surface of the aluminum gallium arsenide (Al 0.3 Ga 0.7 As) layer 2 is formed from the lower (back) surface. This step can be carried out using a reactive sputter etching method using dichlorodifluoromethane (CCl 2 F 2 ) or the like as the reactive gas. At this time, since the etching rate ratio of gallium arsenide (GaAs) and aluminum gallium arsenide (Al 0.3 Ga 0.7 As) in the above etching method is about 200:1, selective etching of only gallium arsenide (GaAs) is possible. becomes possible.
第3図参照
上記半絶縁性ヒ化ガリウム(GaAs)基板1の
下面に、真空蒸着法を使用して開口3にまで伸延
する金ゲルマニウム(AuGe)よりなるヒートシ
ンク兼背面電極4を形成し、さらに、半絶縁性ア
ルミニウムガリウムヒ素(Al0.3Ga0.7As)層2の
上面にスパツタ成長法とフオトリソグラフイー法
とを使用して、アルミニウム(Al)または金
(Au)、金ゲルマニウム(AuGe)、金ゲルマニウ
ムニツケル(AuGeNi)等よりなる上部電極・配
線5を形成し、本発明の一実施例に関する半導体
装置の立体構造を有するキヤパシタを完成する。
かゝる上部電極・配線5はかゝる半絶縁性ヒ化ガ
リウム(GaAs)基板1の上面に選択的に形成さ
れたn型ヒ化ガリウム(GaAs)層(図示せず)
に形成される半導体素子(GaAsFET)のソー
ス、ドレインあるいはゲートの各電極のうちから
選択された電極に接続される。Refer to Fig. 3 A heat sink/back electrode 4 made of gold germanium (AuGe) extending to the opening 3 is formed on the lower surface of the semi-insulating gallium arsenide (GaAs) substrate 1 using a vacuum evaporation method, and further , aluminum ( Al ) or gold ( Au ), gold germanium (AuGe), gold, or An upper electrode/wiring 5 made of germanium nickel (AuGeNi) or the like is formed to complete a capacitor having the three-dimensional structure of a semiconductor device according to an embodiment of the present invention.
The upper electrode/wiring 5 is an n-type gallium arsenide (GaAs) layer (not shown) selectively formed on the upper surface of the semi-insulating gallium arsenide (GaAs) substrate 1.
The electrode is connected to a selected one of the source, drain, and gate electrodes of a semiconductor device (GaAsFET) formed in the semiconductor device.
上記の工程において、キヤパシタの静電容量は
当然のことながら、半絶縁性アルミニウムガリウ
ムヒ素(Al0.3Ga0.7As)層2の厚さと、上部電極
5、下部電極4との対向面積に依存して決定され
る。一例として、上部電極5と下部電極4との対
向部の形状が1辺が50μmの正方形であるとき
に、27pF程度の静電容量を得ようとする場合、
上記(2)式において、
C=2.7(pF)=2.7×10-12(F)
ε=12.2×8.854×10-12(F/m)
S=502(μm2)=(50×10-6)2(m2)
を代入すると、
d=εS/C=1×10-10(m)=1(Å)
となり、アルミニウムガリウムヒ素(Al0.3Ga0.7
As)の膜厚はかなり小さいものとなるので、使
用されるアルミニウムガリウムヒ素(AlGaAs)
等の化合物半導体の成長速度は膜厚を精度よく制
御するためには、比較的遅いことが望ましい。 In the above process, the capacitance of the capacitor naturally depends on the thickness of the semi-insulating aluminum gallium arsenide (Al 0.3 Ga 0.7 As) layer 2 and the facing area of the upper electrode 5 and the lower electrode 4. It is determined. As an example, when trying to obtain a capacitance of about 27 pF when the shape of the opposing portion of the upper electrode 5 and the lower electrode 4 is a square with one side of 50 μm,
In the above formula (2), C = 2.7 (pF) = 2.7 × 10 -12 (F) ε = 12.2 × 8.854 × 10 -12 (F/m) S = 50 2 (μm 2 ) = (50 × 10 - 6 ) By substituting 2 (m 2 ), d=εS/C=1×10 -10 (m)=1 (Å), and aluminum gallium arsenide (Al 0.3 Ga 0.7
Since the film thickness of As) is quite small, aluminum gallium arsenide (AlGaAs) is used.
It is desirable that the growth rate of such compound semiconductors be relatively slow in order to accurately control the film thickness.
一方、本発明を、立体構造を有する抵抗を含む
半導体装置に適用する場合は、アルミニウムガリ
ウムヒ素(AlGaAs)に所望の導電型を有する不
純物を所望の濃度となるように導入すれば、所望
の値の比抵抗となり、また上記(1)式において、L
が導電体層の厚さとなるので、これを所望の値と
なすことにより、目的の抵抗値を得ることができ
る。 On the other hand, when the present invention is applied to a semiconductor device including a resistor having a three-dimensional structure, the desired value can be obtained by introducing an impurity having a desired conductivity type into aluminum gallium arsenide (AlGaAs) to a desired concentration. , and in the above equation (1), L
is the thickness of the conductor layer, and by setting this to a desired value, the desired resistance value can be obtained.
上記の工程によれば、付加的工程をほとんど伴
わず、立体構造を有し、かつ、背面電極との接続
用端子と同一の領域に形成される、抵抗、キヤパ
シタ等の受動素子を有する半導体装置を製造する
ことができ、さらに、抵抗、キヤパシタの直列、
または並列回路も容易に立体構造となすことが可
能であり、抵抗、キヤパシタ等の専用面積を非常
に小さくする、また、不要となすことができ、装
置の高集積化に有効に寄与する。 According to the above process, a semiconductor device having a three-dimensional structure and having passive elements such as a resistor and a capacitor formed in the same area as a terminal for connection to a back electrode, with almost no additional steps. In addition, resistors and capacitors can be manufactured in series,
Alternatively, a parallel circuit can also be easily formed into a three-dimensional structure, and the area dedicated to resistors, capacitors, etc. can be made extremely small or unnecessary, which effectively contributes to higher integration of devices.
以上説明せるとおり、本発明に係る半導体装置
の製造方法においては、ヒ化ガリウム(GaAs)
基板上にヒ化ガリウムと格子定数のマツチングが
可能なアルミニウムガリウムヒ素層を形成し、ヒ
化ガリウム基板をエツチングして開口を形成し、
開口に対応するアルミニウムガリウムヒ素層を金
属層をもつて挟んでキヤパシタ形成するので、キ
ヤパシタは立体構造を有し、結果として、チツプ
表面の専用面積を必要とせず、また、アルミニウ
ムガリウムヒ素層よりなる誘電体層に歪みが発生
することがないので、信頼性が著しく向上する
とゝもに、静電容量値を所望の値に正確に制御す
ることができる。
As explained above, in the method for manufacturing a semiconductor device according to the present invention, gallium arsenide (GaAs)
An aluminum gallium arsenide layer whose lattice constant can be matched with gallium arsenide is formed on the substrate, and an opening is formed by etching the gallium arsenide substrate.
Since the capacitor is formed by sandwiching the aluminum gallium arsenide layer corresponding to the opening with metal layers, the capacitor has a three-dimensional structure, and as a result, it does not require a dedicated area on the chip surface. Since no distortion occurs in the dielectric layer, reliability is significantly improved and the capacitance value can be precisely controlled to a desired value.
また、本発明に係る半導体装置の製造方法にお
いては、ヒ化ガリウム(GaAs)基板上にヒ化ガ
リウムと格子定数のマツチングが可能なアルミニ
ウムガリウムヒ素のドープされた層(不純物を含
み抵抗値が有限であるアルミニウムガリウムヒ素
の層)を形成し、ヒ化ガリウム基板をエツチング
して開口を形成し、開口に対応するアルミニウム
ガリウムヒ素層を金属層をもつて挟んで抵抗を形
成するので、抵抗は立体構造を有し、結果とし
て、チツプ表面の専用面積を必要とせず、また、
アルミニウムガリウムヒ素層よりなる誘電体層に
歪みが発生することがないので、信頼性が著しく
向上するとゝもに、抵抗値を所望の値に正確に制
御することができる。 In addition, in the method for manufacturing a semiconductor device according to the present invention, a layer doped with aluminum gallium arsenide (containing impurities and having a finite resistance value) whose lattice constant can be matched with gallium arsenide on a gallium arsenide (GaAs) substrate. The gallium arsenide substrate is etched to form an opening, and the aluminum gallium arsenide layer corresponding to the opening is sandwiched between metal layers to form a resistor. structure, as a result, it does not require a dedicated area on the chip surface, and
Since no distortion occurs in the dielectric layer made of aluminum gallium arsenide, reliability is significantly improved and the resistance value can be accurately controlled to a desired value.
第1図〜第3図は、本発明の一実施例に係る半
導体装置におけるキヤパシタの製造方法の主要工
程完了後の基板断面図である。
1……半絶縁性基板(GaAs)、2……半絶縁
性アルミニウムガリウムヒ素(Al0.3Ga0.7As)
層、3……背面電極兼ヒートシンク形成用開口、
4……背面電極ヒートシンク(AuGe)、5……
上部電極(Al)。
1 to 3 are cross-sectional views of a substrate after completion of the main steps of a method for manufacturing a capacitor in a semiconductor device according to an embodiment of the present invention. 1... Semi-insulating substrate (GaAs), 2... Semi-insulating aluminum gallium arsenide (Al 0.3 Ga 0.7 As)
Layer 3... Opening for forming back electrode and heat sink;
4... Back electrode heat sink (AuGe), 5...
Top electrode (Al).
Claims (1)
(GaAs)基板1の一方の主面上に、アルミニウ
ムガリウムヒ素層2を形成する工程と、 前記基板1を、他方の主面から選択的にエツチ
ングして、前記アルミニウムガリウムヒ素層2が
露出した時点で該エツチングを停止して開口3を
形成する工程と、 該開口3を埋めて前記基板1の他方の主面上に
導出される背面電極4を形成する工程と、 前記アルミニウムガリウムヒ素層2上に、前記
開口3に対応して、上部電極5を形成する工程と を含んでなることを特徴とする半導体装置の製造
方法。 2 前記アルミニウムガリウムヒ素が絶縁性物質
であり、キヤパシタを構成することを特徴とする
特許請求の範囲第1項記載の半導体装置の製造方
法。 3 前記アルミニウムガリウムヒ素が導電性物質
であり、抵抗を構成することを特徴とする特許請
求の範囲第1項記載の半導体装置の製造方法。[Claims] 1. A step of forming an aluminum gallium arsenide layer 2 on one main surface of a semi-insulating or insulating gallium arsenide (GaAs) substrate 1; forming an opening 3 by selectively etching the aluminum gallium arsenide layer 2 and stopping the etching when the aluminum gallium arsenide layer 2 is exposed; and filling the opening 3 and exposing it to the other main surface of the substrate 1. and forming an upper electrode 5 on the aluminum gallium arsenide layer 2 in correspondence with the opening 3. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the aluminum gallium arsenide is an insulating material and constitutes a capacitor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the aluminum gallium arsenide is a conductive substance and constitutes a resistor.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11511482A JPS595655A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
DE8383303769T DE3377960D1 (en) | 1982-06-30 | 1983-06-29 | A field-effect semiconductor device |
EP19830303769 EP0098167B1 (en) | 1982-06-30 | 1983-06-29 | A field-effect semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11511482A JPS595655A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS595655A JPS595655A (en) | 1984-01-12 |
JPH0216587B2 true JPH0216587B2 (en) | 1990-04-17 |
Family
ID=14654584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11511482A Granted JPS595655A (en) | 1982-06-30 | 1982-07-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS595655A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR900001394B1 (en) * | 1985-04-05 | 1990-03-09 | Fujitsu Ltd | Super high frequency intergrated circuit device |
JPH0650407U (en) * | 1992-03-12 | 1994-07-12 | 勝 赤司 | Agricultural wheelchair with harness |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5515290A (en) * | 1978-07-20 | 1980-02-02 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
JPS5799767A (en) * | 1980-12-11 | 1982-06-21 | Mitsubishi Electric Corp | Semiconductor device |
JPS57104265A (en) * | 1980-12-19 | 1982-06-29 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-07-01 JP JP11511482A patent/JPS595655A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5515290A (en) * | 1978-07-20 | 1980-02-02 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
JPS5799767A (en) * | 1980-12-11 | 1982-06-21 | Mitsubishi Electric Corp | Semiconductor device |
JPS57104265A (en) * | 1980-12-19 | 1982-06-29 | Fujitsu Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS595655A (en) | 1984-01-12 |
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