JP3389009B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a MOSFET and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the circuit speed, it is necessary to increase the current driving force. For this purpose,
Up to now, the element has been miniaturized. For example, MOSF
In the case of ET, shortening the channel length by miniaturization is extremely effective.

When the MOSFET is operated with a channel length of 0.1 μm or less by further miniaturization, its driving force is roughly determined by the velocity of carriers near the source.

This is because of the following reasons. The carriers injected from the source end into the channel by diffusion are then accelerated by the electric field along the channel length direction and approach the saturation velocity value. Therefore, even if the channel length is further miniaturized, the acceleration is not sufficient in the source end region, and the carriers run at a low speed. As a result, MOSFE
The driving force of the entire T is limited by the carrier velocity in the source end region.

On the other hand, an MO having a channel length of 0.1 μm or less
In the SFET, the carrier in the channel is accelerated by the high electric field, reaches the drain with almost no scattering in the channel, and the carrier velocity higher than the saturation velocity is obtained. It is expected to increase.

However, even when trying to utilize this phenomenon, as described above, when the carrier velocity in the source end region is slow, the conductance of carriers in this region dominates the conductance of the entire element, resulting in velocity overshoot. I was not able to take advantage of the phenomenon.

In order to solve this problem, as shown in FIG. 10, the forbidden band width of the semiconductor forming the source layer 92 is made larger than the forbidden band width of the semiconductor forming the semiconductor substrate 91 in which the inversion layer is induced. , Proposed a MOSFET for injecting carriers from a source end into a channel at high speed by utilizing band discontinuity of a heterojunction of these two semiconductors (Japanese Patent Application No.
-150412). Specifically, the source layer 9
GaAs is used as the constituent semiconductor of No. 2 and Si is used as the constituent semiconductor of the semiconductor substrate 91.

However, this type of heterojunction MO
The SFET has a problem that the contact portion between the source layer 92 and the inversion layer 96 formed immediately below the gate electrode 95 is smaller than that of a normal homojunction MOSFET.

Further, the gate insulating film 94 and the gate electrode 9
After forming 5, the semiconductor having a large forbidden band width such as GaAs as the source layer 92 and the drain layer 93 needs to be selectively crystal-grown. However, there are problems that the manufacturing process is restricted, the manufacturing process is complicated, and the selective growth is required to restrict the manufacturing process.

[0010]

As described above, the conventional M
The OSFET has a problem that the carrier velocity in the source end region is slow. In addition, a MOSFET capable of solving such a problem has been proposed. However, after forming a gate electrode, it is necessary to selectively crystallize a semiconductor having a large forbidden band width as a source layer and a drain layer. There is a problem that the crystallinity of the drain layer is lowered at the gate end.

The present invention has been made in consideration of the above circumstances, and an object thereof is a MOSFET which has a high carrier velocity in the source end region and is advantageous in the process.
To provide a semiconductor device having the above and a manufacturing method thereof.

[0012]

[Outline] In order to achieve the above object, a semiconductor device according to the present invention (claim 1) includes a first source / drain layer.
Semiconductor layer, a second semiconductor layer formed in a predetermined shape on the first semiconductor layer and inducing an inversion layer, and the second semiconductor layer.
Of the second source-drain layers formed in the semiconductor layer, it comprises a MOSFET composed of said second semiconductor layer a gate electrode provided via a gate insulating film on the sidewall of the MOSFET is In the case of an n-channel, the energy difference between the conduction band and the vacuum level of the material of at least the source / drain layer used as the source of the first source / drain layer and the second source / drain layer is rather smaller than the energy difference between the conduction band and the vacuum level of the material of the second semiconductor layer, the MOSFET is p Cha
In the case of a channel, the energy difference between the valence band and the vacuum level of the material of at least the source / drain layer used as the source of the first source / drain layer and the second source / drain layer is Material of second semiconductor layer
It is characterized in that it is larger than the energy difference between the valence band of and the vacuum level.

Here, the predetermined shape is, for example, an island shape or a concave shape. Further, another semiconductor device according to the present invention (claim 2)
Comprises a MOSFET comprising a source layer and a drain layer formed in the semiconductor layer, and a gate electrode provided on the semiconductor layer between the source layer and the drain layer via a gate insulating film, The semiconductor layer is a p-type strained silicon layer, the source layer is an n-type strain-free silicon germanium layer, or the semiconductor layer is an n-type strained silicon germanium layer, and the source layer is a p-type strain-free silicon layer. To do.

Here, the source layer and the drain layer formed in the semiconductor layer are, for example, the source layer and the drain layer formed in or on the semiconductor layer. Further, a method of manufacturing a semiconductor device according to the present invention (claim 3).
Is a method of manufacturing semiconductor devices including MOSFET manufacturing processes.
A method, in a first semiconductor layer including a first source-drain layer, a second semiconductor layer which an inversion layer is induced, second
Of sequentially forming a third semiconductor layer as a source / drain layer by an epitaxial growth method, a step of etching the second semiconductor layer and the third semiconductor layer into a predetermined shape, and a gate insulating film and a gate over the entire surface. The method further comprises the steps of sequentially forming a conductive film to be an electrode and anisotropically etching the conductive film to form a gate electrode on a sidewall of the second semiconductor layer. The drain layer and the material of the source / drain layer used as at least the source of the second source / drain layer, and the MOSFET of n as the material of the second semiconductor layer.
For channels, the energy difference between the conduction band and the vacuum level of the material of the source-drain layer, also Kunar smaller than the energy difference between the conduction band and the vacuum level of the second semiconductor layer
When the MOSFET is a p-channel, the energy difference between the valence band of the source / drain layer and the vacuum level is the energy difference between the valence band of the second semiconductor layer and the vacuum level. It is characterized by using a larger one .

Here, the predetermined shape is, for example, an island shape or a concave shape. Another method for manufacturing a semiconductor device according to the present invention (claim 4) is a step of forming a source layer and a drain layer in a semiconductor layer, and a gate on the semiconductor layer between the source layer and the drain layer. A step of forming a gate electrode via an insulating film, wherein the semiconductor layer is a p-type strained silicon layer, the source layer is an n-type strainless silicon germanium layer, or the semiconductor layer is an n-type strained silicon germanium layer. P-type unstrained silicon layer is used as the layer and the source layer.

Here, the source layer and the drain layer formed in the semiconductor layer are, for example, the source layer and the drain layer formed in or on the semiconductor layer. [Operation] According to the present invention (Claim 1), the first or second source / drain layer (hereinafter,
A notch-shaped band discontinuity is formed at the junction surface between the source layer) and the second semiconductor layer in which the inversion layer is induced.

As a result, the carriers injected from the source layer into the second semiconductor layer obtain a large amount of energy at the junction surface and travel at high speed even at the edge of the source layer, and then along the channel length direction. Accelerated by the electric field,
The first or second source / drain layer (hereinafter referred to as the drain layer) used as the drain is reached.

Therefore, according to the present invention, the carrier travels at a high speed in the entire second semiconductor layer, so that a semiconductor device having a MOSFET with a high operation speed can be realized.

According to the present invention (claim 2), a notch-shaped band discontinuity is formed at the junction surface between the source layer and the semiconductor layer. As a result, carriers injected from the source layer into the semiconductor layer obtain a large amount of energy at the junction surface and travel at a high speed even at the edge of the source layer, and then are accelerated by an electric field along the channel length direction. , Reach the drain layer.

Therefore, according to the present invention, carriers travel at high speed in the entire semiconductor layer, so that a semiconductor device having a MOSFET with a high operating speed can be realized. Further, according to the present invention (claims 3 and 4), since the source layer and the drain layer are formed before the gate electrode is formed, the gate is formed after the above-mentioned conventional source layer and drain layer are formed. The problems of the conventional method of forming electrodes do not occur in principle. Therefore, the MOSFET of the semiconductor device according to the present invention (claims 1 and 2) is process-wise advantageous.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments (embodiments) of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing an element structure of an n-type MOSFET according to a first embodiment of the present invention.

In the figure, reference numeral 1 denotes a p-type silicon substrate, and a p-type silicon buffer layer 2 is formed on the p-type silicon substrate 1. On this p-type silicon buffer layer 2, a p-type with relaxed lattice strain is formed via a p-type graded Si _1-x Ge _x layer 3 in which the Ge concentration gradually increases from the bottom to the top. Type Si _0.7 Ge _0.3 layer 4
(First semiconductor layer) is formed. This p-type Si
_A first source / drain layer is formed on the surface of the _0.7 Ge _0.3 layer 4 as described later.

On the p-type Si _0.7 Ge _0.3 layer 4, an island-shaped p-type strained Si layer 5 (second semiconductor layer) in which the n-type inversion layer 10 lattice-matched with the p-type Si _0.7 Ge _0.3 layer is induced is formed. This p
On the type strained Si layer 5, a high concentration n is formed as a second source / drain layer in which lattice-matched island-shaped strain is relaxed.
A type Si _0.7 Ge _0.3 layer 6 is formed.

P-type strained Si layer 5 and n-type Si _0.7 Ge
_A gate electrode 8 is formed on the side surface of the _0.3 layer 6 via a gate insulating film 7. The p-type strained Si layer 5 and the n-type Si _0.7 Ge _0.3 layer 6 are surrounded by the p-type Si _0.7 G layer.
e _0.3 The surface of the layer 4 has the first source / drain electrode 1
A high-concentration n-type Si _0.7 Ge _0.3 layer 9 is formed as a first source / drain layer in which 1 is provided. Therefore, in this embodiment, when a positive voltage is applied to the gate electrode 8, the n-type inversion layer 10 is formed on the side surface of the p-type strained Si layer 5.
Is formed.

The entire surface of the element is covered with an interlayer insulating film 12, and a contact hole is opened in this interlayer insulating film 12, and n-type Si _0.7 is formed through this contact hole.
A first source / drain electrode 11 that contacts the Ge _0.3 layer 9 and a second source / drain electrode 13 that contacts the n-type Si _0.7 Ge _0.3 layer 6 and the first source / drain electrode 11 are formed. .

Next, a method of manufacturing the MOSFET thus configured will be described with reference to process sectional views of FIGS. First, as shown in FIG. 2 (a), a p-type silicon substrate 1 having a thickness of about 2 μm is formed on the p-type silicon substrate 1 by an epitaxial growth method such as a VPE (vapor phase epitaxy) method or an MBE (molecular beam epitaxy) method. Si buffer layer 2, p-type graded Si having a thickness x of about 1.5 μm and a Ge composition x increasing substantially linearly with thickness from 5% to 30%
_0.7 Ge _0.3 layer 3, thickness 250 nm and Ge composition 30
% Strain-relaxed p-type Si _0.7 Ge _0.3 layer 4, thickness 30
nm p-type Si _0.7 Ge _0.3 layer 4 lattice-matched p-type strained Si layer 5, 100 nm thick strain-relieved n-type Si
_{A 0.7} Ge _0.3 layer 6 (third semiconductor layer) is sequentially formed.

At this time, the p-type silicon substrate 1 and the p-type Si
Buffer layer 2, p-type graded Si _0.7 Ge _0.3 layer 3
And the impurity concentration of the p-type Si _0.7 Ge _0.3 layer 4 is 1 × 1.
0 ¹⁶ cm ⁻³ , the impurity concentration of the p-type strained Si layer 5 is 1 ×
The impurity concentration of the n-type Si _0.7 Ge _0.36 was set to about 10 ¹⁸ cm ^{-3 and} about 1 × 10 ²¹ cm ^-3 .

Next, as shown in FIG. 2B, n-type Si
After forming a photoresist pattern (not shown) on the _0.7 Ge _0.3 layer 6, the n-type Si _0.7 Ge _0.3 layer 6 and the p-type strained Si layer 5 are RIE (reactive ion etching) using the photoresist pattern as a mask. Method, n
The type Si _0.7 Ge _0.3 layer 6 and the p-type strained Si layer 5 are etched into an island shape. Then, the photoresist pattern is removed.

Next, as shown in FIG. 2C, a thin insulating film having a thickness of about 5 nm, a part of which is used as the gate insulating film 7, is deposited on the entire surface by a CVD (chemical vapor deposition) method. Next, as shown in FIG. 3A, a polycrystalline silicon film 8 having a thickness of 20 nm to be a gate electrode is deposited on the entire surface, and then phosphorus is ion-implanted on the entire surface at a dose amount of about 5 × 10 ¹⁵ cm ^-2. Then, the polycrystalline silicon film 8 is heavily doped with n-type.

Next, as shown in FIG. 3B, the entire surface is etched by anisotropic etching such as RIE.
A gate electrode 8 is formed by selectively leaving the n-type polycrystalline silicon film on the sidewalls of the n-type Si _0.7 Ge _0.3 layer 6 and the p-type strained Si layer 5.

Next, as shown in FIG. 3B, the gate electrode 8, the n-type Si _0.7 Ge _0.3 layer 6 and the p-type strained Si layer 5 are formed.
Using as a mask, arsenic is ion-implanted into the entire surface at a dose of about 5 × 10 ¹⁵ cm ^-2 , and then annealed to form a high concentration n-type Si _0.7 G on the surface of the p-type Si _0.7 Ge _0.3 layer 4.
e _0.3 Layer 9 is formed.

Next, as shown in FIG. 3C, a silicon oxide film as an interlayer insulating film 12 is deposited on the entire surface by a CVD method, and then the silicon oxide film is formed by a CMP (chemical mechanical polishing) method. The surface of the is polished to form an interlayer insulating film 12 having a flat surface.

Finally, a photolithography method is used to open contact holes in the interlayer insulating film 12 to form the source / drain electrodes 13, and the MOSFET having the structure shown in FIG. 1 is completed.

FIG. 4 shows the n-type Si _0.7 Ge _0.3 layer 9 (first
Is a source / drain layer), a p-type strained Si layer 5 (channel region), and an n-type Si _0.7 Ge _0.3 layer 6 (second source / drain).

N-type Si _0.7 Ge _0.3 layer 6 and p-type strained Si
Heterojunction surface with layer 5, p-type strained Si layer 5 and n-type Si
_0.7 The heterojunction surface between Ge _0.3 layer 9 can notched band discontinuity, the conduction band of the n-type Si _0.7 Ge _0.3 layers 6,9 is higher energy than the conduction band of the p-type strained Si layer 5 In position.

As a result, when the n-type Si _0.7 Ge _0.3 layer 6 is used as a source, the electrons injected from the n-type Si _0.7 Ge _0.3 layer 6 into the p-type strained Si layer 5 are these layers 5, 6 Gaining large kinetic energy at the heterojunction plane of
The n-type Si _0.7 Ge _0.3 layer also runs at high speed at the 6-edge. Then, the electrons are accelerated by the electric field along the channel length direction and reach the n-type Si _0.7 Ge _0.3 layer 9.

Therefore, according to the present embodiment, the electrons travel at high speed in the entire n-type Si _0.7 Ge _0.3 layer 9, so that an n-type MOS transistor having a high operating speed can be realized. Further, when electrons travel through the entire n-type Si _0.7 Ge _0.3 layer 9 at a high speed to reduce the channel length to 0.1 μm or less, an increase in current driving force due to a speed overshoot phenomenon can be expected.

On the other hand, in the case of the conventional MOSFET, since the normal unstrained Si is used for the semiconductor layer in which the inversion layer is induced and the strained Si layer is not used, the junction surface between the source layer and the semiconductor layer is not formed. No band discontinuity is possible, and the conduction band of the source layer is at a lower energy position than that of the semiconductor layer.

As a result, the electrons injected from the source layer into the semiconductor layer are diffused over these junction surfaces,
It travels at a low speed at the edge of the source layer, and then is accelerated by an electric field along the channel length direction to reach the drain. Therefore, electrons travel at a low speed at the edge of the source layer, so that an n-type MOS transistor having a high operating speed cannot be realized.

Further, according to this embodiment, the channel length is determined by the thickness of the epitaxially grown p-type strained Si layer 5, so that an extremely short channel MOSFET can be easily and strictly controlled in length. You will be able to make it by hand.

Since the gate electrode 8 is formed by leaving the sidewall after forming the p-type strained Si layer 5, the n-type Si _0.7 Ge _0.3 layer 6, and the gate insulating film 7, the above-mentioned conventional source layer, In principle, the problem of the conventional method of forming the gate electrode after forming the drain layer (for example, the source / drain layer is separated from the inversion layer) does not occur.

In the present embodiment, the Ge composition x of the Si _1-x Ge _x layer is set to 30%, but it is not limited to this. The same applies to the other embodiments described below. (Second Embodiment) FIG. 5 is a sectional view showing an element structure of a p-type MOSFET according to a second embodiment of the present invention.
The portion corresponding to the n-type MOSFET in FIG.
Are denoted by the same reference numerals, and detailed description will be omitted.

The feature of this embodiment is that p-type unstrained Si is used as the first and second source / drain layers 9'and 6 ', and n-type strained Si _{1-x is used} as the semiconductor layer 5'in which the inversion layer is induced. Ge
I used _x .

As the silicon substrate and the silicon buffer layer, an n-type silicon substrate 1'and an n-type silicon buffer layer 2 ', which have conductivity types opposite to those of the n-type MOS transistor shown in FIG. 1, are used. In the case of this embodiment, the graded Si _1-x Ge _x buffer layer is not necessary.

Also in this embodiment, since the notch-shaped band discontinuity is formed at the heterojunction surface between the source / drain layers 9'and 6'and the semiconductor layer 5 ', the hole traveling speed in the entire channel is increased. It becomes faster and can realize high-speed operation. In addition, the same effects as those of the first embodiment can be obtained. (Third Embodiment) FIG. 6 is a sectional view showing an element structure of an n-type MOSFET according to a third embodiment of the present invention.

The first and second embodiments are vertical type MOSFEs.
Although this is an example of T, this embodiment is an example in which the present invention is applied to an ordinary planar type MOSFET. This will be described according to the manufacturing process. First, the p-type silicon buffer layer 22 is formed on the p-type silicon substrate 21.

Next, after the p-type silicon germanium buffer layer 23 is formed on the p-type silicon buffer layer 22, the p-type silicon germanium buffer layer 23 is formed.
P-type Si _1-y Ge on which an inversion layer with lattice relaxation is induced
_{The y} layer 24 is formed.

Next, after forming an n-type strained Si layer to be the first and second source / drain layers 25 and 26 on the p-type Si _1-y Ge _y layer 24, this n-type strained Si layer is formed. By patterning, the first and second source / drain layers 25 and 26 are formed.
To form.

Next, the gate insulating film 27 is formed on the entire surface, and subsequently, a conductive film to be the gate electrode 28 is formed on the gate insulating film 27, and then the conductive film is patterned to form the gate electrode 28.

Next, the first and second source / drain layers 2
Openings are formed in the gate insulating films on 5, 26 to form first source / drain electrodes 29, 30. After this,
Although not shown, an interlayer insulating film is formed as in the case of the first embodiment, contact holes are opened in this interlayer insulating film, and then second source / drain electrodes are formed to complete the process.

Also in this embodiment, the first and second source / drain layers (n-type strained Si layers) 25 and 26 and the p-type Si _{1-y are formed.}
Since a notch-shaped band discontinuity is formed on the heterojunction surface with the Ge _y layer 24, it is possible to realize an n-type MOSFET having the effect of high-speed operation and the like as in the first embodiment.

In the present embodiment, the case of the n-type MOSFET has been described, but as in the second embodiment, the strain n
It is also possible to form a p-type MOSFET by using the type Si _1-y Ge _y layer and the unstrained Si layer. (Fourth Embodiment) FIG. 7 is a plan view and a sectional view showing an element structure of an n-type MOSFET according to a fourth embodiment of the present invention. The parts corresponding to those of the n-type MOSFET in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted.

The feature of this embodiment is that the p-type strained Si layer 5,
a groove is formed in n-type Si _0.7 Ge _0.3 layer 6, n-type Si _0.7 Ge into the p-type Si _0.7 surface of the Ge _0.3 layer 4 of the bottom surface of the groove
_{The 0.3} layer 9 is formed, and the gate electrode 8 is formed on the side wall of the groove with the gate insulating film 7 interposed therebetween. In this embodiment, the same effect as that of the first embodiment can be obtained. Although the groove has a square planar shape in the present embodiment, it may have another shape. Further, in the figure, 31 indicates a gate extraction electrode. (Fifth Embodiment) FIGS. 8 and 9 are process sectional views showing a method for manufacturing an n-type MOSFET according to a fifth embodiment of the present invention.

First, as shown in FIG. 8A, a p-type silicon buffer layer 42, a p-type graded Si _0.7 Ge _0.3 layer 43, and strain-relaxed p are formed on a p-type silicon substrate 41.
A type Si _0.7 Ge _0.3 layer 44 is sequentially formed.

Next, as shown in FIG. 8B, oxygen ions (O ⁺ ) are implanted into the strain-relaxed p-type Si _0.7 Ge _0.3 layer 44 to form a buried oxide film 32. As a result, the strain-relaxed p-type Si _0.7 Ge _0.3 layer 44 has SIMOX.
An SOI structure similar to the substrate is formed.

Next, as shown in FIG. 8C, p-type Si
To _0.7 Ge _0.3 layer 44 over the entire surface by implanting As ions (As ^+), it was a high concentration of strain relaxation that the p-type Si _0.7 Ge _0.3 layer 44 was strain-relaxed above the buried oxide film 32 becomes an n-type source layer Change to n-type Si _0.7 Ge _0.3 layer 49.

Next, as shown in FIG. 8D, n-type Si
After etching the _0.7 Ge _0.3 layer 49 into an island shape, a gate insulating film 47 made of SiO ₂ is formed on the entire surface by a CVD method. Since the gate insulating film 47 formed in this step is etched in a later step, part of it is actually used as a gate insulating film.

Next, as shown in FIG. 9A, the gate insulating film 47 and the n-type Si _0.7 Ge _0.3 layer 49 are etched to form an n-type source layer. At this time, as shown in the drawing, one side wall of the n-type Si _0.7 Ge _0.3 layer 49 is exposed.

Next, as shown in FIG. 9B, n-type Si
_{After the} p-type strained Si layer 45 is laterally grown using the exposed surface of the _0.7 Ge _0.3 layer 49 as a seed, the p-type strained Si layer 45 is grown.
A gate insulating film 47 is formed on top.

Next, as shown in FIG. 9C, after forming a conductive film to be the gate electrode 48 on the gate insulating film 47,
The conductive film is patterned to form the gate electrode 48. At this time, the edge of the gate electrode 48 and the n-type Si _0.7 G
e _0.3 Pattern so that the end of the layer 49 is aligned.

Next, as shown in FIG. 6C, by ion implantation of As using the gate electrode 48 as a mask, the p-type strained Si layer 45 is used as an n-type drain layer with a high concentration of n-type Si _0.7 Ge. Change to _0.3 layer 46a. After that, activation annealing is performed.

Finally, as shown in FIG. 9D, after forming an opening in the gate insulating film 47 on the source / drain layer, a source / drain electrode 51 is formed to complete the process. In this embodiment, the same effect as that of the first embodiment can be obtained.
In the figure, 50 indicates an n-type inversion layer. Also, p
An n-type strained silicon germanium layer may be used instead of the type-strained Si layer 45, and a strain-relaxed n-type silicon germanium layer (n-type unstrained silicon germanium layer) may be used instead of the strain-relaxed n-type Si _0.7 Ge _0.3 layer 49. Similar effects are obtained.

The present invention is not limited to the above embodiment. For example, in the first, second and third embodiments, the case where the source layer and the drain layer may be exchanged, which is an advantageous structure for expanding the degree of freedom in circuit design, is presented. However, if the source and drain layers on the circuit may be limited, the device can be further improved.

For example, in the case of the n-type MOS transistor of FIG. 1, when the n-type Si _1-x Ge _x layer 6 is used as the source layer, a drain layer should be formed inside the p-type strained Si layer 5. Thus, the parasitic drain resistance due to band discontinuity can be reduced.

To form the drain layer inside the p-type strained Si layer 5, for example, p-type strained S by oblique ion implantation is used.
A high dose of n-type impurities may be implanted in the i layer 5. On the other hand, when the n-type Si _0.7 Ge _0.3 layer 9 is used as the source layer, a high concentration is formed on the surface of the p-type strained Si layer 5 on the interface side between the p-type strained Si layer 5 and the n-type Si _0.7 Ge _0.3 layer 6. The n-type layer may be formed.

Specifically, for example, when the crystal growth of the p-type strained Si layer 5 is completed, n-type impurities are added to the raw material to grow Si crystal, or after the p-type strained Si layer 5 is formed, p
A high dose of n-type impurities is implanted into the surface of the strained Si layer 5.

In the above embodiment, the case where the notch-shaped band discontinuity is formed on both of the two heterojunction surfaces has been described. However, in order to eliminate the cause of the decrease in the operating speed, it is used at least as a source. It suffices that a notch-shaped band discontinuity is formed on the heterojunction surface between the source / drain layer and the semiconductor layer on which the inversion layer is formed.

Further, as the material of the semiconductor layer in which the source / drain layer and the inversion layer are induced, in addition to those used in the above embodiment, Si, Ge, Si _1-x C _x , Si _1-xy C
_x Ge _y , Ge _1-x C _x , Si _1-xyz C _x Ge _y Sn
Similar effects can be obtained by using an appropriate combination of _z and the like. In addition, various modifications can be made without departing from the scope of the present invention.

[0069]

As described in detail above, according to the present invention, it is possible to provide a semiconductor device having a MOSFET that operates at high speed and is processally advantageous, and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1 is an n-type MOSFE according to a first embodiment of the present invention.
Sectional drawing which shows the element structure of T

FIG. 2 is an n-type MOSFE according to the first embodiment of the present invention.
Process sectional drawing showing the manufacturing method of the first half of T

FIG. 3 is an n-type MOSFE according to the first embodiment of the present invention.
Process sectional drawing showing the manufacturing method of the latter half of T

FIG. 4 is an n-type MOSFE according to the first embodiment of the present invention.
Band diagram of T

FIG. 5 is an n-type MOSFE according to a second embodiment of the present invention.
Sectional drawing which shows the element structure of T

FIG. 6 is a p-type MOSFE according to a third embodiment of the present invention.
Sectional drawing which shows the element structure of T

FIG. 7 is an n-type MOSFE according to a fourth embodiment of the present invention.
The top view and sectional drawing which show the element structure of T.

FIG. 8 is an n-type MOSFE according to a fifth embodiment of the present invention.
Process sectional drawing showing the manufacturing method of the first half of T

FIG. 9 is an n-type MOSFE according to a fifth embodiment of the present invention.
Process sectional drawing showing the manufacturing method of the latter half of T

FIG. 10 is a sectional view showing a device structure of a conventional MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... p-type silicon buffer layer 3 ... p-type graded Si _1-x Ge _x layer 4 ... p-type Si _0.7 Ge _0.3 layer (first semiconductor layer) 5 ... p-type strained Si layer (Second semiconductor layer) 6 ... n-type Si _0.7 Ge _0.3 layer (second source / drain layer, third semiconductor layer) 7 ... Gate insulating film 8 ... Gate electrode 9 ... n-type Si _1-x Ge _x Layer (first source / drain layer) 10 ... N-type inversion layer 11 ... First source / drain electrode 12 ... Interlayer insulating film 13 ... Second source / drain electrode 21 ... P-type silicon substrate 22 ... P-type silicon Buffer layer 23 ... p-type silicon germanium buffer layer 24 ... p-type Si _1-y Ge _y layer 24 25 ... n-type strained Si layer (first source / drain layer) 26 ... n-type strained Si layer (second) Source / drain layer) 27 ... Gate insulating film 18 ... Gate electrode 29 Source / drain electrode 30 Source / drain electrode 32 Buried oxide film 41 p-type silicon substrate 42 p-type silicon buffer layer 43 p-type graded Si _0.7 Ge _0.3 layer 44 p-type Si _0.7 Ge _0.3 layer 45 ... p-type strained Si layer 46a ... n-type Si _0.7 Ge _0.3 layer 47 ... gate insulating film 48 ... gate electrode 49 ... n-type Si _0.7 Ge _0.3 layer 50 ... n-type inversion layer 51 ... source / drain electrode

Claims (4)

(57) [Claims] 1. A first semiconductor layer including a first source / drain layer, a second semiconductor layer formed in a predetermined shape on the first semiconductor layer and inducing an inversion layer, a second source-drain layer formed on the second semiconductor layer, and comprises a MOSFET composed of said second semiconductor layer a gate electrode provided via a gate insulating film on the sidewall of the MOSFET Is an n-channel, the energy difference between the conduction band and the vacuum level of the material of at least the source / drain layer used as the source of the first source / drain layer and the second source / drain layer is: the second rather smaller than the energy difference between the conduction band and the vacuum level of the material of the semiconductor layer, wherein when the MOSFET is a p-channel, the first source-drain layer and the second source-drain The energy difference between the valence band and the vacuum level of the material of the source-drain layer to be used as at least a source of layers,
A semiconductor device having a larger energy difference between a valence band and a vacuum level of the material of the second semiconductor layer. 2. A MOSFET comprising a source layer and a drain layer formed in a semiconductor layer, and a gate electrode provided on the semiconductor layer between the source layer and the drain layer via a gate insulating film. The semiconductor layer is a p-type strained silicon layer, and the source layer is n.
Type unstrained silicon germanium layer, or the semiconductor layer is an n type strained silicon germanium layer, and the source layer is a p type unstrained silicon layer. 3. A semiconductor device including a manufacturing process of a MOSFET.
And a first semiconductor layer including a first source / drain layer,
A step of sequentially forming a second semiconductor layer in which an inversion layer is induced and a third semiconductor layer as a second source / drain layer by an epitaxial growth method; and a step of forming the second semiconductor layer and the third semiconductor layer in a predetermined manner. Etching into a shape, a step of sequentially forming a gate insulating film and a conductive film to be a gate electrode over the entire surface, and anisotropic etching of the conductive film to form a gate electrode on a sidewall of the second semiconductor layer. it and a process for the material of the source-drain layer to be used as at least a source of said first source-drain layer and the second source-drain layer, the material of the second semiconductor layer < as br />, wherein the MOSFET is the case of n-channel, the energy difference between the conduction band and the vacuum level of the material of the source-drain layer, the conduction band and the vacuum level of the second semiconductor layer Use Kunar those smaller than energy differences, if the MOSFET is a p-channel, the energy difference between the valence band and the vacuum level of the source-drain layer, the valence band and the vacuum of the second semiconductor layer A method of manufacturing a semiconductor device, wherein a material having an energy difference larger than a level is used . 4. A step of forming a source layer and a drain layer in the semiconductor layer, and a step of forming a gate electrode on the semiconductor layer between the source layer and the drain layer via a gate insulating film. A p-type strained silicon layer is used as the semiconductor layer, an n-type strainless silicon germanium layer is used as the source layer, or an n-type strained silicon germanium layer is used as the semiconductor layer, and a p-type strainless silicon layer is used as the source layer. A method of manufacturing a semiconductor device, comprising: