JPH09213936A - Charge coupled device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a noise component mixing in the potential at a charge detector by covering the marginal end of a reset gate electrode at the side of an output gate with a shield electrode, except that of a narrower overhang than the width of a reset drain region. SOLUTION: A reset gate electrode 5a has a narrower overhang 4a-1 on a floating diffused layer than the width of a reset drain region 5, the part 4a-1 is disposed on a coupling part 8-1, and the marginal end of the electrode 4a at the side of an output gate 2 is covered with a shield electrode 15, except that of the overhang 4a-1. This reduces the coupling capacitance between the electrode 4a and charge detector and as a result unwanted potential variation of the charge detector can be made very little.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera and an F
The present invention relates to a charge-coupled device used in a solid-state image pickup device used for an AX and a scanner, and more specifically to the structure of its charge detection unit.

[0002]

2. Description of the Related Art The structure of a charge detecting portion of a conventional charge coupled device is shown in FIG. This is, for example, Japanese Patent Laid-Open No. 1-259555.
4A is a plan view and FIG. 4B is a cross-sectional view taken along the line AA of FIG. 4A. 1
Is a transfer gate electrode of the CCD register (a pair of a storage electrode made of a first-layer polysilicon film and a barrier electrode made of a second-layer polysilicon film), and 2 is a voltage applied to the charge carried by the CCD register. An output gate electrode for outputting to the charge detection unit 3 that is converted into the charge detection unit 3, a reset gate electrode 4 for applying the reference potential V _RD to the charge detection unit 3, and a reset drain region 5 to which the reference potential V _RD is applied. Reference numeral 6 is an output wiring for transmitting the electric potential of the charge detecting portion, and 7 is an output wiring 6 and the charge detecting portion 3.
N-type high-concentration impurity diffusion layer for ensuring connection of
Reference numeral 8 is a channel portion of a CCD register, an output gate, a reset gate, and an N-type low-concentration impurity diffusion layer forming a part of the charge detection portion, and 9 is a P-well on the surface portion of an N-type silicon substrate, for example.

The operation of the charge coupled device configured as described above will be described with reference to the timing diagram shown in FIG. 5 and the potential diagram shown in FIG. At time t ₁ , a high voltage is applied to the reset gate electrode 4 to bring the reset gate into a conductive state, so that the floating diffusion layer of the charge detection portion (the portion sandwiched between the output gate electrode 2 and the portion directly below the reset gate electrode 4). The potential V _S of the low concentration impurity diffusion layer 8 and the high concentration impurity diffusion layer 7) is set to the same potential as the reset drain voltage V _RD applied to the reset drain region 5. At time t ₂ , the reset gate electrode 4 is set to a low voltage and the reset gate is made non-conductive. At this time, the potential V _S of the floating diffusion layer of the charge detection unit is expressed by the following equation (1) because of the coupling capacitance C ₀ existing between the reset gate electrode 4 and the floating diffusion layer of the charge detection unit 3. Subject to potential fluctuation V _O.

V ₀ = V _R C _O / C _T (1) where C _T is the capacitance of the charge detecting portion and V _R is the amplitude of the pulse φ _R applied to the reset gate electrode. At time t ₃ , by changing the φ ₁ pulse applied to the transfer gate electrode 1 of the CCD register from “H” to “L”,
The signal charge Q ₁ existing under the transfer gate electrode 1 is caused to flow into the charge detection unit 3. As a result, the potential fluctuation V ₁ of the charge detector becomes as shown in equation (2).

V ₁ = C ₁ / C _T (V) (2) By transmitting these potential changes of V _S through the output wiring 6, the so-called signal charge of conversion of signal charge into voltage Detection is taking place.

[0006]

However, in the conventional structure, V given by the equation (1) is generated due to the coupling capacitance C ₀ existing between the reset gate electrode 4 and the charge detection portion 3. A potential fluctuation of ₀ was applied to the charge detection unit. Specifically, for example, C _T = 10fF, C ₀ = 1
In a general numerical example of fF, V _R = 120, V ₀ = 1.
It was as big as 20. On the other hand, the signal V ₁ to be detected is, for example, C _T = 10f as shown in the equation (2).
F, Q ₁ = 10f Coulomb V ₁ = 10/10 = 10
And V ₀ are almost the same.

As described above, the potential V _S of the charge detecting portion has caused a completely unnecessary potential variation of V ₀ which is almost the same level as that of V ₁ which is a signal, in addition to V ₁ which is a signal. This unnecessary potential fluctuation V ₀ must be finally removed from the signal when the potential fluctuation of V _S is passed through the output wiring 6 and signal processing such as amplification is performed. Since the removal function is provided, the price of the signal processing circuit is increased.

[0008]

SUMMARY OF THE INVENTION A charge coupled device according to the present invention includes a CCD register having a plurality of charge transfer electrodes provided above a semiconductor substrate, and a signal charge received from the CCD register via an output gate to generate a voltage. A charge detection unit having a floating diffusion layer for converting into a reset diffusion region, a reset / drain region formed on a surface portion of the semiconductor substrate apart from the floating diffusion layer, and the semiconductor sandwiched between the floating diffusion layer and the reset / drain region. A charge-coupled device having a reset gate including a reset gate electrode provided on a surface of a substrate via a gate insulating film, wherein the reset
The gate electrode has an overhang portion on the floating diffusion layer side that is narrower than the reset / drain region side, and the floating diffusion layer includes a connection portion on the reset gate side that is narrower than the output gate side. The protruding portion is disposed on the connecting portion and is covered with a shield electrode except for the edge portion of the reset gate electrode on the output gate side except the edge portion of the protruding portion. is there.

In this case, an impurity diffusion layer having a conductivity type opposite to that of the floating diffusion layer is selectively provided on the surface portion of the floating diffusion layer having a constant width to narrow the effective width of the floating diffusion layer and to form a connecting portion. You can

Also, a fixed potential can be applied to the shield electrode.

With this configuration, by significantly reducing the coupling capacitance between the reset gate electrode and the charge detection unit, it is possible to significantly reduce the noise component that the reset pulse mixes with the potential of the charge detection unit. Further, by narrowing the width of the connecting portion, it is possible to reduce the coupling capacitance between the electrode to which the fixed potential is applied and the charge detecting portion, thereby suppressing the increase in the capacitance of the charge detecting portion.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of a charge detection unit and its vicinity in a charge coupled device according to an embodiment of the present invention.
1B is a sectional view taken along the line AA of FIG. 1A, and FIG. 1C is a sectional view taken along the line BB of FIG. The CCD register is exactly the same as the conventional example shown in FIG.

In the present embodiment, a CCD register having a plurality of charge transfer electrodes (1 in FIG. 4) provided above a silicon semiconductor substrate having a P well 9 on the surface thereof and an output gate ( A charge detection unit 3a having a floating diffusion layer (high-concentration impurity diffusion layer 7 and a low-concentration impurity diffusion layer around the high-concentration impurity diffusion layer 7) that receives signal charges via the output gate electrode 2) and converts them into a voltage; The reset / drain region 5 formed on the surface of the P well 9 apart from the floating diffusion layer described above and the surface of the semiconductor substrate sandwiched between the floating diffusion layer and the reset drain region 5 via the gate insulating film 11 Reset gate electrode 4
In a charge-coupled device having a reset gate including a, the reset gate electrode 4a (first-layer polysilicon film) has an overhang portion that is narrower on the floating diffusion layer side than on the reset drain region 5 side. 4a-1 and the floating diffusion layer described above has a connecting portion 8-1 that is narrower on the reset gate (4a) side than on the output gate (2) side.
-1 is disposed on the connecting portion 8-1, and the protruding portion 4a is included in the edge portion of the reset gate electrode 4a on the output gate (2) side.
It is covered with the shield electrode 15 (polysilicon film of the second layer) except the edge portion of -1. The shield electrode 15 and the reset gate electrode have a thickness of 300 to 40.
It is insulated by a 0 nm silicon oxide film 14.

Here, a P-type impurity diffusion layer 13 opposite to the floating diffusion layer is selectively provided on the surface of the N-type floating diffusion layer (8) having a constant width (W ₁ = 10 μm). The effective width of the floating diffusion layer is narrowed to W _A = 2 μm to form the connecting portion 8-1. A fixed potential (ground potential) is applied to the shield electrode 15.

The P-type impurity diffusion layer reduces the effective area of the charge detecting portion 3a, and the shield gate electrode 15 and the charge detecting portion are separated from each other.

Regarding the operation of the charge detecting device configured as described above, the applied pulse timing chart of FIG. 2 and FIG.
Description will be made with reference to potential diagrams of (a) and (b).

At time t ₁₁ , the reset gate electrode 4a
By applying a high voltage to the reset gate to make the reset gate conductive, the potential V _S1 of the charge detection unit is set to the same potential as the reset drain potential V _RD applied to the reset drain region 5. At time t _21, the reset gate electrode 4a as a low voltage, the reset gate non-conductive. At this time, the electric potential V _S1 of the electric detector is changed according to the same principle as the conventional example. However, most of the reset gate electrode 4a is shielded by the shield electrode 15 with respect to the charge detection portion, so that its variation is small. Specifically, assuming that the width of the overhanging portion 4a-1 of the reset gate electrode which is in contact with the charge detecting portion 3a is W _A and the width of the conventional reset gate potential is W ₁ , the reset gate electrode 4a The coupling capacitance C ₀₁ existing between the charge detector 3a and the charge detector 3a is smaller than that of the conventional example in the ratio of W _A and W ₁ . Thus a potential variation V ₀₁ by coupling capacitor C ₀₁ is _{V 01 = V R C 01 /} C T = (C 0 × W A / W 1) · V R / C T = V 0 × (W A / W 1) (3) It becomes small.

At time t ₃₁ , the φ ₁ pulse applied to the transfer gate electrode 1 of the CCD register is changed from “H” to “L”, so that the signal charges flow in and V _S1 becomes a signal due to potential fluctuation. What is detected is the same as in the conventional example.

Here, V ₀₁ is W _{A as} can be seen from the equation (3).
It can be reduced in proportion to / W ₁ . Specifically, C _T = ₁₀ fF, C ₀ = 1 fF, and V _R = 120 are the same as in the conventional example, W _A = 2 μm, W ₁ = 10 μm, L _A = 1 μ
m, L _C = 5 μm, L _D = 5 μm, V ₀₁ = V ₀ ×
(2/10) = 0.24V, which is very small,
It becomes about 20% of V _O of the conventional example.

A P-type impurity diffusion layer 13 formed by ion implantation is provided below the shield electrode 15 at a portion where the shield electrode 15 and the charge detection portion 3a are in contact with each other. As a result, there is effectively no charge detection section below the shield electrode 15, and the capacitance between the shield electrode 14 and the charge detection section 3a is prevented from increasing. This impurity diffusion layer 1
If there is not 3, the large coupling capacitance C _C between the shield electrode 15 and the charge detection unit 3a is added to the charge detection unit capacitance C _T , and as a result, as can be seen from the equation (2), the potential fluctuation V ₁ due to the signal is This lowers the sensitivity of the charge detection unit. In the present invention, this coupling capacity can be reduced to a negligible level.

The impurity diffusion layer 13 may be deeper than the low-concentration impurity diffusion layer 8.

[0023]

As described above, the present invention reduces the coupling capacitance between the reset gate electrode and the charge detection unit by shielding most of the reset gate electrode with respect to the charge detection unit by the shield electrode. As a result, unnecessary potential fluctuations in the charge detection unit can be made extremely small.

In addition, the protruding portion of the reset gate electrode is provided on the narrow connecting portion of the floating diffusion layer to weaken the coupling between the shield potential and the charge detection portion, and thus the coupling capacitance for the shield electrode and the charge detection portion. Is small,
Since the unnecessary potential fluctuation is reduced without lowering the sensitivity of the charge detection unit, there is an effect that the signal processing circuit is simplified and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention (FIG.
(A)), a sectional view taken along line AA of FIG. 1 (a) (FIG. 1 (b))
It is a BB line sectional view (FIG.1 (c)).

FIG. 2 is a pulse timing chart for explaining the operation of the embodiment.

FIG. 3 is a potential diagram of a portion along line AA of FIG. 1A for explaining the operation of the embodiment (FIG. 3A) and a potential of a portion along line BB. It is a figure (FIG.3 (b)).

FIG. 4 is a plan view showing a conventional example (FIG. 4A) and FIG.
It is the sectional view on the AA line of (a) (FIG.4 (b)).

FIG. 5 is a pulse timing diagram for explaining the operation of the conventional example.

FIG. 6 is a potential diagram for explaining the operation of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transfer gate electrode 2 Output gate electrode 3,3a Charge detection part 4,4a Reset gate electrode 4a-1 Overhang part 5 Reset drain region 6 Output wiring 7 High concentration impurity diffusion layer 8 Low concentration impurity diffusion layer 8-1 Connection part 9 P-well 10 Barrier layer 11 Gate insulating film 12 Silicon oxide film 13 P-type impurity diffusion layer 14 Silicon oxide film 15 Shield electrode

Claims (3)

[Claims] 1. A CCD register having a plurality of charge transfer electrodes provided above a semiconductor substrate, and a charge detection unit having a floating diffusion layer that receives signal charges from the CCD register through an output gate and converts the signal charges into a voltage. A reset / drain region formed on the surface of the semiconductor substrate apart from the floating diffusion layer and a surface of the semiconductor substrate sandwiched between the floating diffusion layer and the reset / drain region with a gate insulating film interposed therebetween. And a reset gate including a reset gate electrode, wherein the reset gate electrode has an overhang portion on the floating diffusion layer side that is narrower than the reset drain region side, A layer has a connecting portion that is narrower on the reset gate side than on the output gate side, and the overhanging portion is disposed on the connecting portion; A charge-coupled device, characterized in that the set gate electrode is covered with a shield electrode except for the edge of the protruding portion of the edge on the output gate side. 2. An impurity diffusion layer having a conductivity type opposite to that of the floating diffusion layer is selectively provided on a surface portion of the floating diffusion layer having a constant width to narrow an effective width of the floating diffusion layer and to form a connecting portion. The charge-coupled device according to claim 1. 3. The charge coupled device according to claim 1, wherein a fixed potential is applied to the shield electrode.