KR100299575B1 - Solid-state image sensor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state imaging device, in particular, a solid state imaging device having a small pixel that handles a small amount of charge. The solid state imaging device includes a photoelectric conversion section (a) for converting light into electric charges; An ultrashort MOSFET comprising a transfer section (b) for transferring charge, a floating diffusion layer (c) for converting transferred charges into a voltage, and a source follower circuit (d) having multiple stages for amplifying and outputting the voltage. The distance between the wiring supplied with the drain potential of the gate electrode and the gate electrode is longer than the distance between the wiring supplied with the drain potential of the MOSFET of the second stage or the next stage and the gate electrode. According to the above-mentioned solid state imaging device, the capacitance of the gate electrode of the ultra-short MOSFET can be reduced, so that a high sensitivity can be secured even in a solid state imaging device having a small pixel that handles a small amount of charge.

Description

Solid State Imaging Device {SOLID-STATE IMAGE SENSOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state imaging device, in particular, a solid state imaging device having a small pixel that handles a small amount of electric charge.

The charge transfer device is usually manufactured to include an output circuit composed of multiple stage MOSFETs. The above apparatus accumulates the signal charges transmitted through the charge transfer section as the detection capacitance, and amplifies and outputs the potential variation of the detection capacitance. In the above general charge transfer apparatus, a source follower circuit including a reset MOSFET having a floating diffusion layer for signal charge detection and a MOSFET having a gate electrode electrically connected to the floating diffusion layer through a wiring layer. The charge transfer device constituting the above is known in the art.

For example, one such device is disclosed in 'Two Phase Charge Coupled Devices with Overlapping Polysillicon and Aluminum Gates', Kosonocky, WF and Cames. JE, RCA Review Vol. 34, pp. 146-202, 1973. It is.

1 is a cross sectional view of a conventional solid-state imaging device. The solid-state imaging device shown above includes a photoelectric conversion unit (not shown) in which light is converted into electricity, a signal charge including a three-phase drive charge transfer unit 10 for transferring charge, and a reset MOSFET 14. A source follower circuit composed of two stages comprising a detector 16, an ultra-short source follower circuit 18, and a second-stage source follower circuit 20 is provided.

In Fig. 1, the three-phase drive charge transfer section 10 includes a P-type semiconductor substrate 22, an N-type semiconductor region 24 formed on the P-type semiconductor substrate 22, charge transfer pulses? 1,? 2, And charge transfer electrodes 26, 28, and 30 to which Φ3 is applied, and gate electrode 32 to which low voltage Vog generated at the output of the charge transfer section 10 is applied.

The signal charge detection unit 16 includes the P-type semiconductor substrate 22, the floating diffusion layer 12 formed on the P-type semiconductor substrate 22, and the N-type semiconductor region formed on the P-type semiconductor substrate 22. (24), an N ⁺ type semiconductor region 36 electrically connected to the reset power supply _Vrd , and a reset gate electrode 34 to which a reset pulse voltage? Is applied.

The first stage source follower circuit 18 includes a P-type semiconductor substrate 22, a gate electrode 37 of the first MOSFET for charge detection, a gate electrode 39 of a depletion type second MOSFET serving as a load, A wiring layer 41 for supplying the drain potential, a wiring layer 43 for drawing the source potential of the first MOSFET, a wiring layer 45 for supplying the ground potential or the source potential of the second MOSTET, and an apparatus. Is composed of a high concentration P-type semiconductor region 48 that electrically isolates each of the regions to be manufactured, and an interlayer insulating film 49 that electrically insulates the gate electrodes 37 and 39 from each other.

The second stage source follower circuit 20 includes a P-type semiconductor substrate 22, a gate electrode 38 of the first MOSFET for charge detection, and a depletion-type second MOSFET gate electrode 40 serving as a load. A wiring layer 42 for supplying the drain potential, a wiring layer 44 for extracting the source potential of the first MOSFET, a wiring layer 46 for supplying the ground potential or the source potential of the second MOSTET; A high concentration P-type semiconductor region 50 electrically separating each region to be fabricated, and an interlayer insulating film 51 electrically insulating the gate electrodes 38 and 40.

The floating diffusion layer 12 of the signal charge detection unit 16 is electrically connected to the gate electrode 37 of the first stage source follower circuit 18 through the wiring 53.

The drain power source Vdd is electrically connected to the wiring layers 41 and 42 in the source follower circuits 18 and 20 in the first and second stages. The wiring layer 43 for extracting the source voltage of the source follower circuit 18 at the first stage is electrically connected to the gate electrode 38 of the source follower circuit 20 at the second stage. The wiring layer 44 which draws out the source potential of the source follower circuit 20 of the second stage is electrically connected to the signal output terminal 52.

When the total charge detection capacity including the gate electrode 37 electrically connected to the floating diffusion layer 12 of the signal charge detection unit 16 is Cfd and the amount of transmitted signal charge is Qsig, the floating diffusion layer 12 ), A potential variation ΔVfd is generated. Here, ΔVfd = Qsig / Cfd.

The potential change [Delta] Vfd changes the gate voltage at the gate electrode of the first MOSFET of the source follower circuits 18 and 20 in the first and second stages. As a result, a voltage change proportional to the signal charge Qsig is detected at the output terminal 52.

In recent solid state imaging devices, it is necessary to sufficiently secure the S / N ratio of the video signal, that is, reduce the charge detection capacity in order to increase the detection sensitivity.

However, in the conventional solid-state imaging device, as shown in Fig. 2, in order to prevent the occurrence of smears, it is manufactured to have a thin interlayer insulating film 49 that is not planarized. The influence of the capacitance between the gate and the wiring cannot be ignored.

The above-mentioned capacitance between the gate and the wiring corresponds to the capacitance between the gate electrode 37 and the wiring layers 41 and 43 in the first stage source follower circuit 18, and the second stage source follower circuit. It also corresponds to the capacitance between the gate electrode 38 and the wiring layers 42 and 44 at (20).

The capacitance described above is influenced by the distance between the gate electrode and the wiring layer. In Fig. 1, the distance between the wiring layer 41 and the gate electrode 37 for supplying the drain potential Vdd in the first stage source follower circuit 18 is represented by L1, and in the second stage source follower circuit 20 is shown. The distance between the wiring layer 42 and the gate electrode 38 for supplying the drain voltage Vdd is also represented by L1.

In Fig. 1, the wiring layer 41 is shown as separated from the gate electrode 37 for convenience of explanation. In reality, however, the wiring layer 41 extends to an upper position of the gate electrode 37 with the interlayer insulating film 49 interposed therebetween, as shown in FIG. Thus, the distance Ll becomes substantially zero.

The conventional solid-state imaging device having the above-described configuration has a problem in that, if it is provided with a small pixel having a small amount of handling charge, it is not sufficient to reduce the charge detection capacity, and thus it is not easy to obtain high sensitivity characteristics.

In view of the above-described problems, it is an object of the present invention to provide a solid state imaging device which sufficiently reduces the charge detection capacity and ensures high sensitivity even if the solid state imaging device includes a small pixel that handles a small amount of charge. have.

In the device for transferring charge according to the present invention, a wiring and a gate in which the distance L2 between the wiring for supplying the drain potential in the first stage MOSFET and the gate electrode supply the drain potential in the second stage or the next stage MOSFET is provided. It includes a plurality of MOSFETs characterized in that it is longer than the distance between the electrodes.

In addition, the solid-state imaging device according to the present invention includes a photoelectric conversion section (a) for converting light into electricity, a transfer section (b) for transferring the charge, and a floating diffusion layer (c) for converting the transferred charge into a voltage. And a multi-stage source follower circuit (d) for amplifying and outputting the voltage, wherein the distance L2 between the wiring for supplying the drain potential in the first-stage MOSFET and the gate electrode is the second stage or the next. It is characterized by being longer than the distance between the wiring for supplying the drain potential in the MOSFET at the stage and the gate electrode.

According to the present invention, it is possible to reduce the input capacitance of the gate electrode of the ultra-short source follower circuit, and in particular, it is possible to reduce the capacitance between the gate electrode and the drain wiring and the capacitance between the gate electrode and the source wiring.

1 is a cross-sectional view of a conventional solid-state imaging device.

Fig. 2 is a sectional view of a conventional solid state imaging device.

Fig. 3 is a sectional view of a solid state imaging device according to a first embodiment of the present invention.

Fig. 4 is a sectional view of a solid state imaging device according to a second embodiment of the present invention.

<Brief description of the main parts of the drawing>

10: three-phase drive charge transmitter 12: floating diffusion layer

14: reset MOSFET 16: signal charge detector

18: second stage source follower circuit 20: second stage source follower circuit

22: P-type semiconductor substrate 24: N-type semiconductor region

26, 28, 30: charge transfer electrode 32: gate electrode

34: reset gate electrode 36: N ⁺ type semiconductor region

37, 38: MOSFET gate electrode for charge detection

39, 40: MOSFET gate electrode for load

41, 42: Drain potential supply wiring

43, 44: source potential drawing wiring of MOSFET

45, 46: source potential supply wiring of MOSFET

48, 50: P-type semiconductor region 49, 51: interlayer insulating film

52: signal output terminal 53: wiring

First Embodiment

3 is a cross sectional view of a solid-state imaging device according to the present invention. As shown in Fig. 3, the solid-state imaging device includes a photoelectric conversion unit (not shown) for converting light into electric charge, a three-phase drive charge transfer unit 10 for transferring electric charge, and a reset MOSFET 14 And a two-stage source follower circuit including a signal charge detection unit 16 including a first stage source follower circuit 18 and a second stage source follower circuit 20.

The three-phase drive charge transfer unit 10 includes a P-type semiconductor substrate 22, an N-type semiconductor region 24 formed on the semiconductor substrate 22, and charge transfer pulses Φ 1, Φ 2, and Φ 3, respectively. The charge transfer electrodes 26, 28, and 30, and the gate electrode 32 to which the low voltage Vog generated at the output terminal of the charge transfer section 10 are applied.

The signal electrode 16 includes a P-type semiconductor substrate 22, a floating diffusion layer 12 formed on the P-type semiconductor substrate 22, an N-type semiconductor region 24 formed on the semiconductor substrate 22, and And an N ⁺ type semiconductor region 36 electrically connected to the reset power supply V _rd , and a reset gate electrode 34 to which a reset pulse voltage Φ is applied.

The ultra-short source follower circuit 18 includes a P-type semiconductor substrate 22, a gate electrode 37 of a first MOSFET for charge detection, a gate electrode 39 of a second depletion MOSFET serving as a load, A wiring layer 41 for supplying the drain potential, a wiring layer 43 for drawing the source potential of the first MOSFET, a wiring layer 45 for supplying the ground potential or the source potential of the second MOSTET, and an apparatus. Is composed of a high concentration P-type semiconductor region 48 that electrically isolates each region to be manufactured, and an interlayer insulating film 49 that electrically insulates the gate electrodes 37 and 39.

The second stage source follower circuit 20 includes a P-type semiconductor substrate 22, a gate electrode 38 of the first MOSFET for charge detection, and a gate electrode of the second MOSFET having a depletion type serving as a load. 40, the wiring layer 42 for supplying the drain potential, the wiring layer 44 for extracting the source potential of the first MOSFET, and the wiring layer 46 for supplying the ground potential or source potential of the second MOSTET. And a high concentration P-type semiconductor region 50 for electrically separating each region where the device is to be manufactured, and an interlayer insulating film 51 for electrically insulating the gate electrodes 38 and 39.

The floating diffusion layer 12 of the signal charge detector 16 is electrically connected to the gate electrode 37 of the first stage source follower circuit 18 through the wiring 53.

The drain power source Vdd is electrically connected to the wiring layers 41 and 42 of the source follower circuits 18 and 20 in the first and second stages. The wiring layer 43 which draws out the source potential of the source follower circuit 18 at the first stage is electrically connected to the gate electrode 38 of the source follower circuit 20 at the second stage. The wiring layer 44 for extracting the source voltage of the source follower circuit 20 of the second stage is electrically connected to the signal output terminal 52.

In the first embodiment according to the present invention, the distance L2 between the wiring layer 41 and the gate electrode 37 that supplies the drain potential Vdd in the ultrashort source follower circuit 18 is the second stage source. It is designed to be longer than the distance L1 between the wiring layer 42 for supplying the drain potential Vdd in the follower circuit 20 and the gate electrode 38. That is, the distance L2 is designed to be longer than the distance in the conventional solid state imaging device as shown in FIG.

In the solid state imaging device according to the first embodiment of the present invention, the charge detection capacitance C is the junction capacitance Cfd (a) between the floating diffusion layer 12 and the P-type semiconductor substrate 22 and the floating diffusion layer 12. ) And the wiring capacitance Cw (b) between the gate electrode 37 of the ultrashort source follower circuit 18, the input capacitance Ggw (c) of the gate electrode 37, the gate electrode 37 and the It is shown by the sum with the capacitance Cgd (d) between the wiring layer 41 and the drain region 60 extending between the gate electrode 37. FIG.

C = Cfd + Cw + Cgw + Cgd

If the first MOSFET for detecting charge in the first stage source follower circuit 18 is composed of an N-type channel transistor, the input capacitance Cgw of the gate electrode 37 is defined as follows.

Cgw = Cgw1 + (1-G) × Cgw2

Where G is the gain, Cgwl is the capacitance between the gate electrode 37 and the drain wiring layer 41, and Cgw2 is the capacitance between the wiring layer 43 and the gate electrode 37 to which the source voltage is supplied. Indicates.

Since the gain G of the source follower circuit is about 0.90, the input capacitance Cgw of the gate electrode 37 is more affected by the capacitance Cgwl than the capacitance Cgw2.

According to the first embodiment of the present invention, the distance L2 between the wiring layer 41 and the gate electrode 37 for supplying the drain voltage Vdd in the first stage source follower circuit 18 is the second stage source follower. It is longer than the distance L1 between the wiring layer 42 and the gate electrode 38 for supplying the drain voltage Vdd in the fishing circuit 20.

As a result, it is possible to reduce the input capacitance Cgw of the gate electrode 37 of the ultrashort source follower circuit 18, thereby ensuring the reduction of the charge detection capacitance C.

The inventor has confirmed through experiments that the solid state imaging device according to the first embodiment of the present invention can reduce the charge detection capacity C. By experiment, the inventor produced two solid state imaging devices. In the first solid state imaging device, the distances L1 and L2 were set to be close to zero. In the second solid state imaging device, the distance L2 was set to about 10.0 μm. In other words, the first solid-state imaging device means the thing according to the conventional invention, and the second solid-state imaging device means the thing according to the first embodiment according to the present invention. The second solid-state imaging device was able to reduce the charge detection capacitance C by about 15% compared with the first solid-state imaging device, that is, the invention according to the prior art.

Second Embodiment

Fig. 4 is a cross sectional view showing a second embodiment according to the present invention.

The solid state imaging device according to the second embodiment of the present invention has the same configuration as that of the solid state imaging device according to the first embodiment of the present invention. Elements or parts corresponding to those of the solid state imaging device shown in Fig. 3 are given the same reference numerals.

As a difference between the solid state imaging device according to the second embodiment of the present invention and the solid state imaging device according to the first embodiment of the present invention, the source voltage of the first MOSFET in the ultra-short source follower circuit 18 is described. The distance L3 between the wiring layer 43 and the gate electrode 37 for extracting the same is the wiring layer 44 and the gate electrode 38 for extracting the source voltage of the first MOSFET in the second stage source follower circuit 20. It's just designed to be longer than the distance between them.

According to the second embodiment of the present invention, it is also possible to reduce the charge detection capacity C.

The inventor has confirmed through experiments that the solid state imaging device according to the second embodiment of the present invention can reduce the charge detection capacity C. In the experiment, the inventor prepared two solid state imaging devices. In the first solid state imaging device, L2 was set to about 10 µm, and distances L1, L3, and L4 were set to zero. In the second solid state imaging device, the distances L2 and L3 were set to 10 m, and the distances L1 and L4 were set to zero. That is, the first solid state imaging device is meant according to the first embodiment according to the present invention, and the second solid state imaging device is meant according to the second embodiment according to the present invention. The second solid-state imaging device was able to reduce the charge detection capacitance C by about 10% compared with the first solid-state imaging device.

In the above-mentioned first and second embodiments, the case where the source follower circuit has two stages has been described, but it should be noted that the source follower circuit may be three or more stages. When the source follower circuit has three or more stages, the distance L2 of the first stage source follower circuit 18 is set longer than the distance Ll of the source follower circuit of the second stage or the next stage, The distance L3 was set longer than the distance L4 of the source follower circuit of the second stage or the next stage.

In the above-mentioned first and second embodiments, it is to be noted that although the source follower circuit is adopted as the output circuit, other amplifiers may be employed as the output circuit.

According to the present invention, in the charge transfer device which accumulates the signal charges transferred from the charge transfer unit in the detection capacitor, and amplifies the potential variation of the detection capacitor in an output circuit composed of a plurality of stages of the detection MOSFETs, it detects the first stage. Since the input capacitance of the gate electrode of the MOSFET can be reduced, there is an effect that the charge detection capacitance can be reduced and high sensitivity can be obtained even in a solid state imaging device having a small pixel size with a small handling charge amount.

Claims (8)

In the charge transfer apparatus, the distance L2 between the wiring 41 and the gate electrode 37 for supplying the drain potential in the first stage MOSFET 18 is set in the second stage or the next stage MOSFET 20. A charge transfer device comprising a plurality of MOSFETs longer than a distance L1 between a wiring for supplying a drain potential and a gate electrode. The charge transfer device of claim 1, wherein the distance L2 is 0 μm <L2 ≦ 30 μm. 3. The MOSFET L according to claim 1 or 2, wherein the distance L3 between the wiring 43 for extracting the source potential in the ultra-short MOSFET 18 and the gate electrode 37 is the second or next stage MOSFET. A charge transfer device characterized by being longer than the distance L4 between the wiring for extracting the source potential in (20) and the gate electrode. 4. The charge transfer device of claim 3, wherein the distance L3 is 0 μm < L3 &lt; 30 μm. In the solid state imaging device, (a) a photoelectric conversion unit for converting light into electric charges, (b) a charge transfer unit 10 for transferring the charges, (c) a floating diffusion layer 12 for converting the transferred charge into a voltage; (d) a multi-stage source follower circuit for amplifying and outputting the voltage; The distance L2 between the wiring 41 for supplying the drain potential in the MOSFET 18 at the first stage and the gate electrode 37 is for supplying the drain potential in the MOSFET 20 at the second or next stage. A solid-state imaging device comprising a plurality of MOSFETs longer than the distance L1 between the wiring and the gate electrode. The method of claim 5, The distance L3 between the wiring 43 for drawing the source potential in the first stage MOSFET 18 and the gate electrode 37 is for drawing the source potential in the second stage or the next stage MOSFET 20. A solid state imaging device, characterized in that it is longer than the distance L4 between the wiring and the gate electrode. The solid state image pickup device according to claim 5 or 6, wherein the distance L2 is 0 µm < L2 &lt; 30 µm. 7. The solid state imaging device according to claim 6, wherein the distance L3 is 0 mu m < L3 &lt; 30 mu m.