KR100779498B1 - Memory access apparatus and method for video codec - Google Patents

Abstract

The present invention relates to an apparatus and method for accessing a video codec, and a conventional video codec has a plurality of memory buffers for real-time processing and simultaneously accesses a memory, thereby increasing the cost of a video codec. In order to overcome this problem, there is a problem in that, when a memory is incorporated in the encoding or decoding chip, the cost of the chip is increased and the power consumption is increased. Accordingly, the present invention provides a block-based video codec for performing encoding and decoding, comprising: a PLL unit for receiving a pixel clock and generating a predetermined number of high-speed clocks; A memory controller and a coding controller for dividing the interval of the high-speed clock into a predetermined number of sections and appropriately allocating each functional block in the codec necessary for memory access to each high-speed clock section to access the memory A functional block requiring a memory access is occupied by each of the four memory access sections after dividing the memory access clock into a plurality of memory accesses, It is possible to minimize the size of the chip, the product unit price, and the power consumption.

Description

[0001] MEMORY ACCESS APPARATUS AND METHOD FOR VIDEO CODEC [0002]

1 is a block diagram showing a configuration of an encoding apparatus of a conventional video codec;

2 is a block diagram showing a configuration of a decoding apparatus of a conventional video codec;

3 is a timing diagram of a clock signal for explaining a memory access method of a video codec according to the present invention;

4 is a block diagram showing a memory access device of a video codec according to the present invention.

DESCRIPTION OF THE REFERENCE SYMBOLS

100: PLL unit 200: memory control unit

300: coding control unit 400: memory

The present invention relates to an apparatus and a method for accessing a memory of a video codec, and more particularly, to a memory access apparatus and method for a video codec that can perform a video codec function using only one external memory without using a plurality of external memories in a block- And more particularly, to a memory access apparatus and method of a memory access method.

Here, the fact that the block is based on means that the encoding unit is a macroblock (MB) of 16x16 pixels.

That is, the block-based video codec estimates a motion vector for each macroblock (MB) and performs information compression according to temporal picture correlation through a motion compensated inter-frame prediction method for each macroblock (MB) And performs spatial information compression by DCT (Discrete Cosine Transform) by dividing each macroblock (MB) into 8 × 8 pixel blocks.

Meanwhile, the basic encoding and decoding methods in the block-based video codec are generally performed through the process shown in FIG. 1 and FIG.

Hereinafter, the description of the technical structures of FIG. 1 and FIG. 2 will be omitted for the detailed operation of each block which may obscure the gist of the present invention.

1 is a block diagram showing a configuration of an encoding apparatus of a conventional video codec. As shown in FIG. 1, one frame is divided into macroblocks (MB), and the macroblocks are divided into 8x8 blocks and subjected to DCT, The motion vector is detected and quantized, and then encoded through variable length coding (VLC).

Next, FIG. 2 is a block diagram showing a configuration of a decoding apparatus of a conventional video codec. As shown in FIG. 2, decoding is performed in the reverse order of encoding.

Importantly, memory access for 8 × 8 blocks is required for DCT or IDCT, and memory accesses for 8 × 8 blocks or 16 × 16 macroblocks (MB) for motion vector (MV) Memory accesses are required.

Also, such memory accesses must be done simultaneously for real-time processing, not sequential.

Therefore, several memory buffers 22, 29, 47, and 49 are required for smooth encoding / decoding.

This increases the unit cost of the video codec. In order to overcome this problem, there is a problem of increasing the price of the chip and increasing the power consumption when the memory is incorporated in the encoding or decoding chip.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to at least partially solve the problems in the conventional arts. And to provide a method and apparatus for accessing a memory of a video codec.

According to an aspect of the present invention, there is provided a memory access apparatus for performing encoding and decoding in a block-based video codec, the memory access apparatus comprising: a PLL unit for receiving a pixel clock and generating an 8-times high- And a memory controller and a coding controller for dividing the interval of the high-speed clock into four sections and appropriately allocating each functional block in the codec necessary for memory access to each high-speed clock section to access the memory .

The present invention also provides a method and apparatus for generating a high-speed clock corresponding to eight times the pixel clock used as an input of each component requiring memory access and providing four clocks And a memory access privilege is given to each of the components during the divided clock periods to enable access at a high speed, thereby sharing one external memory.

In order to use a high-speed memory as an external memory, the present invention divides a section for accessing a memory into four sections and assigns a memory access right to each functional block in the chip for each section, .

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.                     

3 and 4, a high-speed clock of 8 times the pixel clock is generated by using the internal PLL 100, and the high-speed clock of 8 To perform four consecutive memory accesses.

This is because in the block-based codec, all memory accesses are based on 8 × 8 horizontally and vertically, so that 8 consecutive memory accesses can be used as a base unit.

That is, in the conventional case, in order to process encoding and decoding in real time, memory accesses are simultaneously performed in each functional block for 8 pixel clocks using several memories. However, in the present invention, a high speed (8 times) Clocks are generated and divided into a predetermined number (four) of memory access sections, and each functional block is sequentially accessed to one memory during each section, thereby achieving the same effect as simultaneous access for eight pixel clock periods .

At this time, the four sections are appropriately allocated for memory access for frame capture, frame display, DCT block read / write, IDCT block read / write, search area read and DPCM read / write functions do.

For example, frame capture and frame display are not used in the blank interval of a video signal. Therefore, memory access is required during the active period, and the remaining functions are not always generated at the same time. It depends on whether or not it is different, or various other variables, so it can be used in combination.                     

That is, as shown in FIG. 4, the coding control unit 300 and the memory control unit 200 determine which functional block makes the memory access in which high-speed clock period.

The coding control unit 300 makes a memory access request to the memory control unit 200 to perform a required function and the memory control unit 200 reads or writes the data requested by the coding control unit 300. [

4 is a block diagram of a memory access device of a video codec according to the present invention. The PLL unit 100 receives a pixel clock and generates a high-speed clock of a predetermined multiple, ) And the coding control unit 300 divides the high-speed clock interval into a predetermined number of intervals and appropriately allocates each functional block 500 to 800 requiring memory access to each interval to access the memory 400 .

In other words, in the conventional techniques shown in FIGS. 1 and 2, a plurality of buffers for memory access are provided, and the process of transferring the data in the external memory to the buffer or the data in the buffer is transferred to the external memory, The memory accesses are sequentially performed by the high-speed clock during the period 1 to the period 4 shown in FIG.

As described above, the memory access apparatus and method of the video codec of the present invention is a block-based video codec that generates a clock faster than a pixel clock by using a PLL, divides the clock into four memory access sections, A functional block requiring access needs to occupy each of the sections, and a frequent memory access by one external memory is realized at the same time as the input / output of a certain pixel, thereby minimizing the chip size, the product unit price, and the power consumption .

Claims (4)

CLAIMS 1. A memory access apparatus for performing encoding and decoding in a block-based video codec, the memory access apparatus comprising: a PLL unit for receiving a pixel clock and generating an 8-times high-speed clock; And a memory controller and a coding controller for dividing the interval of the high-speed clock into four sections and allocating each functional block in the codec requiring memory access to each high-speed clock section to access the memory. To the memory access device of the video codec. A memory access method for performing encoding and decoding in a block-based video codec, the memory access method comprising: generating a high-speed clock corresponding to eight times the pixel clock used as an input of each constituent unit requiring memory access; The memory unit is divided into four clock periods for allowing the memory unit to access the memory unit. The memory units are allowed to access the respective units during the divided clock periods, Wherein the memory access method comprises: The method of claim 2, wherein the block-based video codec is a codec based on 8 × 8 pixels. 3. The method of claim 2, wherein the high-speed clock causes four consecutive memory accesses to be performed four times during an eight-pixel period.

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