JPH09213692A - Fabrication of semiconductor integrated circuit through regional oxidation of silicon and structure of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for fabricating a semiconductor in which a bird's beak structure is not formed in the semiconductor insulating region. SOLUTION: A pad oxide layer is deposited on the upper surface of a semiconductor substrate 100 and a polysilicon layer 140 is deposited thereon. Subsequently, a second silicon nitride 200 is deposited on a first silicon nitride layer 160. The second silicon nitride layer 200 is deposited significantly thicker than the first silicon nitride layer 160. The second silicon nitride layer 200, the first silicon nitride layer 160 and the polysilicon layer 140 are then patterned in order to determine a mask. The mask includes the exposed region of pad oxide layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a kind of semiconductor integrated circuit and its manufacturing method. The present invention is a MOSFET
(MOS field effect transistor: metal oxi
de silicon field effect t
Although illustrated by way of example of a method and structure for insulating a device such as a transistor, the present invention has a much wider range of applications. To give an example, a bipolar transistor and a CMOSFET (complement)
ary metal oxide semiconductoru
center field effect transis
tor), BiCMOSFET (bipolar co
plementary metal oxide
miconductor field effect
Transistor) and the like.

[0002]

BACKGROUND OF THE INVENTION Traditionally, the industry has utilized device isolation techniques in integrated circuits and at the same time have made improvements. As one of such technologies, U.S.P. S. Philips
Corp .. United States Patent No. 3,970,4
Area oxidation of silicon (L
OCOS: local oxidation of s
Ilicon). To outline this LOCOS technique, first a silicon dioxide layer (SiO ₂ ) or pad oxide layer is formed on a silicon substrate, and a silicon nitride layer (Si ₃ N ₄ ) is formed on the silicon dioxide layer. Forming, and further patterning the silicon nitride layer to partially expose the pad oxide, the exposed pad oxide defining a field insulating oxide formation area, and further using silicon nitride as a mask, A thermal oxidation step forms field insulating oxide areas in the exposed areas of pad oxide. As shown in FIG.
In COS technology, the silicon dioxide is laterally oxidized to form a'bird's beak 'type structure that produces undesirable effects. FIG. 1 is a traditional field-insulating oxide structure 10 including a semiconductor substrate 11 field-insulating oxide area 13, an active area 17, and a bird's beak structure 15. As shown in the figure, this bird's beak structure hinders the formation of devices in the active area due to its thickness 19.

Various techniques have already been provided to overcome the undesirable effects of such bird's beak structures.
One of them is to increase the thickness of the bird's beak structure to prevent leakage between devices. However, if the bird's beak structure is thick,
The bird's beak becomes longer, that is, the bird's beak projects further into the active device area. The longer bird's beak also has the obvious undesirable consequence of reducing the device density of the integrated circuit.

Another technique is the "polybuffer".
There is a (poly-buffered) LOCOS method.
The polybuffer LOCOS method utilizes a multi-layer sandwich structure including an oxide layer, a polysilicon layer, and a nitride layer. This polybuffer LOCOS method can reduce lateral erosion of silicon dioxide. However, the polybuffer LOCOS method forms a secondary bird's beak type structure, as shown in FIG. FIG. 2 shows a traditional field insulating oxide region 20 made by the traditional polybuffer LOCOS method. This traditional method forms a semiconductor substrate field insulating oxide region 23, a primary bird's beak structure 25, and a secondary bird's beak structure 29. This polybuffer LOC
In addition to the OS method, the polysilicon etching residue 27
Has the disadvantage that it remains in the field insulating oxide area,
The secondary bird's beak type structure and the etching residue have obviously resulted in undesirable results.

In view of the above, there has been a demand for a highly reliable method capable of forming a semiconductor insulating area simply and at low cost.

[0006]

SUMMARY OF THE INVENTION The present invention is a reliable method for enhancing the quality of integrated circuits by providing semiconductor isolation areas that are simple, low cost, and substantially free of bird's beak structures. The challenge is to provide.

[0007]

According to a first aspect of the invention, there is provided a step of providing a semiconductor substrate having an upper surface, a step of forming a pad oxide layer on the upper surface of the semiconductor substrate, and a polysilicon layer on the pad oxide layer. Forming a first silicon nitride layer on the polysilicon layer;
A second silicon nitride layer thicker than the first silicon nitride layer,
Forming on the first silicon nitride layer, patterning the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer to define a mask that includes exposed areas of the pad oxide layer; Including the above steps,
The method is for manufacturing a semiconductor integrated circuit.

A second aspect of the present invention provides a method of manufacturing a semiconductor integrated circuit, further including the step of forming a field insulating oxide area in the exposed area.

According to a third aspect of the present invention, there is further provided a method of manufacturing a semiconductor integrated circuit, further comprising the step of forming a field insulating oxide region in the exposed region and removing the mask.

The invention of claim 4 is characterized in that the pad oxide layer is formed by a thermal oxidation process.

In the invention of claim 5, the first silicon nitride layer is a very thin silicon nitride layer having a thickness of about 100 angstroms or less.

The invention of claim 6 is characterized in that the first silicon nitride layer is formed with almost no pinholes.

In the invention of claim 7, the first silicon nitride layer is formed of a polysilicon layer by reacting a nitrogen supply source with silicon.

According to the invention of claim 8, the second silicon nitride layer is formed by a chemical vapor deposition method.

In the invention of claim 9, the thickness of the second silicon nitride layer is about 500 angstroms to about 3000.
Angstrom.

According to a tenth aspect of the invention, the mask is an oxidation mask.

According to the invention of claim 11, a semiconductor substrate having an upper surface, a pad oxide layer formed on the upper surface of the semiconductor substrate, a polysilicon layer formed on the pad oxide layer, and A first silicon nitride layer formed on the polysilicon layer and a second silicon nitride layer formed on the first silicon nitride layer to be thicker than the first silicon nitride layer; A structure of a semiconductor integrated circuit is characterized in that a silicon layer, the first silicon nitride layer and the polysilicon layer define a mask, the mask including exposed areas of the pad oxide layer.

A twelfth aspect of the present invention provides a structure of a semiconductor integrated circuit further including a field insulating oxide area limited to the exposed area.

In the thirteenth aspect of the present invention, the pad oxide layer is formed by a thermal oxidation process.

In the fourteenth aspect of the present invention, the first silicon nitride layer is a very thin silicon nitride layer having a thickness of about 100 angstroms or less.

In the fifteenth aspect of the invention, the first silicon nitride layer has substantially no pinholes.

According to the sixteenth aspect of the present invention, the first silicon nitride layer is formed of a polysilicon layer by reacting a nitrogen supply source with silicon.

According to the seventeenth aspect of the present invention, the second silicon nitride layer is formed by the chemical vapor deposition method.

In the invention of claim 18, the thickness of the second silicon nitride layer is about 500 angstroms to about 3000.
Angstrom.

In the nineteenth aspect of the invention, the mask is an oxidation mask.

According to a twentieth aspect of the present invention, a pad oxide layer is formed on the upper surface of the semiconductor substrate, a polysilicon layer is stacked on the pad oxide layer soil, and a reaction between the polysilicon layer and a nitrogen source is performed. First on the polysilicon layer
Forming a silicon nitride layer, forming a second silicon nitride 1 layer thicker than the first silicon nitride layer on the first silicon nitride layer by chemical vapor deposition, and forming the second silicon nitride layer
Patterning a silicon nitride layer, the first silicon nitride layer, and the polysilicon layer to define an oxidation mask that includes exposed areas of the pad oxide layer, the method including the steps of: The method is to form an insulating area.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is provided in the form of a method for forming a semiconductor integrated circuit. The method comprises depositing a pad oxide layer on a top surface of a semiconductor substrate, depositing a polysilicon layer on the pad oxide layer, and depositing a second silicon nitride layer on a first silicon nitride layer. To proceed. The second silicon nitride layer is provided much thicker than the first silicon nitride layer. Then, a patterning step for the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer to define a mask is also performed. The mask includes exposed areas of the pad oxide layer.

The invention is also provided in the form of a field insulating structure of silicon formed by the above method. that is,
A semiconductor substrate, an oxide layer deposited on the semiconductor substrate, a polysilicon layer deposited on the oxide layer, and a first silicon nitride layer formed on the polysilicon layer,
A second silicon nitride layer is formed on the first silicon nitride layer. In this embodiment, the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer define the mask. The mask includes exposed areas of the pad oxide layer.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 is a schematic vertical cross-section of a LOCOS structure according to the present invention. This electric field insulating structure is used for the semiconductor substrate 10.
0, field insulating oxide area 300, active device area 32
0, and other elements (not shown in the figure). As shown in the figure, the electric field insulating structure of the present invention provides a relatively flat surface as a location for active devices,
And it has almost no bird's beak structure. In particular, the length of the bird's beak structure is in the range of about 0.1 μ to about 0.3 μ for a thickness of the field oxide of about 0.3 μ to about 0.6 μ. The electric field insulation structure of the present invention is explained by the examples described below.

An example of the method of constructing the electric field insulating structure of the present invention will be described below. 1. A semiconductor substrate is provided. 2. A pad oxide layer (or oxide layer) is formed on the substrate surface. 3. A polysilicon layer is formed on the pad oxide layer. 4. Form a very thin film of high quality silicon nitride layer on the polysilicon layer. 5. Form a thick silicon nitride layer on a very thin film of high quality silicon nitride. 6. A thick silicon nitride layer, a very thin film of high quality silicon nitride, and a polysilicon layer are patterned to form exposed areas for forming field insulating oxide areas. 7. A field insulating oxide area is formed in the exposed area. 8. Remove the silicon nitride layer, polysilicon layer, pad oxide layer. 9. Proceed with the remaining process steps.

The above steps combine a polysilicon layer, a very thin film of high quality silicon nitride, and a thick silicon nitride layer to form one oxidation mask. The oxidation mask of the present invention causes almost no defects in the crystal in the semiconductor substrate during the process. Also, after removal of the silicon nitride and polysilicon layers, little polysilicon residue remains on the edges of the field insulating oxide areas. The oxidation mask of the present invention also prevents formation of holes on the active areas during subsequent processing. Moreover, the traditional bird's beak structure is largely eliminated by the method of the present invention. A detailed description of the method of the present invention is provided below with reference to the figures.

4 to 8 show a method of constructing an electric field insulating structure according to the present invention. These drawings are for the purpose of briefly explaining the constitution method of the present invention and do not limit the scope of the claims of the present invention.

FIG. 4 shows the starting point of the construction method according to the invention. The method of the present invention begins by providing a semiconductor substrate 100. The semiconductor substrate 100 may be a silicon wafer or any other suitable substrate, but is preferably a silicon wafer. Of course, the type of wafer used depends on the application.

In the method of the present invention, the silicon dioxide layer 120
Alternatively, a similar insulating layer (also known as a pad oxide layer) is formed on the upper surface 115 of the semiconductor substrate 100. The silicon dioxide layer 120 is formed by a silicon thermal oxidation technique, preferably at a temperature of about 1000.degree. C. or higher, and is of high quality without pinholes. The thickness of the silicon dioxide layer 120 is about 50 angstroms to about 500 angstroms, and preferably about 300 angstroms.

Further, the step of depositing the polysilicon layer 140 on the pad oxide layer upper surface 130 is performed. The polysilicon layer 140 is preferably low pressure chemical vapor deposition (L
PCVD: low pressure chemical
1 vapor deposition) or a technique similar thereto. According to the LPCVD technique, silane (SiH ₄ ) or a similar gas is used, and the pressure is in the range of about 100 mTorr to about 300 mTorr, preferably about 200 mTorr, at about 550 ° C. to about 700 ° C., preferably about 620 ° C. React at the temperature of. In the preferred embodiment, the polysilicon layer is formed to a thickness of about 300 Å to about 1500 Å. Of course, a special reaction,
Temperature, pressure, and others are determined by the application.

FIG. 5 briefly shows a method of forming the silicon nitride thin film 160 on the upper surface 155 of the polysilicon layer 140. The silicon nitride thin film 160 is a very thin thin film of high quality silicon nitride. A suitable technique for such silicon nitride layer construction is a polysilicon layer 16
0 is exposed to a gas of a nitrogen supply source such as high temperature ammonia (NH ₃ ) gas and is nitrided to form a very thin silicon nitride (Si ₃ N ₄ ) or a similar thin film from a polysilicon layer. Can be mentioned. The nitriding is about 700
C. to about 1100.degree. C., preferably about 950.degree. The ammonia gas used is about 0.1% to about 10
The concentration is 0%, preferably about 95%. The thickness of the formed silicon nitride thin film is about 5 angstroms to about 100 angstroms.
Angstroms, preferably about 30 Angstroms or less.

In the present invention, as shown in FIG. 6, a silicon nitride layer 200 is then formed on the top surface 1 of a very thin silicon nitride thin film.
90. This silicon nitride layer 200
Is formed by LPCVD or another suitable method. These methods use dichlorosilene (SiH ₂ C
l ₂ ) or ammonia gas or a similar reaction gas, and the amount is about 100 mTorr to about 500 mTorr.
r, preferably under a pressure of about 350 mTorr, and under a temperature of about 600 ° C. to about 800 ° C., preferably about 760 ° C. In the preferred method embodiment, silicon nitride layer 200 is formed to a thickness of from about 500 angstroms to about 3000 angstroms, preferably about 2000 angstroms. As shown, the method of the present invention utilizes a laminated structure including a polysilicon layer 140, a very thin silicon nitride layer 160, and a silicon nitride layer 200 to define an oxidation mask or the like. ing.

As further shown in FIG. 7, in the present invention, the polysilicon layer 140 and the very thin silicon nitride layer 16 are used.
0, and the laminated structure including the silicon nitride layer 200 is patterned by etching. The oxidation mask defines exposed areas 210 that define field insulating oxide areas and the like. Plasma etching, reactive ion etching, or the like is used for the etching, and preferably, the polysilicon layer 140, the very thin silicon nitride thin film 160,
An anisotropic pattern is formed on the silicon nitride layer 200 by plasma etching. The pad oxide layer may be an etch stop layer for plasma etching, or the pad oxide layer may be part of the oxidation mask.

The plasma etching technique is based on the Lam Reaseac of Fremont, California, USA.
It is performed in a plasma etching apparatus called a plasma etcher for products such as RAINBOW 4520 manufactured by h Company. Plasma etching is about 300mTo
rr to about 500 mTorr, preferably 400 mTor
Power at about 400 watts to about 700 watts, preferably 525 watts, at a pressure of rr. Then, a plasma etcher is performed using argon gas, oxygen gas, and trifluoromethane or a similar gas. The flow rate is about 100 sccm to about 400 sc
cm, preferably 320 sccm. About 10 sccm to about 50 sc when using trifluoromethane
The flow rate is cm, and preferably 20 sccm. About 10 sccm to about 200 sccm for oxygen gas
Flow rate of 50 sccm.
Of course, the type of reaction gas, flow rate, temperature, pressure, electric power and other conditions are determined according to the application.

In the present invention, the structure shown in FIG. 7 is further subjected to a thermal oxidation step to obtain the state shown in FIG. The thermal oxidation step is performed on a laminated structure such as the above-mentioned oxidation mask using a high temperature oxygen gas or a similar gas. The thermal oxidation is conducted at a temperature range of about 900 ° C. to about 1100 ° C., preferably 1000 ° C. for about 150 minutes to 190 minutes, preferably about 170 minutes or less. This thermal oxidation step forms a field insulating oxide region 300 having a thickness of about 4500 angstroms to about 6500 angstroms, preferably 5000 angstroms.

In the method of the present invention, the oxide mask is then removed according to the etching step sequence. In the method of the present invention, the removal treatment is performed with a hot phosphoric acid solution (H ₃ PO ₃ ) or the like. Then, the bad oxide layer is removed with diluted hydrofluoric acid or the like. Thus, the electric field insulating structure is formed, and the subsequent step is awaited. Of course, the technique used for removing the oxide mask is determined depending on the application.

Although the above describes one embodiment of the method of the present invention, various modifications, selectable configurations and those having equivalent effects can be used. For example, while the above description relates to a conventional field insulating oxide structure for field effect transistors, the present invention is directed to MOS circuits, B
It may also be implemented in an iMOS circuit, a bipolar circuit, an N to P well section of the circuit, or the like. Therefore, the above description is not intended to limit the claimed subject matter of the present invention.

[0043]

The method of the present invention combines a polysilicon layer, a very thin film of high quality silicon nitride, and a thick silicon nitride layer to form one oxidation mask. This oxidation mask causes almost no defects in the crystals on the semiconductor substrate during the process. Also, after removal of the silicon nitride and polysilicon layers, little polysilicon residue remains on the edges of the field insulating oxide areas. The oxidation mask of the present invention also prevents formation of holes on the active areas during subsequent processing. Moreover, the traditional bird's beak structure is largely eliminated by the method of the present invention.

[Brief description of drawings]

FIG. 1 is a conventional LOCOS structure diagram.

FIG. 2 is a conventional LOCOS structure diagram.

FIG. 3 is a schematic vertical sectional view of a LOCOS structure according to the present invention.

FIG. 4 is an explanatory diagram of a LOCOS structure forming method of the present invention.

FIG. 5 is an explanatory diagram of a LOCOS structure forming method of the present invention.

FIG. 6 is an explanatory diagram of a LOCOS structure forming method of the present invention.

FIG. 7 is an explanatory diagram of a LOCOS structure forming method of the present invention.

FIG. 8 is an explanatory diagram of a LOCOS structure forming method of the present invention.

[Explanation of symbols]

10 ... Electric field insulating oxide structure 11 ... Semiconductor substrate 13 ... Electric field insulating oxide area 15 ... Bird's beak structure 17 ... Active area 19 ... Thickness 20 ... Electric field insulating oxidation Object area 23 ... Semiconductor substrate electric field insulating oxide area 25 ...
Primary bird's beak type structure 27 ・ ・ ・ Polysilicon etching residue 29 ・ ・ ・
Secondary bird's beak type structure 100 ... Semiconductor substrate 300 ... Field insulating oxide area 320 ... Active device area 115 ... Semiconductor substrate upper surface 120 ... Silicon dioxide layer 130 ... Pad oxide Upper surface 140 ... Polysilicon layer 155 ... Upper surface of polysilicon layer 160 ... Very thin silicon nitride thin film 190 ...
Top surface of silicon nitride thin film 200 ... Silicon nitride layer 210 ... Exposed area

Claims (20)

[Claims] 1. A step of providing a semiconductor substrate having an upper surface, a step of forming a pad oxide layer on the upper surface of the semiconductor substrate, a step of forming a polysilicon layer on the pad oxide layer, a step of forming a polysilicon layer on the polysilicon layer. Forming a first silicon nitride layer, a second silicon nitride layer thicker than the first silicon nitride layer,
Forming on the first silicon nitride layer, patterning the second silicon nitride layer, the first silicon nitride layer, and a polysilicon layer to define a mask including exposed areas of the pad oxide layer; A method of manufacturing a semiconductor integrated circuit, comprising the above steps. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising forming a field insulating oxide area in the exposed area. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, further comprising forming a field insulating oxide region in the exposed region and removing the mask. 4. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the pad oxide layer is formed by a thermal oxidation process. 5. The first silicon nitride layer has a thickness of about 100.
The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the silicon nitride layer is a very thin silicon nitride layer having a thickness of angstrom or less. 6. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the first silicon nitride layer has substantially no pinholes. 7. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the first silicon nitride layer is a polysilicon layer and is formed by a reaction between a nitrogen supply source and silicon. 8. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the second silicon nitride layer is formed by a chemical vapor deposition method. 9. The thickness of the second silicon nitride layer is about 50.
The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the thickness is from 0 Å to about 3000 Å. 10. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the mask is an oxide mask. 11. A semiconductor substrate having an upper surface, a pad oxide layer formed on the upper surface of the semiconductor substrate, a polysilicon layer formed on the pad oxide layer, and a polysilicon layer formed on the polysilicon layer. A first silicon nitride layer formed on the first silicon nitride layer, and a second silicon nitride layer formed on the first silicon nitride layer to be thicker than the first silicon nitride layer. 1. A structure of a semiconductor integrated circuit, characterized in that a silicon nitride layer and a polysilicon layer define a mask, the mask including exposed areas of the pad oxide layer. 12. The structure of a semiconductor integrated circuit according to claim 11, further comprising a field insulating oxide area limited to the exposed area. 13. The structure of the semiconductor integrated circuit according to claim 11, wherein the pad oxide layer is formed by a thermal oxidation process. 14. The first silicon nitride layer has a thickness of about 10
The structure of the semiconductor integrated circuit according to claim 11, which is a very thin silicon nitride layer having a thickness of 0 angstrom or less. 15. The structure of a semiconductor integrated circuit according to claim 11, wherein the first silicon nitride layer has substantially no pinholes. 16. The structure of the semiconductor integrated circuit according to claim 11, wherein the first silicon nitride layer is a polysilicon layer formed by a reaction between a nitrogen supply source and silicon. 17. The structure of a semiconductor integrated circuit according to claim 11, wherein the second silicon nitride layer is formed by a chemical vapor deposition method. 18. The second silicon nitride layer has a thickness of about 5
The structure of the semiconductor integrated circuit according to claim 11, which is from 00 angstroms to about 3000 angstroms. 19. The structure of the semiconductor integrated circuit according to claim 11, wherein the mask is an oxidation mask. 20. A step of forming a pad oxide layer on a top surface of a semiconductor substrate; a step of depositing a polysilicon layer on the pad oxide layer; and a step of reacting the polysilicon layer with a nitrogen source on the polysilicon layer. Forming a first silicon nitride layer on the first silicon nitride layer, and forming a second silicon nitride layer thicker than the first silicon nitride layer by chemical vapor deposition.
Forming a silicon nitride layer on the first silicon nitride layer, and patterning the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer to expose the pad oxide layer A method of forming a field isolation area on a semiconductor substrate, comprising the steps of defining an oxidation mask that includes the area.