JPH04249324A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To obtain an element isolation method by which a high integration can be achieved, by which a leakage current is small and whose reliability is high by a method wherein a silicon oxide film is formed on the surface of a semiconductor substrate, the silicon oxide film is nitrified, an oxidation- resistant mask is then formed and a field oxide film is formed. CONSTITUTION:A silicon oxide film 2 is formed on the surface of a semiconductor substrate 1; the silicon oxide film 2 is nitrified; and a silicon oxide film 3 which contains nitrogen is formed. Then, an oxidation-resistant film 4 is formed; a heat treatment is executed in an oxidizing atmosphere; and a field oxide film 6 is formed. For example, a thermal oxide film 2 is formed on the surface of an Si substrate 1; after that, a heat treatment is executed in an ammonia atmosphere; the silicon oxide film 2 is nitrified; and a silicon oxide film 3 which contains nitrogen is formed. Then, a mask formed of a silicon nitride film 4 is formed; field ions are implanted; and an inversion-preventing impurity layer 5 is formed. After that, a heat treatment is executed in a steam atmosphere, and a field oxide film 6 is formed in a region which is revealed from the silicon nitride film 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to device isolation.

0002

2. Description of the Related Art In recent years, semiconductor integrated circuits have continued to become smaller and more highly integrated. Therefore, in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance of wiring, a thick insulating film is formed in the so-called field region between elements, and the elements are isolated by this insulating film.

As one example of this, the selective oxidation method (LOCOS method) is widely used as shown in FIG.

In this method, a thin silicon oxide film for stress buffering is formed on the main surface of a silicon substrate by a thermal oxidation method, and then a silicon nitride film is formed by a low pressure CVD method (LPCVD method). After forming an opening in the silicon nitride film, an anti-inversion layer is often formed by ion implantation, and finally selective oxidation is performed.

[0005] This method is carried out as follows.

First, as shown in FIG. 4, an n-type silicon substrate 101 is prepared, and after a thermal oxide film 102 with a thickness of about 50 nm is formed on the surface, a silicon nitride film 103 with a thickness of about 250 nm is sequentially formed. .

Thereafter, the silicon nitride film 103 in the field oxide film forming region is etched by a normal photoresist process.

Then, using this silicon nitride film 103 as a mask, field ion implantation is performed to form a p-type anti-inversion impurity layer 105. Here, boron was used as the implanted ion species, the acceleration voltage was 50 keV, and the dose was 1×
The ion implantation is performed under the condition of 1013 cm-2.

[0009] After this, oxidation is performed using a selective oxidation method,
A field oxide film 106 is formed in a region exposed from the silicon nitride film 103 as an oxidation-resistant film.

Then, the silicon oxide film 107 on the silicon nitride film formed at the same time as the field oxide film is etched with buffered hydrofluoric acid, and then the silicon nitride film 104 and the silicon oxide film 102 are removed.

Element isolation is performed in this way, but in order to remove the silicon nitride film 108, usually called a white ribbon, which is formed at the interface between the thin silicon oxide film 102 and the silicon substrate 101 during field oxide film formation. After removing the silicon oxide film 102, a thermal oxide film is formed and immediately etched.

[0012] After this, formation of element regions such as formation of a gate insulating film, formation of a gate electrode, etc. is performed.

In an element isolation method using such a LOCOS method, when the width of the element isolation region is less than 1 μm, the isolation ability between elements decreases, making it difficult to use for the following reasons.

The first reason is that the field oxide film 10
At the time of forming 6, the oxidation penetrates into the element forming region, forming a bird's beak 109, narrowing the element forming region, and making it impossible to narrow the width of the element isolation region. The length of the bird's beak 109 is determined by the thickness of the silicon oxide film 102 and the silicon nitride film 104, and the thickness of the field oxide film 10.
6 is known to depend on the formation temperature.

If the oxidation temperature is increased, the above-mentioned impurity distribution in the channel stopper becomes too wide, resulting in a problem that leakage current between adjacent transistors during operation becomes large.

Furthermore, if the thickness of the silicon oxide film 102 is made thin or the thickness of the silicon nitride film 104 is made large, crystal defects will easily enter the silicon substrate during the formation of the field oxide film 106, resulting in the formation of a transistor. There is a problem in that the leakage current of the source/drain pn junction increases later.

On the other hand, as one of the new element isolation technologies,
A trench is formed in the field region of the substrate and CVD is performed within the trench.
There is a method called the so-called box method, in which a silicon oxide film is buried and the surface is planarized.

Although this box method provides good isolation between elements, since the silicon oxide film is buried in the trench, stress increases due to the difference in coefficient of thermal expansion with the silicon substrate, and crystal defects are generated from the bottom of the trench. There was a problem that occurred. This causes leakage current to occur. Furthermore, when a MOSFET is formed in such an element isolation region,
The corners of the groove are inevitably exposed, and the electric field from the gate electrode is concentrated at the corner, causing the MOSFE to
There is a problem in that the threshold value of T decreases and the threshold characteristic has a hump.

In order to avoid such problems, FIG. 5(a)
), a method has also been proposed in which the leakage current caused by the above-mentioned crystal defects is suppressed by using a low stress material such as polycrystalline silicon as the filling material. This is done by embedding a polycrystalline silicon film 108 through a silicon oxide film 107 in a groove V formed on the surface of an n-type silicon substrate 101.
A silicon oxide film 109 is formed by surface oxidation, and this silicon oxide film 109 covers the silicon nitride film.

According to this method, since most of the material filled inside the groove is polycrystalline silicon, the stress caused by the difference in thermal expansion coefficients is reduced. However, since various oxidation processes are performed after embedding the polycrystalline silicon film, as shown in FIG. During this period, oxidation progresses in a wedge-like manner, resulting in the problem of crystal defects occurring within the substrate.

In addition, when a polycrystalline silicon film is embedded, if the insulation with the silicon substrate is broken even in one place, the stray capacitance of the wiring formed in the upper layer increases rapidly, making device operation unstable. be.

Furthermore, if the surface of the insulating film 109 after embedding is lower than the substrate surface of the element formation region, the corner portions of the grooves will be exposed, and therefore the transistors to be formed later will suffer from electric field concentration at these corner portions. happened,
There was a problem that the threshold voltage decreased.

[0023]

As described above, the conventional selective oxidation method has the problem that the length of the bird's beak increases, making it difficult to increase the degree of integration.

Furthermore, in the conventional device isolation method using the box method, oxidation progresses in a wedge-like manner between the polycrystalline silicon film and the silicon oxide film, causing crystal defects in the substrate and causing an increase in leakage current. There's a problem.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a highly reliable device isolation method that allows for high integration, has low leakage current, and is highly reliable.

[0026]

[Means for Solving the Problems] Accordingly, in the first aspect of the present invention, when performing element isolation by the LOCOS method, a silicon oxide film is formed for stress buffering before forming an oxidation-resistant mask, and then, for example, this film is By exposing to a high temperature ammonia or nitrogen gas atmosphere, the vicinity of the interface between the silicon oxide film and the silicon substrate, the surface of the silicon oxide film, and the inside of the silicon oxide film are nitrided, thereby suppressing lateral oxidation during field oxidation and preventing the growth of bird's beaks. We are trying to suppress this.

In the second aspect of the present invention, after forming a groove on the substrate surface and oxidizing the groove surface to form a silicon oxide film,
For example, the vicinity of the interface between the silicon oxide film and the silicon substrate, the surface of the silicon oxide film, and the inside of the silicon oxide film are nitrided by exposing to a high temperature ammonia or nitrogen gas atmosphere.

[0028]

[Operation] According to the first method, nitriding treatment is performed prior to forming a silicon nitride film as a mask for field oxidation. This nitriding treatment is performed before the impurity introduction step and can be performed at high temperatures, allowing for sufficient treatment. Therefore, during field oxidation to be performed later, it becomes difficult for the oxidizing agent that has entered through the silicon nitride film opening on the element isolation region to reach the element formation region, and it is possible to suppress the progress of oxidation in the lateral direction.

Furthermore, even after the nitriding process, since the film composition is such that the silicon oxide film contains only a few percent of nitrogen atoms, crystal defects may occur in the silicon substrate due to the stress caused by the nitrided portion of the silicon oxide film during field oxidation. There's nothing to do.

According to the second aspect of the present invention, by nitriding the inner wall of the trench, wedge-shaped oxidation is prevented from progressing between the silicon oxide film and the polycrystalline silicon film and between the silicon oxide film and the silicon substrate. This also eliminates the occurrence of leakage due to crystal defects.

[0031]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a process diagram for forming an element isolation region according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a p-type (100) silicon substrate 1 having a resistivity of 5 to 50 Ω·cm is prepared, and a thermal oxide film 2 with a thickness of about 50 nm is formed on the surface.

Thereafter, heat treatment is performed at 1200° C. for 1 minute in an ammonia atmosphere to nitride the silicon oxide film 2 to form a silicon oxide film 3 containing nitrogen.

Next, the film thickness was 150 nm by LPCVD method.
A silicon nitride film 4 with a thickness of about m is formed, the silicon nitride film 4 in the field oxide film formation region is etched away by a normal photoresist process, and field ion implantation is performed using the silicon nitride film 4 as a mask to form a p-type An anti-inversion impurity layer 5 is formed (FIG. 1(b)). Here, boron was used as the implanted ion species, and the acceleration voltage was 50k.
The ion implantation is performed under the conditions of eV and a dose of 1×10 13 cm −2 .

After that, as shown in FIG. 1(c), 10
A heat treatment is performed for 6 hours in a steam atmosphere at 00° C. (selective oxidation) to form a field oxide film 6 in a region exposed from the silicon nitride film 4 as an oxidation-resistant film.

Then, the silicon oxide film 7 on the silicon nitride film 4 formed at the same time as the field oxide film is etched with buffered hydrofluoric acid for one minute, and then the silicon nitride film 4 is removed by chemical dry etching.

Next, in order to remove the silicon nitride film 8 which is usually called a white ribbon formed during oxidation, heat treatment is performed for 1 minute in an oxygen atmosphere at 1200° C. to form a sacrificial thermal oxide film. Immediately perform etching with buffered hydrofluoric acid.

After this, as shown in FIG. 1(d), a new silicon oxide film with a thickness of 20 nm, which will become the gate insulating film 9, is formed, and ion implantation for threshold control for transistor formation is performed at an accelerating voltage of 100 keV. , dose 1×101
After carrying out the process under the condition of 2 cm -2 , the transistor formation process is continued.

The element isolation region thus formed is subjected to nitriding treatment prior to the formation of a silicon nitride film as a mask for field oxidation. Oxidation does not proceed even in the case of high integration, the growth of bird's beak can be reduced, and reliability can be maintained favorably even in the case of high integration.

Even after the nitriding process, since the film composition is such that the silicon oxide film contains only a few percent of nitrogen atoms, crystal defects may occur in the silicon substrate due to the stress caused by the nitrided portion of the silicon oxide film during field oxidation. There's nothing to do.

Embodiment 2 FIG. 2 is a process diagram for forming an element isolation region according to a second embodiment of the present invention.

In this method, in Example 1, a silicon nitride film 4 was formed as a field oxidation mask by LPCVD after nitriding the silicon oxide film 2, but in this case, a polycrystalline silicon film was formed before forming this silicon nitride film. 11
The only difference is that this polycrystalline silicon film is nitrided again at high temperature to form a silicon nitride film 12, and then a silicon nitride film 4 is formed, and these three layers are patterned simultaneously. The same is true for everything else.

That is, first, as shown in FIG. 2(a), a p-type (100) silicon substrate 1 with a specific resistance of 5 to 50 Ω·cm is prepared, and a thermal oxide film 2 with a thickness of about 50 nm is formed on the surface. .

Thereafter, heat treatment is performed at 1200° C. for 1 minute in an ammonia atmosphere to nitride the silicon oxide film 2 to form a silicon oxide film 3 containing nitrogen.

[0046] Next, a film with a thickness of 50 nm was formed by the LPCVD method.
After forming a polycrystalline silicon film 11 of approximately
Heat treatment is performed in an ammonia atmosphere at 00° C. for 1 minute to nitride the surface of this polycrystalline silicon film 11 to form a silicon nitride film 12 having a thickness of 2 to 3 nm. Furthermore, a silicon nitride film 4 with a thickness of about 150 nm is formed by the LPCVD method, and the silicon nitride film 4 in the field oxide film formation region is etched away by a normal photoresist process. Using this silicon nitride film 4 as a mask, field ion A p-type anti-inversion impurity layer 5 is formed by implantation (FIG. 2(b)).
). Here, boron is used as the implanted ion species, and the ion implantation is performed under conditions of an acceleration voltage of 50 keV and a dose of 1.times.10@13 cm@-2.

After this, as shown in FIG. 2(c), 10
A heat treatment is performed for 6 hours in a steam atmosphere at 00° C. (selective oxidation) to form a field oxide film 6 in a region exposed from the silicon nitride film 4 as an oxidation-resistant film.

Then, the silicon oxide film 7 on the silicon nitride film 4 formed at the same time as the field oxide film is removed by etching with buffered hydrofluoric acid for 1 minute, and then the silicon nitride film 4 is removed by chemical dry etching. do. Furthermore, the silicon nitride film 12 and the polycrystalline silicon film 11 are removed.

Next, in order to remove the silicon nitride film 8 which is usually called a white ribbon formed during oxidation, heat treatment is performed for 1 minute in an oxygen atmosphere at 1200° C. to form a sacrificial thermal oxide film. Immediately perform etching with buffered hydrofluoric acid.

After this, as shown in FIG. 2(d), a new silicon oxide film with a thickness of 20 nm is formed to become the gate insulating film 9, and ion implantation is performed to control the threshold value for forming a transistor. , and then continues the transistor formation process.

In this process, the amount of oxygen consumed by the oxidation of the polycrystalline silicon film 11 is large, so that the oxidizing agent is prevented from reaching the element formation region. Therefore, the growth of bird's beak can be further suppressed than in Example 1, and the reliability can be further improved even in the case of high integration.

Furthermore, even after nitriding, since the film composition is such that the silicon oxide film contains only a few percent of nitrogen atoms, crystal defects may occur in the silicon substrate due to the stress caused by the nitrided portion of the silicon oxide film during field oxidation. There's nothing to do.

Furthermore, in this example, the polycrystalline silicon film 11
Lateral oxidation in the polycrystalline silicon film 11 can be suppressed by the nitrogen-containing silicon oxide film 12 formed on the surface, and reliability can be significantly improved in high integration.

Embodiment 3 Next, a process for forming a semiconductor device according to a third embodiment of the present invention will be described. First, as shown in FIG. 3(a), a p-type (100) silicon substrate 1 with a specific resistance of 5 to 50 Ωcm is prepared, and a thermal oxide film with a thickness of about 20 nm and a silicon oxide film with a thickness of about 10 nm are coated on the surface. These oxide films are then nitrided in the same manner as in Examples 1 and 2 to form silicon oxide films 21 and 22 containing nitrogen, respectively. Furthermore, a polycrystalline silicon film 23 with a film thickness of about 0.2 μm, a silicon nitride film 24 with a film thickness of about 10 nm, a CVD silicon nitride film 25 with a film thickness of about 10 nm, and a CVD silicon oxide film 26 are sequentially formed, and these multilayer films are On the other hand, a groove with a width of 0.5 μm is formed using lithography and etching techniques, and a groove 27 with a depth of 0.5 μm is formed by reactive ion etching using this as a mask.

After this, as shown in FIG. 3(b), 10
A film thickness of approximately 50n was formed on the inner wall of the groove by thermal oxidation at 00°C for 10 minutes.
3(c).
As shown in FIG. 2, heat treatment is performed at 1200° C. for 1 minute in an ammonia atmosphere to nitride the silicon oxide film 28 to form a silicon oxide film 28a containing nitrogen.

Further, as shown in FIG. 3(d), C
A polycrystalline silicon film 29 having a thickness of about 0.4 μm is deposited by the VD method.

After that, by reactive ion etching,
Etch back and etch the polycrystalline silicon film 29 until the surface of the CVD silicon oxide film 26 is exposed,
The polycrystalline silicon film 29 is planarized and left in the trench. Then, by wet etching method, this C
The VD silicon oxide film 26 is removed by etching.

Furthermore, as shown in FIG. 3(e), 100
Thermal oxidation is performed in an oxidizing atmosphere at 0° C. to form a silicon oxide film with a thickness of about 0.2 μm on the surface of this polycrystalline silicon film 29. This silicon oxide film 29a is formed to be thick in consideration of various later etching steps. Then, heat treatment is further performed for 1 minute in an ammonia atmosphere at 1200° C., and this silicon oxide film is nitrided using the CVD silicon nitride film 25 as a mask to form a nitrogen-containing silicon oxide film 30.

After this, as shown in FIG. 3(f), the multilayer film used as a mask is sequentially etched to form a new silicon oxide film 9 with a thickness of 20 nm, which will become a gate insulating film, and is used to form a transistor. After performing ion implantation for threshold control, the transistor formation process continues.

In the element isolation region thus formed, the upper part of the nitrogen-containing silicon oxide film covering the surface of the polycrystalline silicon film formed in the trench protrudes from the substrate surface. This eliminates the exposure of the MOSFET, and it becomes possible to obtain a MOSFET with good characteristics without hump characteristics.

It should be noted that in the above embodiment, since nitrogen easily enters the CVD silicon oxide film, the effect of suppressing oxidant diffusion is remarkable.

The material for the buried layer may be not only polycrystalline silicon but also an insulating film such as a silicon oxide film, a BPSG film, or a silicon nitride film, and it is particularly desirable to use a material with a coefficient of thermal expansion close to that of the substrate. .

[0063]

[Effects of the Invention] As explained above, the first aspect of the present invention
According to , since the nitriding process is performed before forming the silicon nitride film as a mask for field oxidation, lateral oxidation is suppressed, the element isolation region can be miniaturized, and high density can be easily achieved. .

According to the second aspect of the present invention, the inner wall of the trench is nitrided prior to forming the buried layer, so that there is no nitridation between the silicon oxide film and the buried material or between the silicon oxide film and the silicon substrate. Progress of wedge-shaped oxidation is suppressed, and there is no leakage due to crystal defects, improving reliability.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an element isolation process in a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an element isolation process according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an element isolation process according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a conventional element isolation method.

FIG. 5 is a diagram showing a conventional element isolation method.

[Explanation of symbols]

1 P-type silicon substrate 2 Silicon oxide film 3 Silicon oxide film containing nitrogen 4 Silicon nitride film 5 Channel stopper layer 6 Field insulation film 7 Silicon oxide film 9 Gate insulating film 11 Polycrystalline silicon film 12 Silicon nitride film 21 Thermal oxide film containing nitrogen 22 Silicon oxide film containing nitrogen 23 Polycrystalline silicon film 24 Silicon nitride film 25 CVD silicon nitride film 26 Silicon oxide film 27 Groove 28 Silicon oxide film 28a Silicon oxide film containing nitrogen 29 Polycrystalline silicon film 30 Silicon oxide film containing nitrogen

Claims (2)

[Claims] 1. A silicon oxide film forming step of forming a silicon oxide film on the surface of a semiconductor substrate, a nitriding step of nitriding the silicon oxide film to form a silicon oxide film containing nitrogen, and forming an oxidation-resistant mask. A method of manufacturing a semiconductor device, comprising a mask forming step and a selective oxidation step of performing heat treatment in an oxidizing atmosphere to form a field oxide film. 2. A trench forming step of forming a trench on the surface of a semiconductor substrate, an oxidizing step of forming a silicon oxide film on the surface of the trench, and a nitriding step of nitriding the silicon oxide film to form a silicon oxide film containing nitrogen. and a filling step of filling the trench with a filling material.