JPH09203659A - Bolometer type infrared detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the reduction in variations by a method wherein a ground terminal and an output terminal are arranged diagonally to each other so that paths of current flowing to pixels are almost diagonal in a plurality of pixels to uniformize the wiring resistance of the current paths in the individual pixels. SOLUTION: A ground terminal (power source terminal) GND and an output terminal OUT are arranged diagonal to each other, the sources of MOS transistors Q in pixels P11 , P12 ... and Pmn are connected to source lines S1 , S2 ... and Sn and a common horizontal source line S0 is connected to the ground terminal GND to uniformize the lengths of all electric paths passing through the pixels P11 , P12 ... Pmn between the ground terminal GND and the output terminal OUT. Moreover, the wiring widths of signal lines Y1 , Y2 ... and Yn and the source lines S1 , S2 ... Sn are all the same while those of a horizontal signal line Y0 and the common source S0 are made equal. This makes possible the uniformization of the resistance wires passing through any pixels P11 , P12 ... Pmn between the ground terminal GND and the output terminal OUT thereby eliminating variations between the pixels P11 , P12 ... Pmn .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bolometer type infrared detector.

[0002]

2. Description of the Related Art In general, infrared detectors are widely used for crime prevention, surveillance, guidance, medical care, industrial measurement and the like. FIG. 25 shows a two-dimensional bolometer type infrared detection device already proposed by the applicant (see: Japanese Patent Application No. 6-189144).
No., filed on August 11, 1994). In FIG. 25, signal lines X ₁ , X ₂ ,-, X _m are arranged in parallel in the X direction, and signal lines Y ₁ , Y ₂ ,-, Y _n and source lines S ₁ , S ₂ ,-, S _n. Are arranged parallel to the Y direction. In addition, the source line S ₁ ,
S ₂ , ..., S _n are grounded.

The pixel P _ij has signal lines X ₁ , X ₂ ,-, X _m and signal lines Y ₁ , Y ₂ ,-, Y _n (source lines S ₁ , S ₂ ,-, S _n ).
It is provided at the intersection with. For example, pixel P ₂₂
Is composed of an N-channel MOS transistor Q and a bolometer R. In this case, the MOS transistor Q
Is grounded, the drain of the MOS transistor Q is connected to the signal line Y ₂ via the bolometer R, and further the output terminal OUT is connected via the transfer gate TG _2.
It is connected to the. The gate of the MOS transistor Q is connected to the signal line X ₂ .

The bolometer R is made of titanium or its alloy. As a result, the 1 / f noise when the current flows through the bolometer R can be reduced, so that the sensitivity and the S / N ratio can be improved. Further, since the bolometer R using titanium has a small specific resistance, thermal noise can be reduced. Further, since the resistance change per unit temperature and the thermal conductivity are small, the sensitivity can be improved.

Further, since the bolometer R is connected to the drain of the MOS transistor Q, the resistance of the bolometer R determines the current flowing through the MOS transistor Q, so that 1 / f noise, which is a variation in resistance, is hardly observed. . The bolometer R is connected to the ground terminal GND and the MOS.
If it is connected between the source of transistor Q and M
When the OS transistor Q is turned on, the voltage drop by the bolometer R raises the source potential of the MOS transistor Q, and as a result, the ON resistance of the MOS transistor Q rises and 1 / f noise increases. .

Further, transfer gates TG ₁ and TG composed of P-channel MOS transistors and N-channel MOS transistors are provided between the signal lines Y ₁ , Y ₂ , ..., Y _n and the horizontal signal line Y _O, that is, the output terminal OUT. ₂ , ─, TG
_n is connected. In this case, the current flowing through the bolometer R depends on the required signal amount, and therefore the voltage drop across the bolometer R depends on this signal amount. As a result,
The operating points of the transfer gates TG ₁ , TG ₂ , ..., TG _n change according to the corresponding bolometer R. However, in the P-channel MOS transistor of each transfer gate, the on-resistance is large when the source potential is small, while in the N-channel MOS transistor, the on-resistance is small when the source potential is small. Therefore, at any operating point, the on-resistance of each transfer gate is small, and 1 / f noise can be minimized.

The signal lines X ₁ , X ₂ ,-, X _m are sequentially selected by the vertical register 1 and AND circuits 2-1, 2-2,-, 2-m. For example, when the output signal φ _V2 of the vertical shift register 1 is “1” (high level), the signal line X
The voltage of 2 is made high (= V _V ). For example, V _V = 5
V. The vertical shift register 1 has a vertical synchronizing signal V _SYNC.
Is received, and a horizontal synchronizing signal H _SYNC is received and shifted.

The signal lines Y ₁ , Y ₂ , ..., Y _n are sequentially selected by the horizontal register 3 and AND circuits 4-1, 4-2 ,. For example, when the output signal φ _H2 of the horizontal shift register 3 is “1” (high level), the output of the AND circuit 4-2 is made high (= V _H ). For example,
V _H = 5V. The horizontal shift register 3 receives the horizontal synchronizing signal H _SYNC 'and shifts it by receiving the synchronizing clock signal SCK.

The horizontal sync signal H _SYNC 'is the horizontal sync signal H
_SYNC is delayed by the horizontal blanking time T _B. Therefore, the delay circuit 5 having the delay time T _B is provided. That is, the signal lines X ₁ , X ₂ ,-, X _m are made of, for example, polysilicon having a relatively large resistance value, and the signal lines Y ₁ , Y ₂ ,-, Y _n and the source lines S ₁ , S ₂ ,-, S _n
Is made of, for example, aluminum or its alloy having a relatively low resistance value. Also, the signal lines X ₁ , X ₂ , ─, X _m
Has a large capacitance including the gate capacitance of the MOS transistor Q. Therefore, the time constant of the voltage of the signal lines X ₁ , X ₂ ,-, X _m is larger than the time constant of the voltage of the signal lines Y ₁ , Y ₂ ,-, Y _n . Therefore, in order to perform a sufficient horizontal operation after applying the pulse to the signal lines X ₁ , X ₂ , ..., X _m , it is necessary to delay the horizontal synchronizing signal H _SYNC .

The output terminal OUT is connected to the integrating circuit 6. The integrating circuit 6 includes a bipolar transistor 61 having an emitter connected to the output terminal OUT, a capacitor 62 connected to the collector of the bipolar transistor 61, and a reset transistor 6 connected to the capacitor 62.
Consists of three. The bipolar transistor 61 is operated by the integrated bias signal φ _B corresponding to the respective operating times of the transfer gates TG ₁ , TG ₂ , ..., TG _n . Further, the reset transistor 63 operates by the signal φ _R and sets the integrated output signal S _OUT of the integrating circuit 6 to V _R.

In the integration circuit 6, the integration time T _S determined by the integration bias signal φ _B is determined by the transfer gate T determined by one period of the synchronous clock signal SCK.
G _1, TG _2, ─, less than the operating time of the TG _n, thereby, the transfer gate TG _1, TG _2, ─, to remove random noise and fixed pattern caused by variations in the operating time of TG _n. The integration period T _S is determined by the width of the pulse output from the horizontal shift register 3, and assuming that the base voltage of the bipolar transistor 61 is constant, the MOS transistor of the horizontal shift register 3 and the AND circuit 4-1. , 4-2,-, 4-n cause variations in the operation of the MOS transistor Q of the pixel, resulting in variations in self-heating of the bolometer, and random noise and fixed pattern noise.

The voltage applied to one pixel composed of the MOS transistor Q and the bolometer R is the difference voltage between the emitter of the bipolar transistor 61 and the ground terminal GND, that is, the difference voltage between the base of the bipolar transistor and the ground terminal GND minus. It is determined by the voltage obtained by subtracting the built-in voltage of the bipolar transistor. Therefore, the voltage of the integrated output signal S _OUT is separated from each pixel. As a result, when the integration period T _S is increased to reduce noise, or when the current flowing through the bolometer is increased to increase sensitivity, the amount of charge stored in the capacitor 62 is increased. However, in this case, the reset voltage V _R can be set independently of the voltage applied to the pixel. In this way, the state of the bolometer R can be read.

[0013]

However, in the bolometer type infrared detecting device of the above-mentioned prior application, the source of the MOS transistor Q of each pixel P _ij is set for each source line S ₁ , S ₂ ,-, S _n . It is grounded. Therefore, when sequentially reading each pixel P _ij , each pixel P _ij is read from the ground terminal.
_In each current path to the output terminal OUT via _ij , the wiring resistance related to the horizontal signal line Y ₀ varies depending on the pixel. In the first place, since the change in the resistance of the bolometer R due to the incident infrared rays is slight, there is a problem that the above-mentioned variation in the wiring resistance causes a large variation between pixels. The signal lines Y ₁ , Y ₂ ,-, Y _n , the source lines S ₁ , S ₂ ,
─, S _n and horizontal signal line Y ₀ are made of aluminum or an alloy thereof to reduce the resistance and reduce the variation of the wiring resistance, the variation of the wiring resistance remains and it is not possible to eliminate the variation between pixels. It is enough. Therefore, the object of the present invention is to
It is to provide a bolometer type infrared detection device in which variations between pixels are reduced.

[0014]

In order to solve the above-mentioned problems, the present invention is one in which a current path flowing in each pixel is substantially diagonal in a group of a plurality of pixels.

[0015]

1 is a circuit diagram showing a first embodiment of a bolometer type infrared detecting device according to the present invention. In FIG. 1, the ground terminal GND and the output terminal OUT
And are arranged diagonally to each other. This equalizes the lengths of the electrical paths between any of the pixels P _ij between the ground terminal GND and the output terminal OUT. Further, the signal lines Y ₁ , Y ₂ ,-, Y _n and the source lines S ₁ , S ₂ ,-, S _n.
And the horizontal signal line Y ₀ and the horizontal source line S ₀ have the same wiring width.

In this case, the vertical lines Y ₁ , Y ₂ ,
It is not necessary that the wiring widths of Y _n , S ₁ , S ₂ , ..., S _{n be the same as} the wiring widths of the horizontal lines Y ₀ , S ₀ . For example the vertical line Y
_In order to increase the aperture ratio of the pixel (ratio of the light receiving area to the pixel area) ₁ , Y ₂ , ..., Y _n use thin wiring of several μm. Further, since the horizontal lines Y ₀ and S ₀ have a relatively large space, the resistance is reduced by using thick wiring of several tens of μm. In this way, the resistance of the wiring that passes through any pixel P _ij between the ground terminal GND and the output terminal OUT is equalized. Output terminal OUT with ground terminal GND
Does not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by the dotted line. In short, it _suffices that the current flowing through the pixel P _ij flows substantially diagonally from the lower right to the upper left of the figure on the device (chip), and the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 2A is a detailed circuit diagram of the vertical shift register 1 of FIG. That is, the D flip-flops 1-1, 1-2, ..., 1-m are connected in series. D
Flip-flop 1-1 receives the vertical sync signal V _SYNC , while all D flip-flops 1-1, 1-
2,-, 1-m are operated by the horizontal synchronizing signal H _SYNC . As a result, the vertical shift register 1 sequentially generates the vertical selection signals φ _V1 , φ _V2 ,-, φ _Vm , and the signal lines X ₁ , X ₂ ,
-, X _m are sequentially selected to operate.

FIG. 2B is a detailed circuit diagram of the horizontal shift register 3 shown in FIG. That is, the D flip-flops 3-1, 3-2, ..., 3-n are connected in series. D
The flip-flop 3-1 receives the horizontal synchronizing signal H _SYNC ', while all the D flip-flops 3-1 and 3- are provided.
2,-, 3-n are operated by the synchronous clock signal SCK. As a result, the horizontal shift register 3 sequentially generates horizontal selection signals φ _H1 , φ _H2 ,-, φ _Hn , and the signal lines Y ₁ ,
Y ₂ , ..., Y _n are sequentially selected and operated.

The operation of the bolometer type infrared detector of FIG. 1 will be described with reference to FIG. The vertical shift register 1 has a vertical synchronizing signal V _SYNC shown in FIG. 3A and a vertical synchronizing signal V _SYNC shown in FIG.
When the horizontal synchronizing signal H _SYNC shown in FIG. 3 is received, vertical selection signals φ _V1 , φ _V2 , φ _V3 , ─, φ _Vm are received as shown in (C), (D), (E), and (F) of FIG. It occurs sequentially. As described above, the horizontal synchronizing signal H _SYNC is delayed by the delay circuit 5 and becomes the horizontal synchronizing signal H _SYNC ′ shown in (G) and (H) of FIG. 3H is a partially enlarged view of FIG. 3G.

When the horizontal shift register 3 receives the horizontal synchronizing signal H _SYNC 'shown in (H) of FIG. 3 and the synchronizing clock signal SCK shown in (I) of FIG. 3, (J) of FIG.
As shown in (K), (L), and (M), the horizontal selection signal φ
_H1 , φ _H2 , φ _H3 ,-, φ _Hn are sequentially generated.

The integrated bias signal φ _B shown in (N) of FIG. 3 is input to the bipolar transistor 61, and the reset signal φ _R shown in (O) of FIG. 3 is input to the reset transistor 63 after each integration period T _S. To do. As a result, the integrated output signal S _OUT shown in (P) of FIG. 3 is obtained.

FIG. 4 shows a modification of the bolometer type infrared detecting device of FIG. In FIG. 4, the ground terminal GND and the output terminal OUT are diagonally arranged on the device (chip) by a method different from that in FIG. Further, instead of the transfer gates TG ₁ , TG ₂ , ・ ・ ・, TG _n in FIG. 1, N-channel MOS transistors G ₁ , G ₂ , ・ ・ ・, G
_n is provided. Thus, also in FIG. 4, any pixel P between the ground terminal GND and the output terminal OUT is
_Equalize the resistance of the wiring that passes through _ij . Also in FIG. 4, the ground terminal GND and the output terminal OUT do not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by the dotted line. In short, it _suffices that the current flowing through the pixel P _ij flows substantially diagonally from the upper right corner to the lower left corner of the drawing on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 5 is a circuit diagram showing a second embodiment of a bolometer type infrared detecting device according to the present invention. In FIG. 5, an output terminal OUT ′ and an integrating circuit 6 ′ connected to the output terminal OUT ′ are added to the components of FIG. The integrating circuit 6'has the same configuration as the integrating circuit 6. In this case, the transfer gates TG ₁ , TG ₃ ,
-, TG _n-1 is an output terminal OUT through the horizontal signal line Y _0.
Connected to the transfer gates TG ₂ , TG ₄ , ─, T
G _n is connected to the output terminal OUT ′ via the horizontal signal line Y ₀ ′. Furthermore, the total wiring width of the horizontal signal lines Y ₀ and Y ₀ ′ is the wiring width of the horizontal lease line S ₀ . That is, the wiring width of the horizontal source line S ₀ is equal to that of each horizontal signal line Y ₀ , Y ₀ '
Is twice as wide as the wiring width. As a result, the voltage drop per unit length of the horizontal signal lines Y ₀ , Y ₀ ′ is reduced by the horizontal source line S _0.
The voltage drop should be the same as the voltage drop per unit length of. Further, a latch circuit 7 is provided between the horizontal shift register 3 of FIG. 1 and the transfer gates TG ₁ , TG ₂ , ..., TG _n . The latch circuit 7 receives the horizontal selection signals φ _H1 , φ _H2 ,-, φ _Hn from the horizontal shift register 3 and responds to the strobe signal ST by selecting the horizontal selection signals φ _H1 ', φ _H2 ',-, φ.
_Hn 'is generated. In FIG. 5, two pixels can be read at the same time, that is, the integration period is set to 2 in the case of FIG.
Can be doubled. In this way, the resistance of the wiring that passes through any pixel P _ij between the ground terminal GND and the output terminals OUT and OUT ′ is equalized.

FIG. 6 is a detailed circuit diagram of the latch circuit of FIG. That is, as shown in FIG.
-1,7-2, ─, 7-n are connected in parallel, each latch 7-1 and 7-2, ─, 7-n horizontal selection signal phi _H1 from the horizontal shift register 3, phi _H2, ─ , Φ _Hn are received and controlled by the strobe signal ST. Each latch 7-
1, 7-2,-, 7-n are shown in FIG. 6 (B). That is, when ST = "0" (low level),
The latch 7-i is in the holding state, and when ST = “1” (high level), the latch 7-i is in the passing state, that is,
The horizontal selection signal φ _Hi 'is the same as the horizontal selection signal φ _Hi .
Therefore, when the strobe signal ST switches from "1" to "0", the latch 7-i switches from the passing state to the holding state and holds the value immediately before that.

First of the bolometer type infrared detecting device of FIG.
The operation will be described with reference to FIG. The vertical shift register 1 has a vertical synchronization signal V _SYNC shown in FIGS.
Since the same operation as in the case of FIG. 1 is performed using the vertical synchronizing signal H _SYNC and the vertical synchronizing signal H _SYNC , description of the signals φ _V1 , φ _V2 , −, φ _Vm will be omitted. As shown in FIGS. 7C and 7D, the delayed horizontal synchronizing signal H _SYNC 'has a pulse width that sufficiently covers two clocks of the synchronizing clock signal SCK shown in FIG. 7E. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC 'shown in FIG. 7D and the synchronization clock signal SCK shown in FIG.
As shown in (L) and (M), (J), (K), and
Horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn having a pulse width twice that in the cases of (L) and (M) are generated. (E) of FIG.
As shown in (I), the frequency of the strobe signal ST is 1/2 of the frequency of the synchronous clock signal SCK. Therefore, the latch circuit 7 has the same horizontal selection signals φ _H1 'and φ _H2 ' shown in (J) and (K) of FIG. 7, (L) of FIG.
The same horizontal selection signals φ _H3 'and φ _H4 ' as shown in (M) are generated.

Further, the integral bias signals φ _B and φ _B 'are the same as shown in FIG.
6'is supplied. In this case, the pulse width of the integral bias signals φ _B and φ _B 'shown in FIG. 7N is twice the pulse width of the integrated bias signal φ _B shown in FIG. Further, the same reset signals φ _R and φ _R 'shown in (O) of FIG.
Is supplied to the integrating circuits 6, 6'after each integration period 2T _S. In this way, the integrated output signals S _OUT and S _OUT ^′ shown in (P) and (Q) of FIG. 7 can be obtained.

Second bolometer type infrared detector of FIG.
The operation of will be described with reference to FIG. In the second operation, the strobe signal ST is always "1" (high level), as shown in (I) of FIG. Therefore, the latch circuit 7 is in the passing state, and as a result, (F) in FIG.
As shown in (G), (H), (J), (K), and (L), φ _Hn 'is the same as the horizontal selection signals φ _H1 , φ _H2 ,-, φ _Hn . In addition, (M), (N), (P), (Q) in FIG.
As shown in, the integration bias signal φ _B 'for the integration circuit 6'
And the reset pulse φ _R ′ is shifted by one clock of the synchronous clock signal SCK with respect to the integration bias signal φ _B for the integration circuit 6 and the reset signal φ _R. As a result, integrated output signals S _OUT and S _OUT ^′ are obtained as shown in (O) and (R) of FIG.

In both the first and second operations shown in FIGS. 7 and 8, the integration period (2T _S ) is the same as in the case of FIG. 1 (T _S ).
Can be doubled.

FIG. 9 shows a modification of the bolometer type infrared detecting device of FIG. In FIG. 9, one integrating circuit 6 is connected to the output terminals OUT and OUT ′.

The operation of the bolometer type infrared detector of FIG. 9 will be described with reference to FIG. Vertical shift register 1
Is the vertical synchronization signal V _SYNC shown in (A) and (B) of FIG.
Since the same operation as in the case of FIG. 1 is performed by using the vertical synchronizing signal H _SYNC , the description of the signals φ _V1 , φ _V2 , ..., φ _Vm will be omitted. As shown in (C) and (D) of FIG. 10, the delayed horizontal synchronizing signal H _SYNC 'has a palace width enough to cover one clock of the synchronizing clock signal SCK shown in (E) of FIG. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC 'shown in FIG. 10D and the synchronization clock signal SCK shown in FIG.
As shown in (G) and (H), (J), (K), and
Horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn having the same palace width in the cases of (L) and (M) are generated.

Further, as shown in (I) of FIG. 10, the strobe signal ST is always "1" (high level).
Therefore, the latch circuit 7 is in the passing state, and as a result, (F), (G), (H), (J), (K),
As shown in (L), horizontal selection signals φ _H1 ', φ _H2 ',
, Φ _Hn 'is the same as the horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn . Further, the integration bias signal φ _B and the reset signal φ _R ′ shown in (M) and (N) of FIG. 10 are supplied to the integrating circuit 6. As a result, the integrated output signal S _OUT is obtained as shown in (O) of FIG. As described above, the infrared detector of FIG. 9 having the latch circuit 7 operates in the same manner as the infrared detector of FIG. 1 having no latch circuit.

FIG. 11 shows a modification of the bolometer type infrared detecting device of FIG. In FIG. 11, the ground terminal GND
The output terminal OUT and the output terminal OUT are diagonally arranged on the device (chip) by a method different from that in FIG. Also,
The transfer gates TG ₁ , TG ₂ , ..., TG _{n of FIG.}
Instead of N-channel MOS transistors G ₁ , G ₂ ,
..., G _n is provided. In this way, also in FIG. 11, the resistances of the wirings passing through any pixel P _ij between the ground terminal GND and the output terminal OUT are equalized. FIG.
Also in 1, the ground terminal GND and the output terminal OUT do not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by the dotted line. In short, it _suffices that the current flowing through the pixel P _ij flows substantially diagonally from the upper right corner to the lower left corner of the drawing on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 12 is a circuit diagram showing a third embodiment of the infrared detecting device according to the present invention, showing a one-dimensional infrared detecting device. In FIG. 12, the ground terminal G
Horizontal source line S ₀ and output terminal OUT connected to ND
, The horizontal signal line Y ₀ connected in parallel to the X direction, and the signal lines Y ₁ ′, Y ₂ ′, ..., Y _n ′ arranged in parallel to the Y direction.

The pixel P _j (j = 1, 2, ..., N) is provided at the intersection of the horizontal source line S ₀ and the signal lines Y ₁ ′, Y ₂ ′, ..., Y _n ′. For example, the pixel P ₂ is composed of an N-channel MOS transistor Q and a bolometer R. In this case, the source of the MOS transistor Q is connected to the ground terminal GND, and the drain of the MOS transistor Q is connected to the output terminal OUT via the bolometer R. The gate of the MOS transistor Q is connected to the signal line Y ₂ '.

Further, since the bolometer R is connected to the drain of the MOS transistor Q, the resistance of the bolometer R determines the current flowing through the MOS transistor Q, so that 1 / f noise, which is a variation in resistance, is hardly observed. .

Also in FIG. 12, the ground terminal GND and the output terminal OUT are arranged diagonally to each other. As a result, the lengths of electrical paths passing through any pixel P _J between the ground terminal GND and the output terminal OUT are equalized. Further, the wiring widths of the horizontal signal line Y ₀ and the horizontal source line S ₀ are made the same. In this way, the resistance of the wiring that passes through any pixel P _J between the ground terminal GND and the output terminal OUT is equalized. The ground terminal GND and the output terminal OUT do not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by the dotted line. In short, it suffices that the current flowing through the pixel P _j flows almost diagonally from the lower right side to the upper left side of the drawing on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _j .

The operation of the bolometer type infrared detector of FIG. 12 will be described with reference to FIG. Horizontal shift register 3
Is the horizontal synchronization signal H _SYNC 'shown in FIG.
When the synchronous clock signal SCK shown in (B) of FIG. 3 is received, as shown in (C), (D), (E), and (F) of FIG. 13, horizontal selection signals φ _H1 , φ _H2 , φ _H3 , ... , Φ _Hn are sequentially generated.

Further, the integrated bite signal φ _B shown in (G) of FIG.
The reset signal φ _R shown in (H) of 3 is input to the reset transistor 63 after each integration period T _S. This allows
The integrated output signal S _OUT shown in (I) of FIG. 13 is obtained.

FIG. 14 is a circuit diagram showing a fourth embodiment of a bolometer type infrared detecting device according to the present invention. FIG.
4, the output terminal OUT ′ and the output terminal OU
An integrating circuit 6'connected to T'is added to the components of FIG. The integrating circuit 6'has the same configuration as the integrating circuit 6. The total wiring width of the horizontal signal lines Y ₀ and Y ₀ ′ is the wiring width of the horizontal source line S ₀ .
That is, the wiring width of the horizontal source line S ₀ is twice the wiring width of each horizontal signal line Y ₀ , Y ₀ ′. As a result, the voltage drop per unit length of the horizontal signal lines Y ₀ and Y ₀ 'is made equal to the voltage drop per unit length of the horizontal source line S ₀ .

Further, a latch circuit 7 is provided between the horizontal shift register 3 of FIG. 12 and the AND circuits 4-1, 4-2, ..., 4-n. The latch circuit 7 receives the horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn from the horizontal shift register 3,
In response to the strobe signal ST, the horizontal selection signals φ _H1 ', φ
Generate _H2 ', ..., φ _Hn '. In FIG. 14, two pixels can flow out at the same time, that is, the integration period can be doubled as compared with the case of FIG. In this way, the resistance of the wiring that passes through any pixel P _j between the ground terminal GND and the output terminals OUT and OUT ′ is equalized.

The first operation of the bolometer type infrared detector of FIG. 14 will be described with reference to FIG. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC shown in FIG. 15A and the synchronization clock signal SCK shown in FIG. 15B, and the horizontal shift register 3 shown in FIGS. 15C, _15D, and _15E . As shown in FIG. 13, horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn having a pulse width twice that in the cases of (C), (D), (E), and (F) of FIG. 13 are generated. As shown in FIGS. 15B and 15F, the frequency of the strobe signal ST is 1/2 of the frequency of the synchronous clock signal SCK. Therefore, the latch circuit 7 has the same horizontal selection signals φ _H1 'and φ _H2 ' shown in (G) and (H) of FIG. 15 and the same horizontal selection signals shown in (I) and (J) of FIG. Generate signals φ _H3 ', φ _H4 ', etc.

In addition, the integral bias signals φ _B , φ _B ',
Are the same and are supplied to the integrating circuits 6 and 6 ', as shown in FIG. In this case, the pulse widths of the integral bias signals φ _B and φ _B 'shown in FIG.
(G) is twice the pulse width of the integrated bias signal φ _B. Further, the same reset signal phi _R shown in (L) of FIG. 15, phi _R 'is an integration circuit 6 after each integration period 2T _S,
6'is supplied. In this way, (M) of FIG.
The integrated output signals S _OUT and S _OUT 'shown in (N) can be obtained.

The second operation of the bolometer type infrared detector of FIG. 14 will be described with reference to FIG. In the second operation, the strobe signal ST is always "1" (high level) as shown in (F) of FIG. Therefore, the latch circuit 7 is in the passing state, and as a result, (C), (D), (E), (F), (G), (H),
As shown in (I), horizontal selection signals φ _H1 ', φ _H2 ',
, Φ _Hn 'is the same as the horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn . In addition, (J), (K), (M), and
As shown in (N), the integration bias signal φ _B ′ and the reset signal φ _R ′ for the integration circuit 6 ′ are the synchronization clock signal SCK of the integration bias signal φ _B and the reset signal φ _R for the integration circuit 6. It is shifted by one clock. As a result, integrated output signals S _OUT and S _OUT 'are obtained as shown in (L) and (O) of FIG.

In both the first and second operations shown in FIGS. 15 and 16, the integration period (2T _S ) can be doubled as compared with the case of FIG. 12 (T _S ).

FIG. 17 shows a modification of the bolometer type infrared detecting device of FIG. In FIG. 17, one integrating circuit 6 is connected to the output terminals OUT and OUT ′.

The operation of the bolometer type infrared detector of FIG. 17 will be described with reference to FIG. 18A,
As shown in (B), the delayed horizontal synchronizing signal H _SYNC has a pulse width enough to cover one clock of the synchronizing clock signal SCK. The horizontal shift register 3 receives the horizontal synchronizing signal H _SYNC shown in (A) of FIG. 18 and the synchronizing clock signal SCK shown in (B) of FIG. 18, and (C), (D), (E) of FIG. , The horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn having the same palace width in the cases of (C), (D), (E), and (F) of FIG. 13 are generated.

Further, as shown in FIG. 18F, the strobe signal ST is always "1" (high level).
Therefore, the latch circuit 7 is in the passing state, and as a result, (C), (D), (E), (F), (G), and
As shown in (I), horizontal selection signals φ _H1 ', φ _H2 ',
, Φ _Hn 'is the same as the horizontal selection signals φ _H1 , φ _H2 , ..., φ _Hn . Further, the integral bias signal φ _B and the reset signal φ _R ′ shown in (J) and (K) of FIG. 18 are supplied to the integrating circuit 6. As a result, the integrated output signal S _OUT is obtained as shown in (L) of FIG. As described above, the infrared detector of FIG. 17 having the latch circuit 7 operates in the same manner as the infrared detector of FIG. 12 having no latch circuit.

FIG. 19 is a circuit diagram of the integrating circuit 6 of FIGS. 25, 1, 4, 5, 9, 11, 12, 14, and 17.
An example of modification of 6'is shown. That is, the junction type FET 64 is provided in place of the bipolar transistor 61 (61 '). In this case, the junction FET 64 operates in the same way as the bipolar transistor 61 (61 '). Junction type FE
T64 is inferior to the bipolar transistor 61 (61 ′) in terms of mutual conductance, but has an advantage of not having shot noise. It also corresponds to the base resistor of the bipolar transistor. It has the advantage that the resistance value is small and therefore the Johnson noise is also small.

FIG. 20 shows FIG. 1, FIG. 4, FIG. 5, FIG.
FIG. 18 is a block circuit diagram showing an infrared processing system including the bolometer type infrared detection device of FIG. 1, FIG. 12, FIG. 14 or FIG. 1, FIG. 4, FIG. 5, FIG. 9, FIG. 11, FIG.
Bolometer type infrared detector 23 of FIG. 14 or FIG.
00 is the Peltier element 23 except for the integration circuit 6 (6 ′).
01, the infrared detection device is kept at a constant temperature. The Peltier element 2301 is a central processing unit (CPU) 2
Controlled by 303. Further, the CPU 2303 controls the drive circuit 2304 to send control signals such as the vertical synchronizing signal V _SYNC , the horizontal synchronizing signal H _SYNC , the synchronizing clock signal SCK, and the strobe signal ST to the infrared detecting device 2300. In this case, the infrared detection device 2300 is shown in FIG.
If it is as shown in FIG. 12, the strobe signal ST is not supplied. In addition, the infrared detection device 2300 is shown in FIG.
In the case of the signals shown in FIGS. 14 and 17, the vertical synchronization signal V
_SYNC is not supplied.

Each output OUT of the infrared detector 2300,
OUT ′ is connected to the integrator circuits 6 and 6 ′, and each of the integrator circuits 6 and 6 ′ receives the integral bias signals φ _B and φ _B ′ and the reset signals φ _R and φ _R ′ from the drive circuit 2304. The outputs of the integrator circuits 6 and 6'are connected to sample / hold circuits 2305 and 2305 ', and the sample / hold circuits 2305 and 2305' are connected to analog / digital (A / D) converters 2306 and 2306 '. There is. In this case, the infrared detection device 2300 is shown in FIG.
As shown in FIGS. 9, 12, and 17, the integrating circuit 6 ′, the sample / hold circuit 2305 ′, and the A / D converter 2306 ′ do not exist.

In FIG. 20, 2307 is a ROM for storing programs and constants, 2308 is a RAM for storing pixel data, and 2309 is a digital / analog (D / A) converter for generating NTSC signals and the like. CP
U2303, A / D converter 2306, 2306 'ROM
The 2307, the RAM 2308, and the D / A converter 2309 are connected to each other by the data bus DB and the address bus AB. The integrating circuits 6 and 6 ′ can be built in the infrared detector 2300. That is, the infrared detecting device 2300 and the integrating circuits 6 and 6'can be configured by one single chip.

Next, the pixel P _ij in FIGS. 1, 4, 5, 9, and 11 will be described with reference to FIGS. 21, 22, and 23. Note that FIG. 21 is a cross-sectional view, FIGS. 22 and 23 are plan views, FIG. 22 shows a first floor portion for mainly reading out signals, and FIG. 23 shows a second floor portion for mainly converting infrared rays into electric signals. First, referring to FIGS. 22 and 23, P
^A thick silicon oxide layer 2402 is formed on a ⁻ type single crystal silicon substrate 2401 to divide each pixel. Further, a thin silicon oxide layer 2403 is formed thereon, and a polysilicon layer 2404 is formed and patterned to form a signal line X _i . In addition, the silicon substrate 24
01, N-type impurity layers 2401S and 241S and 24 using the silicon oxide layer 2402 and the polysilicon layer 2404 as masks.
01D is formed. These N-type impurity layers 2401S,
2401D acts as a source region and a drain region. In this case, the silicon substrate 2401 below the polysilicon layer 2404 acts as the channel region 2401C.
Thus, the N-channel MOS transistor Q of the pixel P _ij is composed of the gate electrode (polysilicon layer 2404), the source region 2401S and the drain region 2401D. In this case, the gate electrode has a folded shape, that is, a zigzag shape.
The width of the gate electrode is increased to increase the current flowing through the transistor Q. Further, in FIG. 21, a thick silicon oxide layer 2405 is formed on the surface, and a cavity 240 is formed in a part thereof.
5a is formed. This cavity 2405a is formed by burying a polysilicon layer in the silicon oxide layer 2405 and finally etching it away. Cavity 2405
a improves the thermal insulation of the bolometer R.

Next, referring to FIGS. 21 and 23, aluminum or an alloy thereof is formed and patterned to form an aluminum layer 2406. The aluminum layer 2406 includes the source lines S _j and S _{j + 1} and the signal line Y.
acts as _j . In this case, the source lines S _j and S _{j + 1} are connected to the source region 2401 through the contact hole CONT1.
S (FIG. 22). In addition, the aluminum layer 2406 functions as a contact to the drain region 2401D through the contact hole CONT2. 21 and 23, a titanium layer 2407 which functions as a bolometer R, a silicon oxide layer 2408, and a titanium nitride layer 2409 are formed. The titanium layer 2407, the silicon oxide layer 2408, and the titanium nitride layer 2409 also form an infrared absorption layer, and together with the cavity 2405a, the slit 2 is formed.
A light receiving surface (diaphragm) having long legs thermally insulated by 410 is formed. That is, the infrared rays reflected from the titanium layer 2407 are not included in the titanium nitride layer 2409.
It is absorbed by the electromagnetic effect of. In order to efficiently exert this electromagnetic effect, the heat of the silicon oxide layer 2408 is λ / (4n), where λ is the wavelength of infrared rays and n is the refractive index of the silicon oxide layer 2408. The titanium nitride layer 2409 has a thickness of several hundred Å. Further, the titanium layer 2407 has a dense foldet shape in order to reflect infrared rays efficiently.

In the pixels shown in FIGS. 21, 22, and 23, when infrared rays are incident on the thermally insulated diaphragm, the diaphragm is heated, and as a result, the resistance value of the bolometer R (2407), that is, the titanium layer 2407. The resistance value changes. In this case, bolometer R (2407)
Since the temperature of the foot part of the is hardly changed, the resistance value of the part is hardly changed. Also, the bolometer R
23 has a zigzag shape as shown in FIG. 23, and as a result, the bolometer R substantially gains a length in receiving infrared rays. Therefore, the resistance value of the long serpentine-shaped portion of the bolometer R is the resistance value of the foot portion of the bolometer R, the ON resistance of the MOS transistor Q, the wiring resistance between the ground terminal GND and the output terminal OUT, or the transfer gate such as TG. _It becomes larger than the resistance value of _j .

FIG. 24 shows a modification of the diaphragm shown in FIGS. 21, 22 and 23. The MOS transistor Q of each pixel is shown in FIG.
Are formed on the silicon substrate 2601 in the same manner as in FIGS. 21, 22, and 23. In addition, the diaphragm 26
02 is made of silicon nitride or silicon oxide, and has two feet 2602a and 2 contacting the silicon substrate 2601.
602b. Furthermore, titanium bolometer 260
3 has a zigzag shape on the diaphragm 2602 and is electrically connected to the silicon substrate 2601. Therefore, also in this case, the bolometer 2603 substantially gains the length with respect to the reception of infrared rays. Therefore, the resistance value of the long serpentine-shaped portion of the bolometer 2603 is
Resistance value of foot of bolometer R, ON resistance of MOS transistor Q, wiring resistance between ground terminal GND and output terminal OUT, or transfer gate such as TG
_It becomes larger than the resistance value of _j .

Although the two output terminals OUT and OUT 'are provided in FIGS. 5, 9, 11, 14, and 17, three or more output terminals can be provided. For example, in the case of three output terminals, the signal lines Y ₁ , Y
_4, a ... to the first output terminal, the signal line Y _2, Y _5, ... the second
, The signal lines Y ₃ , Y ₆ , ... May be connected to the third output terminal. In this case, the horizontal source line S ₀
The wiring width may be three times the wiring width of the horizontal signal line.

[0057]

As described above, according to the present invention, the current paths flowing in the respective pixels are substantially diagonal in the group of a plurality of pixels, so that the wiring resistances of the current paths of the respective pixels can be equalized. , The variation of each pixel can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a bolometer type infrared detection device according to the present invention.

FIG. 2 is a circuit diagram of a vertical shift register and a horizontal shift register of FIG.

3 is a timing diagram illustrating the operation of the apparatus of FIG.

FIG. 4 is a circuit diagram showing a modified example of the device of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of a bolometer type infrared detection device according to the present invention.

FIG. 6 is a circuit diagram of the latch circuit of FIG.

FIG. 7 is a timing diagram showing a first operation of the device of FIG.

8 is a timing diagram showing a second operation of the apparatus of FIG.

9 is a circuit diagram showing a modified example of the device of FIG.

10 is a timing diagram illustrating the operation of the apparatus of FIG.

11 is a circuit diagram showing a modified example of the device of FIG.

FIG. 12 is a circuit diagram showing a third embodiment of a bolometer type infrared detection device according to the present invention.

13 is a circuit diagram showing a modified example of the device of FIG.

FIG. 14 is a circuit diagram showing a fourth embodiment of a bolometer type infrared detection device according to the present invention.

FIG. 15 is a timing diagram showing a first operation of the apparatus of FIG.

16 is a timing diagram showing a second operation of the apparatus of FIG.

FIG. 17 is a circuit diagram showing a modified example of the device of FIG.

FIG. 18 is a timing diagram illustrating the operation of the apparatus of FIG.

19 is a plan view of FIG. 1, FIG. 4, FIG. 5, FIG. 9, FIG.
FIG. 21 is a circuit diagram showing a modified example of the integrating circuit of FIGS. 14 and 20.

FIG. 20, FIG. 4, FIG. 5, FIG. 9, FIG.
FIG. 18 is a block circuit diagram showing an infrared processing system including the bolometer type infrared detection device of FIG. 14 or FIG. 17.

21 is a cross-sectional view showing an example of a pixel of the device of FIGS. 1, 4, 5, 9, and 11. FIG.

22 is a plan view of FIG. 21. FIG.

FIG. 23 is a plan view of FIG. 21.

FIG. 24 is a cross-sectional view showing another example of a pixel of the device of FIGS. 1, 4, 5, 9, and 11.

FIG. 25 is a circuit diagram showing a conventional bolometer type infrared detection device.

[Explanation of symbols]

1 ... Vertical shift register 2-1, 2-2, ..., 2-m ... AND circuit 3 ... Horizontal shift register 4-1, 4-2, ..., 4-n ... AND circuit 5 ... Delay circuit 6, 6 ' Integrator circuit 7 ... Latch circuit X ₁ , X ₂ , ..., X _m ... Signal lines Y ₁ , Y ₂ , ..., Y _n ... Signal lines Y ₀ , Y ₀ '... Horizontal signal lines S ₁ , S ₂ , , S _n ... Source line S ₀ ... Common source line P ₁₁ , P ₁₂ , ..., P _mn , P ₁ , P ₂ , ..., P ₃ ... Pixel R ... Bolometer GND ... Ground terminal OUT, OUT '... Output terminal TG ₁ , TG ₂ , ..., TG _n ... Transfer gate

Claims (16)

[Claims] 1. A power supply terminal (GND) and a plurality of first signal lines (X) arranged in a first direction (Y).
₁ , X ₂ , ..., X _m ) and a plurality of second signal lines (Y ₁ , Y ₂ , ..., Y _n ) arranged in a second direction (X) substantially perpendicular to the first direction. ) And a plurality of source lines (S ₁ , S) arranged in the second direction.
_2, ..., S and _n), the are arranged in a first direction, a horizontal source line for connecting the power supply terminal and respective source lines and (S _0), a plurality of pixels arranged in a two-dimensional (P ₁₁ , P ₁₂ , ...
P _mn ), wherein each pixel has a source connected to one of the source lines, a gate connected to one of the first signal lines, and a drain. (Q) and a bolometer (R) connected to the drain of the first MOS transistor and one of the second signal lines, and a current path flowing through each pixel is A bolometer-type infrared detector that is almost diagonal within the group. 2. A plurality of transfer gates (TG ₁ , TG ₂ , ..., TG _n ) connected to each of the second signal lines, an output terminal (OUT), and arranged in the first direction. And a horizontal signal line (Y ₀ ) for connecting each of the transfer gates and the output terminal, wherein a connection point between the horizontal source line and the power supply terminal is substantially on the device with respect to the output terminal. Claim 1 located diagonally
The bolometer-type infrared detection device described in 1. 3. The bolometer infrared ray according to claim 2, wherein the second signal lines and the source lines have the same wiring width, and the horizontal source lines and the horizontal signal lines have the same wiring width. Detection device. 4. A plurality of second MOS transistors (G ₁ , G ₂ , ..., G) provided between each source line and the horizontal source line.
_n ), an output terminal (OUT), and a horizontal signal line (Y ₀ ) arranged in the first direction and connecting each of the second signal lines to the output terminal, the horizontal source The bolometer-type infrared detection device according to claim 1, wherein a connection point between a line and the power supply terminal is located substantially diagonally on the device with respect to a connection point between the horizontal signal line and the output terminal. 5. The bolometer infrared ray according to claim 4, wherein the wiring widths of the second signal lines and the source lines are the same, and the wiring widths of the horizontal source lines and the horizontal signal lines are the same. Detection device. 6. A plurality of transfer gate groups (TG ₁ , TG ₂ , ..., TG _n ) connected to each of the second signal lines, a plurality of output terminals (OUT), and the first A plurality of horizontal signal lines (Y ₀ , Y ₀ ′) that are arranged in a direction and connect one of the transfer gate groups and one of the output terminals, and connect the horizontal source line and the power supply terminal. The bolometer-type infrared detection device according to claim 1, wherein connection points are located substantially diagonally on the device with respect to the respective output terminals. 7. The wiring widths of the second signal lines and the source lines are the same, and the wiring width of the horizontal source lines is n times the wiring width of the horizontal signal lines, where n is the width of the horizontal signal lines. The bolometer type infrared detection device according to claim 6, which is the number of output terminals. 8. A plurality of second MOS transistors (G ₁ , G ₂ , ..., G) provided between each source line and the horizontal source line.
_n ), a plurality of output terminals (OUT, OUT ′), and a plurality of horizontal signal lines (Y ₀ ) arranged in the first direction and connecting the group of the second signal lines to each of the output terminals. , Y
₀ '), wherein the connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to the connection point between each horizontal signal line and the output terminal. The bolometer-type infrared detection device described in 1. 9. The wiring widths of the second signal lines and the source lines are the same, and the wiring width of the horizontal source lines is n times the wiring width of the horizontal signal lines, where n is the width of the horizontal signal lines. The bolometer type infrared detection device according to claim 8, which is the number of output terminals. 10. A power supply terminal (GND), an output terminal (OUT), a horizontal signal line (Y ₀ ) arranged in the first direction (Y) and connected to the output terminal, and the first signal line (Y ₀ ). A plurality of signal lines (Y ₁ ′, Y ₂ ′, ..., Y _n ′) arranged in a second direction (X) substantially perpendicular to the direction, and the power supply terminals arranged in the first direction. A horizontal source line (S ₀ ) to be connected and a plurality of pixels (P ₁ , P ₂ , ..., P _n ) arranged one-dimensionally in the first direction are provided, and each pixel is the above-mentioned. A first MOS transistor (Q) having a source connected to a horizontal source line, a gate connected to one of the second signal lines, and a drain; and a drain of the first MOS transistor and the horizontal A bolometer (R) connected to a signal line, and a current path flowing through each pixel is A bolometer-type infrared detector that is almost diagonal within a group of pixels. 11. The bolometer according to claim 10, wherein a connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to a connection point between the horizontal signal line and the output terminal. Type infrared detector. 12. The bolometer type infrared detection device according to claim 10, wherein the horizontal source line and the horizontal signal line have the same wiring width. 13. A power supply terminal (GND), a plurality of output terminals (OUT), and a plurality of horizontal signal lines (Y ₀ , Y) arranged in the first direction (Y) and connected to the respective output terminals. ₀ ′) and a plurality of signal lines (Y ₁ ′, Y ₂ ′, ..., Y _n ′) arranged in a second direction (X) substantially perpendicular to the first direction, and the first line. A horizontal source line (S ₀ ) arranged in the first direction and connecting to the power supply terminal, and a plurality of pixels (P ₁ , P ₂ , ..., P _n ) arranged one-dimensionally in the first direction. Each of the pixels includes a first MOS transistor (Q) having a source connected to the horizontal source line, a gate connected to one of the second signal lines, and a drain; A bolometer (R) connected to the drain of the MOS transistor and one of the horizontal signal lines, And has bolometer-type infrared detection device almost diagonal current path within the group of the plurality of pixels. 14. The connection point according to claim 13, wherein the connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to the connection point between the horizontal signal line and each output terminal. Bolometer type infrared detector. 15. The bolometer type infrared detection device according to claim 13, wherein the wiring width of the horizontal source line is n times the wiring width of the horizontal signal line, where n is the number of the output terminals. 16. The integrating circuit (6, 6 ′) has the output terminal.
A junction type FET (64) connected to the output terminal and turned on by an integration bias signal (φ _B ), and a capacitor (62) connected to the junction type FET. A reset transistor (6 connected to the capacitor
1) The bolometer type infrared detection device according to claim 1, 10 or 13, further comprising: