JPH0519828B2 - - Google Patents
Info
- Publication number
- JPH0519828B2 JPH0519828B2 JP58089820A JP8982083A JPH0519828B2 JP H0519828 B2 JPH0519828 B2 JP H0519828B2 JP 58089820 A JP58089820 A JP 58089820A JP 8982083 A JP8982083 A JP 8982083A JP H0519828 B2 JPH0519828 B2 JP H0519828B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- gate
- input
- ccd
- opposite conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 8
- 238000009825 accumulation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 101100115215 Caenorhabditis elegans cul-2 gene Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14875—Infrared CCD or CID imagers
- H01L27/14881—Infrared CCD or CID imagers of the hybrid type
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置に掛かり、特に背景光等に
より生じる不要成分を抑制し得る二次元赤外セン
サの信号読み出し装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to semiconductor devices, and particularly to a signal readout device for a two-dimensional infrared sensor that can suppress unnecessary components caused by background light and the like.
(b) 従来技術と問題点
赤外ホトダイオードと、二次元(インタレース
型)CCDとを組合せて構成される通常のハイブ
リツド二次元センサ(IRCCD)は、検知すべき
信号成分に対し、背景光などによる直流成分が大
きいため、検出感度を高めることが難しくまたダ
イナミツクレンジを大きくすることが困難であ
る。即ち、赤外センサでは検知すべき対象試料温
度の変動分に対応する信号より、背景光である対
象試料の温度レベルあるいは環境温度に対応する
直流成分の方が圧倒的に大きい場合が多い。例え
ば検知しようとする対象試料の温度が、常温にお
ける数度の変動であるような場合、検知される赤
外線強度は約300〔〓〕に対応する背景光に、僅か
数度の変化に対応する微弱な信号光が重畳したも
のとなり、検知出力もこれに対応して上記背景光
に対応する直流成分に、微弱な信号成分が重畳し
たものとなる。従つて検出感度を向上させるに
は、上述の直流成分を除去して所望の信号成分の
みを取り出すことが必要である。(b) Conventional technology and problems A typical hybrid two-dimensional sensor (IRCCD), which is constructed by combining an infrared photodiode and a two-dimensional (interlaced) CCD, detects background light and other signals for the signal components to be detected. Since the direct current component is large, it is difficult to increase the detection sensitivity and it is difficult to increase the dynamic range. That is, in the infrared sensor, in many cases, the DC component corresponding to the temperature level of the target sample or the ambient temperature, which is background light, is overwhelmingly larger than the signal corresponding to the variation in the temperature of the target sample to be detected. For example, if the temperature of the target sample to be detected varies by a few degrees from room temperature, the detected infrared intensity will be the background light corresponding to approximately 300 [〓], and the weak infrared intensity corresponding to a change of only a few degrees. Correspondingly, the detection output is a DC component corresponding to the background light and a weak signal component superimposed thereon. Therefore, in order to improve the detection sensitivity, it is necessary to remove the above-mentioned DC component and extract only the desired signal component.
ところが従来の二次元赤外センサの読み出し回
路に、かかる背景光などによる直流成分を抑制す
る機能を付加しようとすると、読み出し回路の構
成が複雑となり且つCCD領域の面積が減少する。
そのため真に実用的な赤外センサの読み出し回路
の出現が強く望まれていた。 However, if an attempt is made to add a function to suppress the direct current component due to such background light to the readout circuit of a conventional two-dimensional infrared sensor, the configuration of the readout circuit becomes complicated and the area of the CCD region decreases.
Therefore, the emergence of a truly practical infrared sensor readout circuit has been strongly desired.
(c) 発明の目的
本発明はかかる事情に鑑みてなされたものであ
つて、その目的は、背景光などによる直流成分を
抑制して所望の信号成分のみを取り出すことが出
来、且つ構成の簡単な二次元赤外センサの読み出
し回路を提供することにある。(c) Purpose of the Invention The present invention has been made in view of the above circumstances, and its purpose is to suppress DC components caused by background light, etc. and extract only desired signal components, and to have a simple configuration. An object of the present invention is to provide a readout circuit for a two-dimensional infrared sensor.
(d) 発明の構成
本発明は、光電変換素子の検知出力を入力し、
該入力のうち所要の信号部分を選択してCCDへ
出力し不要電荷部分をリセツトトランジスタへ排
出する読み出し電荷量制御素子を有する構成の半
導体装置において、該読み出し電荷量制御素子は
一導電型半導体基板表面に互いに離隔して形成さ
れた入力側及び出力側逆導電型領域と、該入力側
及び出力側逆導電型領域に挟まれた領域上に入力
ゲート、蓄積ゲート、及び移送ゲートとを有し、
且つ前記入力側逆導電型領域が前記光電変換素子
の出力端に接続されるとともに、出力側逆導電型
領域が前記リセツトトランジスタのソース端子お
よび前記CCDの入力端子に接続されてなり、前
記入力ゲート、蓄積ゲート、及び移送ゲートの電
位をそれぞれ選択制御することにより、時系列的
に前記出力側逆導電型領域から前記光電変換素子
の検知出力のうち、所要の信号部分をCCDへ出
力し、もしくは不要電荷部分をリセツトトランジ
スタへ排出することを可能ならしめた半導体装置
にある。(d) Structure of the invention The present invention inputs the detection output of a photoelectric conversion element,
In a semiconductor device having a configuration including a readout charge amount control element that selects a required signal portion from the input and outputs it to a CCD and discharges an unnecessary charge portion to a reset transistor, the readout charge amount control element is a one-conductivity type semiconductor substrate. It has input side and output side opposite conductivity type regions formed on the surface to be spaced apart from each other, and an input gate, an accumulation gate, and a transfer gate on a region sandwiched between the input side and output side opposite conductivity type regions. ,
The input side reverse conductivity type region is connected to the output terminal of the photoelectric conversion element, and the output side reverse conductivity type region is connected to the source terminal of the reset transistor and the input terminal of the CCD, and the input gate , selectively controlling the potentials of the storage gate and the transfer gate to output a required signal portion of the detection output of the photoelectric conversion element from the output side reverse conductivity type region to a CCD in time series, or This semiconductor device is capable of discharging an unnecessary charge portion to a reset transistor.
(e) 発明の実施例
以下本発明の一実施例を図面を参照しながら説
明する。(e) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例の要部を模式的に示
す要部断面図であつて、1は読み出し電荷量制御
素子、2はCCD、3はリセツトトランジスタ、
4は光電変換素子で本実施例では赤外ホトダイオ
ードである。更に5は一導電型半導体基板で、本
実施例ではp型のシリコン(Si)基板、6,7,
8,9,9′は逆導電型領域で本実施例ではn型
領域、10は絶縁膜で例えば二酸化シリコン
(SiO2)膜、11,12,13は多結晶シリコン
等よりなる読み出し電荷量制御素子1の入力ゲー
ト、蓄積ゲート、移送ゲート、14,15は
CCD2の移送ゲート及び転送電極、16はリセ
ツトトランジスタ3のゲート電極で、14〜16
はいずれも多結晶シリコンよりなる。なおCCD
2、リセツトトランジスタ3、及び赤外ホトダイ
オード4は通常のものと何ら変わるところはな
い。 FIG. 1 is a cross-sectional view schematically showing the main parts of an embodiment of the present invention, in which 1 is a readout charge amount control element, 2 is a CCD, 3 is a reset transistor,
Reference numeral 4 denotes a photoelectric conversion element, which in this embodiment is an infrared photodiode. Furthermore, 5 is a semiconductor substrate of one conductivity type, in this example, a p-type silicon (Si) substrate, 6, 7,
8, 9, and 9' are regions of opposite conductivity type, and in this embodiment are n-type regions; 10 is an insulating film, such as a silicon dioxide (SiO 2 ) film; and 11, 12, and 13 are readout charge amount control layers made of polycrystalline silicon, etc. The input gate, storage gate, and transfer gate of element 1, 14 and 15 are
Transfer gate and transfer electrode of CCD 2, 16 is the gate electrode of reset transistor 3, 14-16
Both are made of polycrystalline silicon. Furthermore, CCD
2. The reset transistor 3 and infrared photodiode 4 are no different from ordinary ones.
上記本実施例の動作は、電荷蓄積、信号読み出
し、及び不要電荷排出の3段階から構成される。
その動作を第2図のポテンシヤル図を参照しなが
ら説明する。 The operation of this embodiment is comprised of three stages: charge accumulation, signal readout, and unnecessary charge discharge.
The operation will be explained with reference to the potential diagram in FIG.
まず読み出し電荷量制御素子1の入力ゲート1
1には、全期間を通じて凡そ0.1〔V〕の直流電圧
を印加しておく。これにより第2図に見られる如
く入力ゲート11直下部のポテンシヤルは僅かに
押し下げられる。 First, input gate 1 of readout charge amount control element 1
1, a DC voltage of approximately 0.1 [V] is applied throughout the entire period. As a result, as seen in FIG. 2, the potential directly below the input gate 11 is pushed down slightly.
〔電荷蓄積〕(第2図a参照)
上記状態で蓄積ゲート12に凡そ10〔V〕の
パルス電圧を印加する。このとき移送ゲート1
3の電位は0〔V〕としておく。これにより蓄
積ゲート12直下部のポテンシヤルは上記入力
ゲート11直下部のポテンシヤル22より遥か
に深く押し下げられ、ポテンシヤルの井戸20
が形成されるので、赤外ホトダイオード4か
ら、検知された赤外光強度に対応する量の電荷
が、n型領域6を経由してポテンシヤルの井戸
20に流入(矢印A)し、、所定時間経過後に
は上記赤外光強度に対応した電荷量21がポテ
ンシヤルの井戸20に蓄積される。この段階で
は移送ゲート13には電圧が印加されていない
ので、その直下部のポテンシヤルは高く保た
れ、ポテンシヤルの井戸20とn型領域7との
間の障壁23として働く。従つてポテンシヤル
の井戸20内の電荷は他へ流れ出すことはな
い。 [Charge Accumulation] (See Figure 2a) In the above state, a pulse voltage of about 10 [V] is applied to the accumulation gate 12. At this time, transfer gate 1
The potential of point 3 is set to 0 [V]. As a result, the potential directly below the storage gate 12 is pushed down much deeper than the potential 22 directly below the input gate 11, and the potential well 20
is formed, an amount of charge corresponding to the detected infrared light intensity flows from the infrared photodiode 4 into the potential well 20 via the n-type region 6 (arrow A), and continues for a predetermined time. After the elapse of time, an amount of charge 21 corresponding to the intensity of the infrared light is accumulated in the potential well 20. Since no voltage is applied to the transfer gate 13 at this stage, the potential directly below it remains high and acts as a barrier 23 between the potential well 20 and the n-type region 7. Therefore, the charge within the potential well 20 does not flow out.
〔信号読み出し〕(同図b参照)
次いで読み出し電荷量制御素子1の移送ゲー
ト13に例えば凡そ2〔V〕のパルス電圧を印
加するとともに、CCD3の移送ゲート14に
凡そ3〔V〕の電圧を印加する。これにより移
送ゲート13及び14直下部のポテンシヤルが
下がり、障壁23及び24が低くなる。そのた
めポテンシヤルの井戸20内に蓄積された電荷
21のうち、上記障壁23のポテンシヤルより
高い部分は、障壁23,24を越えてCCD2
のポテンシヤルの井戸25内に流入(矢印B,
C)する。 [Signal readout] (see figure b) Next, a pulse voltage of approximately 2 [V], for example, is applied to the transfer gate 13 of the readout charge amount control element 1, and a voltage of approximately 3 [V] is applied to the transfer gate 14 of the CCD 3. Apply. As a result, the potential directly below the transfer gates 13 and 14 is lowered, and the barriers 23 and 24 are lowered. Therefore, of the charge 21 accumulated in the potential well 20, the portion higher than the potential of the barrier 23 crosses the barriers 23 and 24 and becomes the CCD 2.
into the potential well 25 (arrow B,
C) Do.
〔不要電荷排出〕(同図c参照)
次いでCCD2の移送ゲート14の印加電圧
を0〔V〕ととして障壁24を高め、CCD2へ
の電荷の移送を停止せしめる。そしてCCD2
においては通常の読み出し方法に従つて、転送
電極15に所定の電圧を印加することにより、
ポテンシヤルの井戸25に蓄積された電荷は転
送され時系列データとして外部に読み出され
る。 [Unnecessary Charge Discharge] (See c in the same figure) Next, the voltage applied to the transfer gate 14 of the CCD 2 is set to 0 [V], the barrier 24 is raised, and the transfer of charges to the CCD 2 is stopped. And CCD2
By applying a predetermined voltage to the transfer electrode 15 according to the normal readout method,
The charges accumulated in the potential well 25 are transferred and read out as time series data.
一方読み出し電荷量制御素子1においては、蓄
積ゲート12に対する印加電圧を凡そ1〔V〕と
して、該蓄積ゲート12直下部のポテンシヤルを
上昇させるとともに、リセツトトランジスタ3の
ゲート16に凡そ3〔V〕の電圧を印加して該ゲ
ート16直下部のポテンシヤル26を下げること
により、上記ポテンシヤルの井戸20内部に残留
していた電荷を、n型領域7及びリセツトトラン
ジスタ3のn型領域9,9′を経由して外部の電
源に流出させる(矢印D,E)。これによりポテ
ンシヤルの井戸20内の不要電荷は排出される。
このようにポテンシヤルの井戸20を空にした
後、上述の操作を順次繰り返す。 On the other hand, in the readout charge amount control element 1, the voltage applied to the storage gate 12 is set to about 1 [V] to increase the potential directly below the storage gate 12, and the voltage applied to the gate 16 of the reset transistor 3 is set to about 3 [V]. By lowering the potential 26 directly below the gate 16 by applying a voltage, the charge remaining inside the potential well 20 is removed via the n-type region 7 and the n-type regions 9, 9' of the reset transistor 3. and flows out to an external power source (arrows D and E). As a result, unnecessary charges within the potential well 20 are discharged.
After emptying the potential well 20 in this manner, the above-described operations are repeated in sequence.
上記説明中、電荷蓄積段階でポテンシヤルの井
戸20に蓄積される電荷量は、検知しようとする
対象試料の温度に対応する。即ち前記従来例の説
明な中に掲げた例では、凡そ300〔〓〕に対応する
電荷量が蓄積される。この電荷量は図ではポテン
シヤルの井戸20中の電荷はハツチ部21の高さ
で表される。 In the above description, the amount of charge accumulated in the potential well 20 during the charge accumulation stage corresponds to the temperature of the target sample to be detected. That is, in the example given in the description of the conventional example, an amount of charge corresponding to approximately 300 [〓] is accumulated. The amount of charge in the potential well 20 is represented by the height of the hatch 21 in the figure.
本実施例においては次の信号読み出し段階にお
いて、移送ゲート13に印加する電圧を選択して
障壁23の高さを制御することにより、上記ポテ
ンシヤルの井戸20に蓄積された電荷量のうちか
ら、CCD2に移送する電荷量を制御することが
出来る。例えば上記障壁23の高さが280〔〓〕で
あるとすれば、CCD2に移送される電荷量は、
約20〔〓〕の信号に相当する量のみとなり、上記
280〔〓〕の信号に相当する不要電荷は外部に排出
されることとなる。 In this embodiment, in the next signal readout step, by selecting the voltage applied to the transfer gate 13 and controlling the height of the barrier 23, the CCD 2 is selected from the amount of charge accumulated in the potential well 20. The amount of charge transferred to can be controlled. For example, if the height of the barrier 23 is 280 [〓], the amount of charge transferred to the CCD 2 is:
The amount is only equivalent to approximately 20 [〓] signals, and the above
Unnecessary charges corresponding to the 280 [〓] signal will be discharged to the outside.
以上の如く本実施例を用いれば、赤外センサの
検知出力のうちから、望ましくない直流成分を除
去し、所望の信号部分のみを読み出すことが可能
となる。 As described above, by using this embodiment, it is possible to remove undesirable DC components from the detection output of the infrared sensor and read out only the desired signal portion.
第3図は上記一実施例の信号読み出し部の構成
例を示す要部平面図であつて、前記第1図と同一
部分は同一符号を付して示してある。 FIG. 3 is a plan view of essential parts showing an example of the configuration of the signal readout section of the above embodiment, and the same parts as in FIG. 1 are designated by the same reference numerals.
本実施例の信号読み出し部は前述した如く、読
み出し電荷量制御素子1、CCD2、及びリセツ
トトランジスタ3とからなる。読み出し電荷量制
御素子1は同図では1個のみ示したが、実際には
n行m列のマトリツクス状に配列され、CCD2
及びリセツトトランジスタ3は、いずれも上記マ
トリツクスの1行に対して1個設けられている。 As described above, the signal readout section of this embodiment includes the readout charge amount control element 1, the CCD 2, and the reset transistor 3. Although only one readout charge amount control element 1 is shown in the figure, it is actually arranged in a matrix of n rows and m columns, and the CCD 2
One reset transistor 3 is provided for each row of the matrix.
上記読み出し電荷量制御素子1の入力ゲート1
1、蓄積ゲート12、移送ゲート13は、上記マ
タリツクスの各列に対してそれぞれ1本ずつ配設
されている。 Input gate 1 of the readout charge amount control element 1
1. One storage gate 12 and one transfer gate 13 are provided for each column of the matrix.
31,32は逆導電型領域6,7上を被覆する
絶縁膜に開口された電極窓、また33,34はそ
れぞれCCD2の逆導電型領域8及びリセツトト
ランジスタ3の逆導電型領域9上の電極窓であ
る。35は上記リセツトトランジスタ3の電極窓
35から導出され、対応する行の総ての読み出し
電荷量制御素子1の電極窓32、及びCCD2の
電極窓33を連結する配線で、アルミニウム
(Al)のような金属薄層を用いて形成される。 31 and 32 are electrode windows opened in the insulating film covering the opposite conductivity type regions 6 and 7, and 33 and 34 are electrodes on the opposite conductivity type region 8 of the CCD 2 and the opposite conductivity type region 9 of the reset transistor 3, respectively. It's a window. Reference numeral 35 denotes a wiring that is led out from the electrode window 35 of the reset transistor 3 and connects the electrode window 32 of all the readout charge amount control elements 1 and the electrode window 33 of the CCD 2 in the corresponding row, and is made of a material such as aluminum (Al). It is formed using a thin metal layer.
なお上記一実施例はSi基板5をp型、逆導電型
領域をn型とした例を示したが、これを総て反対
としても良い。 Although the above embodiment shows an example in which the Si substrate 5 is of p-type and the region of the opposite conductivity type is of n-type, these may all be reversed.
(f) 発明の効果
以上説明した如く本発明によれば、二次元赤外
センサの読み出しに当つて、背景光などによる直
流成分を抑制して、所望の信号成分のみを取り出
すことが出来る。(f) Effects of the Invention As described above, according to the present invention, when reading out a two-dimensional infrared sensor, it is possible to suppress DC components caused by background light and the like and extract only desired signal components.
第1図〜第3図は本発明の一実施例を示す図
で、第1図は上記一実施例の構造を模式的に示す
要部断面図、第2図はその動作を説明するための
ポテンシヤル図、第3図はその平面配置を示す要
部平面図である。
図において、1は読み出し電荷量制御素子、2
はCCD、3はリセツトトランジスタ、4は光電
変換素子、5は一導電型の半導体基板、6,7,
8,9,9′は逆導電型領域、10は絶縁膜、1
1,12,13はそれぞれ上記読み出し電荷量制
御素子1の多結晶シリコン等よりなる入力ゲー
ト、蓄積ゲート、及び移送ゲート、14,15は
それぞれCCD2の多結晶シリコン等よりなる移
送ゲート及び転送電極、16はリセツトトランジ
スタ3のゲート電極、20及び25はポテンシヤ
ルの井戸、21は蓄積された電荷、22,23,
24,26は電位の障壁、A〜Eは電荷の流れる
方向を示す矢印である。
1 to 3 are diagrams showing one embodiment of the present invention. FIG. 1 is a cross-sectional view of a main part schematically showing the structure of the above-mentioned embodiment, and FIG. 2 is a cross-sectional view for explaining its operation. The potential diagram, FIG. 3, is a plan view of the main parts showing the planar arrangement thereof. In the figure, 1 is a readout charge amount control element, 2
is a CCD, 3 is a reset transistor, 4 is a photoelectric conversion element, 5 is a semiconductor substrate of one conductivity type, 6, 7,
8, 9, 9' are opposite conductivity type regions, 10 is an insulating film, 1
1, 12, and 13 are input gates, storage gates, and transfer gates made of polycrystalline silicon or the like of the readout charge amount control element 1, respectively; 14 and 15 are transfer gates and transfer electrodes made of polycrystalline silicon or the like of the CCD 2; 16 is the gate electrode of the reset transistor 3, 20 and 25 are potential wells, 21 is the accumulated charge, 22, 23,
24 and 26 are potential barriers, and A to E are arrows indicating the direction of charge flow.
Claims (1)
うち所要の信号部分を選択してCCDへ出力し不
要電荷部分をリセツトトランジスタへ排出する読
み出し電荷量制御素子を有する構成の半導体装置
において、該読み出し電荷量制御素子は一導電型
半導体基板表面に互いに離隔して形成された入力
側及び出力側逆導電型領域と、該入力側及び出力
側逆導電型領域に挟まれた領域上に入力ゲート、
蓄積ゲート、及び移送ゲートとを有し、且つ前記
入力側逆導電型領域が前記光電変換素子の出力端
に接続されるとともに、出力側逆導電型領域が前
記リセツトトランジスタのソース端子および前記
CCDの入力端子に接続されてなり、前記入力ゲ
ート、蓄積ゲート、及び移送ゲートの電位をそれ
ぞれ選択制御することにより、時系列的に前記出
力側逆導電型領域から前記光電変換素子の検知出
力のうち、所要の信号部分をCCDへ出力し、も
しくは不要電荷部分をリセツトトランジスタへ排
出することを可能ならしめたことを特徴とする半
導体装置。1. In a semiconductor device having a configuration including a readout charge amount control element that inputs the detection output of a photoelectric conversion element, selects a required signal portion of the input, outputs it to a CCD, and discharges an unnecessary charge portion to a reset transistor. The readout charge amount control element has an input side and an output side opposite conductivity type regions formed on the surface of a semiconductor substrate of one conductivity type, and an input gate on a region sandwiched between the input side and output side opposite conductivity type regions. ,
It has an accumulation gate and a transfer gate, and the input side opposite conductivity type region is connected to the output terminal of the photoelectric conversion element, and the output side opposite conductivity type region is connected to the source terminal of the reset transistor and the
By selectively controlling the potentials of the input gate, storage gate, and transfer gate, the detection output of the photoelectric conversion element is changed over time from the output-side opposite conductivity type region to the input terminal of the CCD. A semiconductor device characterized in that it is capable of outputting a required signal portion to a CCD or discharging an unnecessary charge portion to a reset transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58089820A JPS59214258A (en) | 1983-05-20 | 1983-05-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58089820A JPS59214258A (en) | 1983-05-20 | 1983-05-20 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59214258A JPS59214258A (en) | 1984-12-04 |
JPH0519828B2 true JPH0519828B2 (en) | 1993-03-17 |
Family
ID=13981384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58089820A Granted JPS59214258A (en) | 1983-05-20 | 1983-05-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59214258A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0448057Y2 (en) * | 1985-07-16 | 1992-11-12 | ||
JP2636898B2 (en) * | 1988-09-08 | 1997-07-30 | 富士通株式会社 | Semiconductor device |
JPH0779445B2 (en) * | 1989-08-28 | 1995-08-23 | 日本電気株式会社 | Driving method for charge transfer imaging device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56114479A (en) * | 1980-02-14 | 1981-09-09 | Fujitsu Ltd | Solid-state image pickup device |
-
1983
- 1983-05-20 JP JP58089820A patent/JPS59214258A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56114479A (en) * | 1980-02-14 | 1981-09-09 | Fujitsu Ltd | Solid-state image pickup device |
Also Published As
Publication number | Publication date |
---|---|
JPS59214258A (en) | 1984-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4562474A (en) | Semiconductor image sensor | |
US6855935B2 (en) | Electromagnetic wave detector | |
US6674471B1 (en) | Solid-state imaging device and method for driving the same | |
JPH0312510B2 (en) | ||
US20070109437A1 (en) | Solid state image sensing device | |
JP2005287068A (en) | Image cell for image-recorder chip | |
WO1996031976A1 (en) | Read-out circuit for active matrix imaging arrays | |
JPS5846070B2 (en) | solid-state imaging device | |
JP7562535B2 (en) | Imaging device and electronic device | |
JP3965049B2 (en) | Imaging device | |
JPH0518265B2 (en) | ||
US5235197A (en) | High photosensitivity and high speed wide dynamic range ccd image sensor | |
US5602407A (en) | Switched CCD electrode photodetector | |
JP4099413B2 (en) | Photodetector | |
JPH05235665A (en) | Amplifier circuit | |
JPH0519828B2 (en) | ||
JP2874662B2 (en) | Bolometer type infrared detector | |
US4429330A (en) | Infrared matrix using transfer gates | |
JPH07322150A (en) | Solid-state image pickup device | |
JP2636898B2 (en) | Semiconductor device | |
JP3244557B2 (en) | Input circuit of solid-state image sensor | |
US20020140010A1 (en) | Imaging system | |
JP2576259B2 (en) | Infrared sensor | |
EP0065599B1 (en) | Infrared imaging system with infrared detector matrix, and method of imaging infrared energy | |
JPH0575090A (en) | Semiconductor photodetector |