JP2636898B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a semiconductor device used for a signal readout device of a two-dimensional infrared sensor, overflow can be prevented even when extremely large excess incident light comes in, integration time can be controlled, and various conditions can be controlled. In this configuration, an overflow gate and an overflow drain are formed adjacent to the input source, and a predetermined voltage is applied to each of the overflow gate and the overflow drain for driving.

[Industrial applications]

The present invention relates to a semiconductor device used for a signal reading device of a two-dimensional infrared sensor.

General hybrid two-dimensional infrared sensors composed of a combination of an infrared photodiode array formed on a narrow band gap semiconductor and a CCD are currently used in various fields and are expected to be promising sensors in the future. ing.
In such a sensor, there is no particular problem as long as the incident light amount is within a normally used range, but in some cases, there may be extremely large excess incident light, for example, 1000 times or more of the normally used incident light amount. In such a case, an overflow occurs and a normal sensor function cannot be performed. Therefore, it is necessary to prevent overflow and function as a normal sensor even in the case of such extremely large excess incident light.

[Conventional technology]

FIG. 8 shows the applicant's Japanese Patent Application No. 58-89820 (Japanese Unexamined Patent Application Publication No.
14258), a sectional view of a semiconductor device proposed in
The figure is a potential diagram for explaining the operation of the device shown in FIG.
10 shows plan views of the device shown in FIG. 8, respectively.

The semiconductor device shown in FIG. 8 and FIG. 10 is a signal reading device of a two-dimensional infrared sensor for the purpose of suppressing unnecessary DC components generated by background light or the like and extracting only desired signal components. . These are input-side and output-side reverse conductivity type regions 6, 7, 8, 9, 9 'formed separately from each other on the surface of the one conductivity type semiconductor substrate 5, and these regions 6, 7, 8, 9, 9'. , 9 ', the read charge control element 1 having an input gate 11, a storage gate 12, and a transfer gate 13 constitutes a means for selecting and outputting a desired signal portion and a means for discharging unnecessary charges.
The input side region 6 is connected to the output end of the photoelectric conversion element 4 and the potentials of the input gate 11, the storage gate 12, and the transfer gate 13 are selectively controlled, respectively, so that the photoelectric conversion from the output side regions 7, 8, 9, 9 'is performed. In the detection output of the element 4, it is possible to selectively output a desired signal portion and discharge unnecessary charges. 2 is CC
In D, 14 is its transfer gate and 15 is its transfer electrode.
3 is a reset transistor, and 16 is its gate electrode. 10 is an insulating film, and 17 is a read line.

A DC voltage of about 0.1 V is always applied to the input gate 11. As a result, as shown in FIG. 9 (A), the potential immediately below the input gate is lowered, and the barrier 22 is slightly lowered. In this state, a voltage of about 10V is applied to the storage gate 12, and the potential of the transfer gate 13 is set to 0V. As a result, the potential immediately below the storage gate 12 is deeper than the potential immediately below the input gate 11, forming a potential well 20, and a charge corresponding to the light intensity detected by the photoelectric conversion element 4 is transferred to the region 6.
Flows into the potential well 20 via the arrow (arrow A),
21 accumulates in the potential well 20. At this time, the potential immediately below the transfer gate 13 is kept high, and the barrier 23 is formed, so that the charges in the potential well 20 do not flow out.

Next, a voltage of about 2 V is applied to the transfer gate 13, while a voltage of about 3 V is applied to the transfer gate 14. Thereby, the ninth
As shown in FIG. 3B, the barrier 23 immediately below the transfer gate 13 and the barrier 24 immediately below the transfer gate 14 are lowered, and the potential well is reduced.
The electric charge 21 in 20 flows into the potential well 25 of the CCD 2 over the barriers 23 and 24 (arrows B and C).

Next, the voltage of the transfer gate 14 is set to 0 V, the barrier 24 is raised to stop the charge transfer to the CCD 2 as shown in FIG. 9C, and a predetermined voltage is applied to the transfer electrode 15. As a result, the charges in the potential well 25 are transferred and read out as data. On the other hand, a voltage of about 1 V is applied to the storage gate 12 to raise the potential immediately below the storage gate 12, and a voltage of about 3 V is applied to the gate electrode 16 of the reset transistor 3 to lower the potential immediately below the gate 16, and a barrier 26 is formed. make low. As a result, the charge remaining in the potential well 20 flows out to the external power supply through the region 7 and the regions 9, 9 '(arrows D and E), and unnecessary charges in the potential well 20 are discharged. The above operation is repeated.

Thus, the apparatus shown in FIGS. 8 and 10 selects the voltage to be applied to the transfer gate 13 at the time of signal reading, and
By controlling the height of 23, the potential well, 20
The amount of charge transferred to the CCD 2 out of the amount of charge accumulated in the CCD 2 can be controlled, and unnecessary charge remaining in the potential well 20 can be discharged to the outside. Therefore, an unnecessary DC component due to background light or the like can be removed from the detection output of the sensor, and only a desired signal portion can be read.

[Problems to be solved by the invention]

In the device previously proposed by the present applicant, neither the region 6 (input source) nor the storage gate 12 has a function for preventing overflow. This discharges the electric charge in the potential well 20 to the outside by the operation of the reset transistor 3 as described above. This is also effective when excessive incident light of several times that in normal use enters. In the case where excessively large incident light, for example, 1000 times or more that of normal use enters, the electric charge in the potential well 20 overflows immediately after resetting and flows out (overflows) to the read line 17. As described above, under such a condition that extremely large excess incident light enters, overflow occurs, and there is a problem that a normal sensor operation cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which can prevent overflow even when extremely large incident light enters, can control the integration time, and can operate normally under various conditions.

[Means for Solving the Problems] In a semiconductor device according to the present invention, an overflow gate and an overflow drain are formed adjacent to an input source. The overflow gate and the overflow drain are driven by applying a predetermined voltage to each of them, and the overflow gate satisfies the relationship of (threshold voltage V _T ) <V _L <(input gate applied voltage V _IG ) <V _H. Voltage _VL and voltage _VH
Is applied with a pulse width of a predetermined time width having each level.

[Action]

V _{H in} overflow mode in absorption mode, in integration mode
A voltage of V _L (<V _H ) is applied. As a result, in the integration mode, the barrier of the overflow gate is slightly lowered, and when excessive incident light enters, the charge overflowing from the storage gate is absorbed by the overflow drain through the lowered barrier of the overflow gate and overflows. Can be prevented. In addition, by controlling the voltage _VL application time, the integration time can be controlled, and the charge storage amount can be easily controlled. Also,
The overflow gate, applying a pulse voltage of a predetermined time width with each level of (the threshold voltage V _T) <V _L <(Input gate application voltage V _IG) <voltage satisfying V _H the relationship V _L and V _H Thus, overflow can be prevented by setting only one voltage VOFG.

〔Example〕

FIG. 1 is a sectional view of an embodiment of the device of the present invention, and FIG. 2 is a potential diagram for explaining the operation thereof. 1, the same components as those of FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 1, reference numeral 30 denotes an overflow gate, and reference numeral 31 denotes an overflow drain, which is provided adjacent to the input source 6, and is configured so that different voltages can be applied to the respective terminals 30a and 31a. In this case, the overflow gate 30 and the overflow drain 31 are of course provided for each unit cell. That is, input source 6, input gate
11, the storage gate 12, the transfer gate 13, and the output drain 7 are unit cells, the transfer gate 13, the output drain 7 are connected in a matrix in the x and Y directions, and the output of the photoelectric conversion element array is connected to each input source. To the commonly connected output drain
This is a two-dimensional sensor that combines parallel inputs of CCD.

Here, in a state of applying a high degree of voltage V _D on the overflow drain 31 through a terminal 31a, a low voltage is applied V _H than this overflow gate 30 through a terminal 30a. On the other hand, a voltage V _IG (<V _H ) is applied to the input gate 11,
The voltage of the transfer gate 13 is 0 V (threshold voltage V _T ). That is,
V _T <V _IG <V _H <V _D As a result, as shown in FIG. 2A, the barrier 32 immediately below the overflow gate 30 is formed.
Is lowered by the overflow gate voltage _VH , and the charge from the photoelectric conversion element 4 is absorbed by the overflow drain 31 across the barrier 32 (absorption mode).

Next, a voltage lower than the voltage V _H to the overflow gate 30
Apply _VL . At this time, the voltage of the input gate 11 is V _IG ,
The voltage of the transfer gate 13 remains at 0V. That is, V _T <V _L <
V _IG <V _H <V _D By an overflow gate voltage V _L, as shown in FIG. 2 (B), the barrier 32 is slightly lower than even the threshold voltage V _T is increased, thereby, the charge from the photoelectric conversion element 4 is shielding by the barrier 32 Girare , Input gate 11
Potential well of storage gate 12 over barrier 33 directly below
Stored at 34 (integration mode).

At this time, the transfer gate 13
13 When the barrier 35 directly below is high, for example, 1000 for normal use
As shown in FIG. 2 (C), when extremely large excess incident light more than twice enters, the charge in the potential well 34 immediately below the storage gate 12 overflows, but the barrier 32 is slightly lowered by the overflow gate voltage _VL . Therefore, the overflowed charges are absorbed by the overflow drain 31 over the barrier 32 and do not flow out (overflow) to the read line (overflow prevention mode).

Thus, the overflow gate voltage V _H is applied during the absorption operation shown in FIG. 2A, and the overflow gate voltage V _L (<V _H ) is applied during the integration operation shown in FIG. 2B. Since 32 is set slightly lower, even if there is an extremely large excess input, the charge only flows to the overflow drain 31 by crossing the barrier 32 and does not overflow to the read line. FIG. 3 shows a time chart of each voltage for only the absorption operation and the integration operation.

Next, when reading is performed after normal integration is performed, a predetermined voltage is applied to the transfer gate 13. At this time, the overflow gate voltage _VL is kept applied. By applying a voltage to the transfer gate 13, the barrier 35 is lowered. Although not shown, the charge in the potential well 34 immediately below the storage gate 12 flows into the output drain 7 over the lowered barrier 35 and is extracted as data. Also at this time, since the barrier 32 is slightly lowered by the overflow gate voltage _VL , the overflow can be prevented as described above.

FIG. 4 is a cross-sectional view of another embodiment of the apparatus of the present invention. In FIG. 4, the same components as those in FIG. In FIG. 4, reference numeral 36 denotes an overflow gate 30.
And the overflow drain 31 are commonly connected. This does not apply separate voltages to the overflow gate 30 and overflow drain 31,
A common negative voltage is applied to 36.

Here, as shown in FIG.
Potential V _D 'is overflow gate voltage applied to the terminal 36 of the
Although the potential is the same as V _OFG , the potential φ _s immediately below the overflow gate 30 is divided by the influence of the gate capacitance and the depletion capacitance and is always lower than the potential V _D '. This allows
As in the embodiment shown in FIG. 1, the overflow gate voltage V
_{Even if} two types of _OFG and overflow drain voltage V _OFD are not set, only one voltage V _OFG is set and V _T <V _L
<V _IG <V _H <V _D ′ can be satisfied, and the overflow prevention described with reference to FIG. 2 can be realized. In this case, the third
As shown, the overflow drain potential V _D ′ is a voltage
It goes up and down according to V _H and V _L.

By the way, in the present invention, as shown in FIG. 6 (for two cells) and FIG. 7 (for four cells), the overflow drain 21 (OFD) can be shared for each cell. Thereby, high-density arrangement becomes possible. In each figure, SG is a storage gate, IG is an input gate, TG is a transfer gate, D is an output drain, S is an input source, OFD is an overflow drain, and OFG is an overflow gate.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent overflow even when extremely large excess incident light (for example, 1000 times or more of normal use) that cannot completely discharge charges even by the operation of the reset transistor comes in. In addition, the integration time can be controlled, the charge storage amount can be easily controlled, and normal operation can be performed under various conditions. Moreover, the overflow gate (threshold voltage V _T) <V _L <(Input gate application voltage V _IG) <voltage V _L and the pulse voltage of a predetermined time width with each level of the voltage V _H which satisfies V _H the relationship Is applied, overflow can be prevented by setting only one voltage V _OFC .

[Brief description of the drawings]

1 is a sectional view of one embodiment of the present invention, FIG. 2 is a potential diagram of the apparatus shown in FIG. 1, FIG. 3 is a time chart of each voltage during absorption and integration, and FIG. FIG. 5 is a cross-sectional view of another embodiment, FIG. 5 is a voltage characteristic diagram of the device shown in FIG. 4, FIG. 6 is a plan view of a two-cell configuration in the device of the present invention, and FIG. FIG. 8 is a cross-sectional view of the device proposed by the present applicant, FIG. 9 is a potential diagram of the device shown in FIG. 8, and FIG. 10 is a plan view of the device shown in FIG. . In the figure, 4 is a photoelectric conversion element, 5 is a negative conductivity type semiconductor substrate, 6 is an input source (S), 7 is an output drain (D), 11 is an input gate (IG), 12 is a storage gate (SG), 13 Is a transfer gate (TG), 30 is an overflow gate (OFG), 30a, 31a, and 36 are terminals, 31 is an overflow drain (OFD), 32, 33, and 35 are barriers, and 34 is a potential well. Is shown. V _T represents the threshold voltage, V _H, V _L is the overflow gate voltage, V _IG input gate voltage, V _D, the V _D 'is overflow drain voltage.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Wakayama 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Isao Tofuku 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 56) References JP-A-58-106966 (JP, A) JP-A-59-214258 (JP, A) JP-A-62-160759 (JP, A) JP-A-56-160176 (JP, A)

Claims (3)

(57) [Claims] An input source (6), an input gate (11), a storage gate (12), a transfer gate (13), and an output drain (7) are unit cells, and the transfer gate (13) and the output drain ( 7) A two-dimensional sensor that is connected in a matrix in the x and y directions, the output of the photoelectric conversion element (4) array is connected to each input source, and the parallel input of the CCD is connected to the commonly connected output drain. The overflow gate (30) adjacent to the input source.
And an overflow drain (31) are formed, and a predetermined voltage is applied to each of the overflow gate (30) and the overflow drain (31) to drive the overflow gate (30). V _T )
<V _L <(Input gate applied voltage V _IG ) <V _H. A semiconductor device characterized by applying a pulse voltage of a predetermined time width having each level of voltage V _L and voltage V _H satisfying a relationship of V _H. 2. The semiconductor device according to claim 1, wherein said overflow gate (30) and said overflow drain (31) are commonly connected. 3. The semiconductor device according to claim 1, wherein said overflow drain is configured to be shared by a plurality of adjacent unit cells.