JP4866257B2 - Semiconductor image sensor - Google Patents

Description

  The present invention relates to a semiconductor image pickup device, and more specifically, it is possible to pick up an image with a wide dynamic range even when a region with a large luminance difference is mixed in a visual field, and to detect a sufficient contrast in the entire region. The present invention relates to a possible semiconductor imaging device.

Solid-state imaging devices such as CCD (Charge-coupled device) and CMOS (Complementary mental-oxide semiconductor) imagers, so-called semiconductor image sensors (hereinafter also referred to as “semiconductor imaging devices”) are used in video cameras and digital cameras. Now, it is also incorporated in mobile phones and the like, and it is widely used as an image sensor with low cost and low power consumption.

  However, the sensing ability of the semiconductor image sensor is greatly inferior to human visual sensing. In human vision, even if there is a luminance distribution of about 4 to 5 digits in one visual field, it is possible to sufficiently detect the contrast between a bright place and a dark place. This excellent contrast sensing ability is realized by a function that allows the light-receiving cells in the retina to adjust their light-sensitive characteristics for each individual cell.

On the other hand, in the conventional semiconductor imaging device, since all the pixels have the same light receiving characteristics, it is difficult to obtain sufficient contrast at the same time in a bright place and a dark place in the field of view. For this reason, in order to realize a wide light receiving sensitivity range and a high contrast detection function, a configuration of a semiconductor imaging device having a mechanism capable of shifting the light receiving sensitivity range in each pixel circuit in accordance with the amount of light incident on the peripheral pixels. Are disclosed (for example, Patent Documents 1 and 2).
JP 2000-34079A JP 2005-160031 A

  However, in the configuration disclosed in Patent Document 1, in each pixel circuit, a first light receiving detection element for detecting its own amount of received light and other pixels for detecting the average amount of received light in the neighboring pixels. It is necessary to dispose two light receiving detection elements, which are a second light receiving detection element connected to each other via a resistance element. For this reason, there is a risk that the pixel size reduction, which is indispensable for meeting the recent demand for higher resolution, may be difficult.

  In addition, since the first and second light receiving detection elements are connected in series in each pixel circuit, noise that has flowed into a node electrically connected to the peripheral pixel circuit is the first light receiving detection element. May be superimposed on the photocurrent of the light source, which may make it easier to pick up noise and reduce detection accuracy.

  Further, in the configuration disclosed in Patent Document 2, although there is one light receiving detection element arranged in each pixel circuit, it is necessary to handle a plurality of types of signal currents in one pixel circuit. The configuration of the peripheral circuit becomes complicated. Due to such a complicated peripheral circuit, there is a possibility that high accuracy is required for manufacturing each component (particularly, transistor) of the pixel circuit in order to suppress variation in characteristics between pixels.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a sufficient contrast between a bright part and a dark part even when the luminance distribution in one field of view is large. It is to provide a highly accurate and small-sized semiconductor imaging device that can be detected with a simple circuit configuration.

  A semiconductor image pickup device according to the present invention includes a plurality of pixel circuits divided into a plurality of pixel groups, an accumulated charge discharging circuit provided for each pixel group, and a readout circuit. Each pixel group includes a plurality of pixel circuits. Each pixel circuit includes a first light receiving detection element, a first node having a predetermined capacity, and a first initialization circuit. The first light receiving detection element is configured to generate a signal charge corresponding to the amount of light incident on the pixel circuit. The first node is configured to accumulate signal charges generated by the first light receiving detection element. The first initialization circuit is configured to clear the signal charge stored in the first node in response to switching of the frame period. When the incident light to the corresponding pixel group is strong in a predetermined period set in advance at a predetermined timing in each frame period, the accumulated charge discharging circuit is configured so that each of the plurality of pixel circuits included in the pixel group includes A charge discharging operation for discharging signal charges from one node is executed. The readout circuit outputs, for each pixel circuit, an electrical signal corresponding to the amount of signal charge accumulated in the first node at an output timing set at a predetermined timing after the predetermined period in each frame period. Composed.

  According to the semiconductor imaging device, when the incident light to the pixel group is strong (high illuminance) by the accumulated charge discharging circuit provided for each pixel group, the signal charge accumulated in each pixel circuit is 1 At an intermediate timing (predetermined timing) of the frame period, it is possible to temporarily discharge an amount corresponding to the amount of incident light so far. Therefore, at high illuminance, it is possible to perform imaging with an expanded dynamic range according to the ratio of one frame period to the re-accumulation period from the predetermined timing to the output timing in one frame period. On the other hand, when the incident light to the pixel group is weak (low illuminance), the signal charge discharging operation by the accumulated charge discharging circuit is not executed, and imaging is performed while ensuring contrast without expanding the dynamic range. Can do.

  With this, a simple circuit configuration that detects the amount of received light based only on the accumulated amount of signal charges generated by the received light detection element in a single light reception detection element arranged in each pixel circuit, at high illuminance. By expanding the dynamic range, it is possible to detect a sufficient contrast between a bright part and a dark part even when the luminance distribution in the field of view is large.

  Preferably, in the semiconductor imaging device, the accumulated charge discharging circuit includes a capacitor unit and a control unit. The capacitor unit is configured to accumulate the signal charge that has flowed out from each first node in the plurality of pixel circuits due to the saturation of the signal charge at the first node. The control unit is configured to increase the amount of signal charge discharged from each first node in a predetermined period in accordance with an increase in the amount of signal charge accumulated in the capacitor unit. The signal charge stored in the capacitor is cleared in response to the end of the predetermined period.

  By adopting such a configuration, the intensity of incident light in the pixel group is determined according to the accumulation amount of the signal charge flowing out from the light receiving detection element in the pixel circuit in the same pixel group due to the saturation of the signal charge. Thus, it is possible to control whether or not the signal charge discharging operation by the accumulated charge discharging circuit is necessary.

  More preferably, in the semiconductor image pickup device, the accumulated charge discharging circuit further includes a second light receiving detection element for generating a signal charge corresponding to the amount of light incident on the accumulated charge discharging circuit. The capacitor unit is configured to further accumulate signal charges generated by the second light receiving detection element.

  With such a configuration, a signal charge generated by a single light reception detection element (second light reception detection element) shared by a plurality of pixel circuits in the same pixel group, and each signal in the pixel group It is possible to detect that the incident light amount of the pixel group is large by both the signal charge saturated by the light receiving detection element (first light receiving detection element) in the pixel circuit, and in response to this, the accumulated charge discharging circuit Thus, it is possible to execute the operation of releasing the signal charge. Thereby, since one frame period necessary for obtaining the same dynamic range at high illuminance is relatively shortened, it is possible to perform higher-speed imaging.

  Preferably, the accumulated charge discharging circuit includes a second light receiving detection element, a capacitor unit, and a control unit. The second light receiving detection element is configured to generate a signal charge corresponding to the amount of light incident on the accumulated charge discharging circuit. The capacitor unit is configured to accumulate the signal charge generated by the second light receiving detection element. The control unit is configured to increase the amount of signal charge discharged from each first node in a predetermined period in accordance with an increase in the amount of signal charge accumulated in the capacitor unit. The signal charge stored in the capacitor is cleared in response to the end of the predetermined period.

  With such a configuration, the amount of incident light on the pixel group is detected by a single light receiving detection element (second light receiving detection element) shared by a plurality of pixel circuits in the same pixel group. Depending on the detection result, it is possible to control whether or not the signal charge discharging operation by the accumulated charge discharging circuit is necessary.

  Alternatively, preferably, in the semiconductor imaging element, the accumulated charge discharging circuit includes a second node having a predetermined capacity, a variable resistance element, a control unit, and a control switch element. The variable resistance element is disposed so as to electrically connect each of the first nodes in the plurality of pixel circuits to the second node. The control unit is configured to decrease the resistance value of the variable resistance element in accordance with an increase in signal charge transmitted from the first node and accumulated in the second node. The control switch element is arranged between a potential node that supplies a predetermined potential for attracting signal charges and the second node, and disconnects the potential node and the second node in a predetermined period. On the other hand, the potential node and the second node are connected outside the predetermined period.

  With such a configuration, during a period other than the predetermined period in which the accumulated charge discharging circuit operates, the accumulation is performed using the capacitance formed in the second node that operates as the overflow drain by being coupled with the predetermined potential. The mechanism of the charge discharging circuit can be realized. That is, the configuration of the present invention can be realized by using the overflow drain capacitance and reducing the number of circuit elements that need to be newly arranged.

  More preferably, in the semiconductor imaging element, the accumulated charge discharging circuit further includes a second light receiving detection element for generating a signal charge corresponding to the amount of light incident on the accumulated charge discharging circuit. The second light receiving detection element is configured such that the generated signal charge is accumulated in the second node.

  With this configuration, the amount of incident light on each pixel group can be detected by the second light receiving detection element configured using the second node capable of operating as an overflow drain capacitance. Therefore, the number of circuit elements that need to be newly arranged can be reduced, and the configuration of the present invention can be realized.

  In particular, in the above-described semiconductor imaging device, the variable resistance element has a first electric field using the first impurity diffusion region constituting the first node as a source and the second impurity diffusion region constituting the second node as a drain. Includes effect transistors. The control unit is configured to control the gate potential of the first field-effect transistor so that the channel resistance between the source and the drain decreases as the signal charge accumulated in the second node increases. . Further, each pixel circuit is configured to transfer the signal charge accumulated in the first impurity diffusion region to the third impurity diffusion region by turning on in the saturation region or the linear region at the output timing. And a second initialization circuit for clearing signal charges in the third impurity diffusion region prior to turning on of the second field effect transistor within the same frame period. The readout circuit is configured to output an electrical signal corresponding to the amount of signal charge accumulated in the third impurity diffusion region.

  With such a configuration, signal charges accumulated in the first impurity diffusion region corresponding to the first node are formed between the second impurity diffusion region and the third impurity diffusion region, respectively. The first and second field effect transistors can be transmitted to the stored charge discharging circuit or the reading circuit. As a result, the signal charge can be taken out without providing a contact point that makes a direct physical contact with the first node. High structure can be obtained.

  Preferably, in the semiconductor imaging device, the accumulated charge discharging circuit is formed in a region surrounded by a plurality of pixel circuits included in a corresponding pixel group in a plane that receives incident light.

  With such a configuration, the accumulated charge discharging circuit can be efficiently arranged, which can contribute to the downsizing of the semiconductor imaging device.

  According to the present invention, even when the luminance distribution in one field of view is large, it is possible to detect a bright part and a dark part with sufficient contrast, and a highly accurate and small semiconductor image sensor is realized with a simple circuit configuration. can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

(Embodiment 1)
FIG. 1 is a circuit diagram illustrating a schematic configuration of a main part of a conductor image pickup device according to Embodiment 1 of the present invention.

  Referring to FIG. 1, the pixel circuit 10 includes a photodiode PD as a light receiving detection element, a transfer gate 12, a reset switch 14, a voltage amplifier 16, and a pixel selection switch 18.

  The reset switch 14 is arranged between the power supply potential node 5 that supplies the power supply potential VDD and the node Nf that acts as a floating diffusion, and is turned on / off in response to the reset control signal RF. The transfer gate 12 is connected between a node N1 where signal charges are accumulated by the generation of photocurrent by the photodiode PD and the node Nf. On / off of the transfer gate 12 is controlled by a transfer control signal TG.

  The photodiode PD is arranged between the ground node 6 that supplies the ground potential VSS and the node N1. The anode of the photodiode PD is biased to the ground potential VSS by the ground node 6. The node N1 corresponds to the cathode of the photodiode PD. That is, in the pixel circuit 10, the signal charge is electrons (negative charge) that are majority carriers at the cathode (n-type).

  Note that in this embodiment, the power supply potential VDD and the ground potential VSS are in a relationship of VDD> VSS, and a bias necessary for circuit operation can be given by a potential difference of (VDD−VSS). Each can be set to any potential. That is, it will be described in a positive manner that the ground potential VSS can be set to any potential other than the ground potential (a negative potential is also acceptable).

  The voltage amplifier 16 is constituted by, for example, a source follower circuit, and its input node is connected to the node Nf, and its output node is connected to the output node No via the pixel selection switch 18. On / off of the pixel selection switch 18 is controlled by a pixel selection control signal PS.

  In the semiconductor imaging device according to the present invention, the plurality of pixel circuits 10 arranged on the light receiving surface are arranged so as to constitute one group (pixel group) for every N (N ≧ 2) integer pixel circuits 10. The An accumulated charge discharging circuit 20 is arranged for each pixel group. In the illustration of the first embodiment, one pixel group is configured for every four adjacent pixel circuits 10.

  The accumulated charge discharging circuit 20 is shared by N (four in this embodiment) pixel circuits 10 included in the same pixel group. The accumulated charge discharging circuit 20 includes a node N2, a control switch 24, an inverting amplifier 26, and N charge discharging gates DG. An overflow drain capacitor 22 is formed at the node N2.

  Control switch 24 is connected between power supply potential node 5 and node N2, and is turned on / off in response to control signal RO. The inverting amplifier 26 is configured such that the higher the potential of the node N2, the lower the potential Vg of the output node (hereinafter also referred to as output potential Vg), and conversely, the lower the potential of the node N2, the higher the output potential Vg. The

  The charge discharge gate DG is connected between the node N1 in each pixel circuit 10 included in the same pixel group and the node N2 in the accumulated charge discharge circuit 20, and functions equivalently as a variable resistor. The electric resistance of the charge discharge gate DG is controlled according to the output potential Vg of the inverting amplifier 26. Specifically, each charge discharge gate DG is configured such that the electrical resistance of each charge discharge gate DG decreases as the output potential Vg increases, and the electrical resistance of each charge discharge gate DG increases as the output potential Vg decreases. Is done.

FIG. 2 shows an arrangement example of pixel circuits and accumulated charge discharging circuits for each pixel group.
Referring to FIG. 2, photodiodes PD of each pixel circuit 10 are arranged in a matrix within a light receiving surface that receives incident light (region 30). One pixel group 2 is formed by four pixel circuits 10 adjacent in the X direction and the Y direction within the light receiving surface. Circuit elements other than the photodiode PD of each pixel circuit 10 are arranged by appropriately using the region 36 between the regions 30 where the photodiode PD is provided. The transfer gate 12 of each pixel circuit 10 is arranged corresponding to the boundary region 35 between the region 30 and the region 36.

  In the accumulated charge discharging circuit 20, the node N2 (overflow drain capacitance 22) is formed in a region 34 surrounded by the arrangement region 30 of N (four) photodiodes PD included in the same pixel group. Further, the charge discharge gate DG is arranged corresponding to the boundary region 32 between the region 30 and the region 34. The other circuit elements of the accumulated charge discharging circuit 20 are also arranged using the region 36 as appropriate.

  As described above, in each pixel group 2, the accumulated charge discharging circuit 20 is disposed in the region 3 surrounded by N (four) pixel circuits 10 constituting the pixel group. Further, the positional relationship between the node N2 (region 34) and the photodiode PD (region 30) is common to each pixel circuit 10 so that the operations as the variable resistors of the charge discharge gates DG are the same. .

  Next, specific structures of the pixel circuit 10 and the accumulated charge discharging circuit 20 shown in FIG. 1 will be described with reference to FIG. FIG. 3 shows an example of the structure of one pixel circuit 10 in the same pixel group and the accumulated charge discharging circuit 20 connected thereto, and FIG. 3 corresponds to a cross-sectional view taken along the line III-III in FIG. .

  Referring to FIG. 3, p-type silicon substrate 100 is supplied with ground potential VSS by ground node 6 as the substrate potential. On the main surface of p-type silicon substrate 100, n + diffusion regions 110 and 120 and buried n- diffusion region 130 are formed.

  The n + diffusion region 110 corresponds to the node N2 in FIG. 1, and a conductive light shielding plate 115 is formed above the n + diffusion region 110 (on the light receiving surface side). Overflow drain capacitance 22 is formed by a junction capacitance between p-type silicon substrate 100 and n + diffusion region 110.

  A p-type region is formed on the buried n− diffusion region 130. The photodiode PD in FIG. 1 is configured by the pn junction between the n− diffusion region 130 and the upper and lower p-type regions. That is, in the first embodiment, the photodiode PD is configured as a buried diode.

  A gate electrode 145 is formed above the channel region between the n + diffusion region 110 and the n− diffusion region 130 via an insulating layer 140. Thus, an n-MOS transistor 160, which is a field effect transistor having the n− diffusion region 130 as a source, the n + diffusion region 110 as a drain, and the gate electrode 145 as a gate, is configured. The n-MOS transistor 160 constitutes the charge discharge gate DG shown in FIG.

  Gate electrode 145 is connected to the output node of inverting amplifier 26. That is, the gate potential of the n-MOS transistor 160 becomes the output potential Vg of the inverting amplifier 26. The inverting amplifier 26 is realized, for example, with a circuit configuration as shown in FIG.

  Referring to FIG. 4, inverting amplifier 26 includes two n-MOS transistors 27 and 28 connected in series.

  The n-MOS transistor 27 is connected between the output node N 3 where the output potential Vg is generated and the power supply potential node 5, and its gate is connected to the power supply potential node 5. On the other hand, n-MOS transistor 28 is connected between output node N3 and ground node 6, and has its gate connected to node N2. Output node N3 is connected to gate electrode 145 shown in FIG.

  Therefore, when the control switch 24 is turned on and the node N2 is connected to the power supply potential VDD, the node N3 is set to a low potential Vl that is a predetermined potential higher than the ground potential VSS. On the other hand, when the potential of the input node N2 drops to the ground potential VSS, the potential becomes a high potential Vh that is lower than the power supply potential VDD by a predetermined potential. As described above, the output potential Vg of the inverting amplifier 26 changes within the range of the low potential Vl (> VSS) and the high potential Vh (<VDD) in accordance with the potential of the node N2 as an input.

  Referring to FIG. 3 again, by controlling the gate potential of the n-MOS transistor 160 with the inverting amplifier 260, the electric resistance of each charge discharge gate DG is when the control switch 24 is on (Vg = Vl). When the control switch 24 is turned off, the maximum value Rh decreases, and the voltage decreases within the range up to the minimum value Rl when Vg = Vh (that is, when the node N2 decreases to the ground potential VSS) according to the potential decrease of the node N2. Even when the control switch 24 is turned on, the n-MOS transistor 160 is not completely turned off, so that a signal charge transmission path from the node N1 to the node N2 can be formed.

  During the ON period of the control switch 24, the node N2 (ie, the n + diffusion region 110) functions as an overflow drain by being connected to the power supply potential VDD. Here, the operation of the overflow drain will be described with reference to FIGS.

  As shown in FIG. 5A and FIG. 5B showing the potential distribution in the XX cross section, when the incident light to the photodiode PD is strong, the signal charge 70 (negative charge) is large. Therefore, the potential well 60 formed by the photodiode is filled with the signal charge 70 and becomes saturated. As a result, the overflowing signal charge 70 flows into the potential well 65 of the adjacent photodiode PD via the substrate region SUB, and a phenomenon called so-called blooming occurs that is detected as a false signal.

  For this reason, as shown in FIG. 6A and FIG. 6B showing the potential distribution in the XX cross section, the lateral overflow drain OFD for absorbing the signal charge 70 overflowing from the photodiode PD is obtained. Is arranged between the photodiodes PD. The lateral overflow drain OFD is formed by biasing an impurity diffusion region of a predetermined conductivity type (n + diffusion region 110 in FIG. 3) with a predetermined potential (power supply potential VDD in this embodiment) that can attract the signal charge 70. Is done. As shown in the XX cross-sectional view, by providing the lateral overflow drain OFD, the signal charge 70 overflowing from the photodiode PD can be absorbed, so that the blooming phenomenon (FIG. 5) can be prevented. The above-described lateral overflow drain is a technique generally used as a countermeasure against blooming, like the vertical overflow drain, which forms an overflow drain in the direction toward the deep part of the silicon substrate.

  Referring again to FIG. 3, n− diffusion region 110 is disconnected from power supply potential VDD during the OFF period of control switch 24. For this reason, the signal charge overflowing from each photodiode PD (specifically, the node N1) of each pixel circuit 10 is caused by the overflow drain capacitance 22 formed between the p-type silicon substrate 100 and the n− diffusion region 110. Accumulated.

  Therefore, when the incident light to each pixel circuit 10 in the pixel group 2, that is, the pixel group 2 is strong, the signal charge overflowing from each photodiode PD is accumulated and the node N2 The potential decreases. As a result, as the output potential Vg of the inverting amplifier 26 increases, the electrical resistance of each charge discharge gate DG (channel resistance of the n-MOS transistor 160) decreases, and therefore, accumulation from the node N1 of each pixel circuit 10 occurs. The charge discharging operation to the node N2 of the charge discharging circuit 20 is promoted.

  On the other hand, when the incident light to the pixel group 2 is weak and the signal charge does not flow out from each photodiode PD, the potential of the node N2 does not decrease from the power supply potential VDD. At this time, since the output potential Vg of the inverting amplifier 26 does not rise, the electrical resistance of each charge discharge gate DG (channel resistance of the n-MOS transistor 160) is maintained in the same manner as when the n + diffusion region 110 operates as an overflow drain. Is done.

  As described above, the accumulated charge discharging circuit 20 for performing the charge discharging operation can be configured while suppressing the additionally required circuit elements and their arrangement areas by using the overflow drain.

  On the other hand, a gate electrode 155 is formed in the channel region between the n + diffusion region 120 and the n− diffusion region 130 via the insulating film 150. As a result, an n-MOS transistor 170 is formed, which is a field effect transistor having the n− diffusion region 130 as a source, the n + diffusion region 120 as a drain, and the gate electrode 155 as a gate. The n-MOS transistor 170 constitutes the transfer gate 12 shown in FIG.

  A transfer control signal TG is input to the gate electrode 155. During the high level (hereinafter also referred to as H level) period of the transfer control signal TG, the n-MOS transistor 170 is turned on in the saturation region or the linear region, and the signal charge accumulated in the n− diffusion region 130 is changed to the n + diffusion region 120. Forwarded to N + diffusion region 120 is connected to power supply potential node 5 through reset switch 14 and to the input node of voltage amplifier 16. That is, the n + diffusion region 120 corresponds to the node Nf as the floating diffusion shown in FIG.

  In this way, by forming the transfer gate 12 (FIG. 1) by the n-MOS transistor 170, the n-diffusion region 130 is stored without providing a contact point that directly contacts the n-diffusion region 130 directly. It is possible to take out the signal charge. That is, the arrangement of the transfer gate 12 makes it possible to apply the present invention to the buried diode. In the buried diode, since the signal charge storage node (node N1) is not physically directly connected to other nodes, highly accurate photoelectric detection with improved noise resistance can be expected.

Next, operations of the pixel circuit 10 and the accumulated charge discharging circuit 20 will be described.
Referring to FIG. 1 again, in each pixel circuit 10, the photodiode PD generates a photocurrent corresponding to the incident light of the pixel circuit 10, and a signal charge (negative charge) is generated according to the generation of the photocurrent. The signal charge is accumulated in the node N1.

  As described above, the accumulated charge discharging circuit 20 exhibits different functions according to the on / off state of the control switch 24. During the ON period of the control switch 24, the node N2 (n + diffusion region 110 in FIG. 3) is connected to the power supply potential VDD, so that the signal charge overflowing due to saturation is discharged from the photodiode PD. 20 functions as an overflow drain shared by the pixel circuits 10 in the same pixel group.

  On the other hand, the accumulated charge discharging circuit 20 accumulates signal charges overflowing from the photodiode PD of each pixel circuit 10 in the same pixel group during the OFF period of the control switch 24, thereby entering the corresponding pixel group. A potential corresponding to the amount of light is generated at the node N2. When the incident light is strong (the amount of light is large), the electrical resistance of the charge discharge gate DG decreases as the potential of the node N2 decreases, so that the accumulated charge discharge circuit 20 is connected to the node N1 of each pixel circuit 10. A “signal charge discharging operation” is executed to discharge the signal charge accumulated up to that point to the node N2. On the other hand, when the incident light is weak (the amount of light is small) and the potential of the node N2 does not decrease, the electric resistance of the charge discharging gate DG is maintained at a high resistance, so that the accumulated charge discharging circuit 20 discharges the signal charge. The operation is not executed. As described above, the charge discharging operation by the accumulated charge discharging circuit 20 is more likely to occur as the signal charge overflowing from each pixel circuit 10 increases, that is, the incident light to the corresponding pixel group 2 increases. That is, the accumulated charge discharging circuit 20 operates so as to discharge a signal charge of an amount corresponding to the amount of light incident on the pixel group from the node N1 in each pixel circuit 10 in the same pixel group.

  In the pixel circuit 10, the transfer gate 12 is turned on in the saturation region or the linear region in accordance with the transfer control signal TG, thereby transferring the signal charge accumulated in the node N1 during one frame period to the node Nf. The node Nf is precharged to the power supply potential VDD when the reset switch 14 is turned on, and then receives and accumulates the signal charge transferred by the transfer gate 12 in a state where the reset switch 14 is turned off. The transfer gate 12 is turned on corresponding to the output timing provided corresponding to the switching of one frame period.

  As a result, a potential corresponding to the amount of signal charge accumulated in the node N1 is generated at the output timing in one frame period at the node Nf as the floating diffusion. The voltage amplifier 16 generates an output voltage corresponding to the potential of the node Nf, and is connected to the output node No via the pixel selection switch 18 that is turned on according to the pixel selection control signal PS. As a result, an output voltage signal Vout corresponding to the signal charge amount accumulated in the node N1 during the one frame period is output to the output node No.

  As a feature of the present invention, by appropriately providing an OFF period (hereinafter also referred to as a charge discharging period) of the control switch 24 in one frame period, incident light is strong and the signal charge of the node N1 is in the middle of one frame period. In such a case, the signal charge once accumulated in the node N1 can be discharged in the middle of one frame period by the signal charge discharging operation by the stored charge discharging circuit 20.

  Next, the operation in one frame period of the semiconductor imaging device according to the first embodiment will be described with reference to FIGS.

  Referring to FIG. 7, pixel selection control signal PS, reset control signal RF, transfer control signal TG, and control signal RO are changed from a high level (H level) to a low level (L level) at a predetermined timing within each frame period. Or a transition from the L level to the H level occurs.

  The transfer gate 12, the reset switch 14, the pixel selection switch 18 and the control switch 24 are turned on during the H level period of the corresponding transfer control signal TG, reset control signal RF, pixel selection control signal PS and control signal RO, and L Off during the level period.

  Corresponding to the switching of the frame period, the pixel selection control signal PS is set to the H level for a predetermined period. In the H level period (pixel selection period) of the pixel selection control signal PS, first, after the reset control signal RF is set to H level and the signal charge of the node Nf is cleared, the H level period (transfer) of the transfer control signal TG is transferred. Period). In this transfer period, the accumulated signal charge of the node N1 in the one frame period is transferred to the node Nf, and the voltage amplifier 16 generates an output voltage signal Vout corresponding to the accumulated signal charge amount of the node N1 at this timing.

  Further, within one frame period, an L level period (charge discharge period) of the control signal RO is provided at a predetermined timing prior to the pixel selection period. As described above, in the charge discharging period, the charge discharging operation by the accumulated charge discharging circuit 20 is executed according to the amount of light incident on the pixel group.

  FIG. 8 schematically shows the formation of the potential barrier and the movement of the signal charge at times t0 to t6 in FIG.

  In FIG. 8, the vertical axis indicates the height of the potential barrier. On the horizontal axis, W1 corresponds to the arrangement region of the overflow drain capacitance 22 (node N2), W2 corresponds to the channel region of the charge discharge gate DG (n-MOS transistor 160), and W3 corresponds to the arrangement region of the photodiode PD. Correspondingly, W4 corresponds to the channel region of the transfer gate 12 (n-MOS transistor 170), and W5 corresponds to the floating diffusion region (node Nf).

  At time t0, the pixel selection control signal PS, the reset control signal RF, and the transfer control signal TG are set to L level, and the control signal RO is set to H level. For this reason, in FIG. 1, in the accumulated charge discharging circuit 20, the node N2 functions as an overflow drain when the control switch 24 is turned on. On the other hand, in the pixel circuit 10, the transfer gate 12 and the reset switch 14 are turned off, and at the node N1, signal charges are accumulated by the photocurrent generated by the photodiode PD in accordance with the amount of light incident on the pixel circuit 10. . Since the photodiode PD constantly generates a photocurrent according to the amount of light incident on the pixel circuit 10, the signal charge accumulation operation at the node N1 is also continuously performed over one frame period.

  Referring to FIG. 8A, at time t0, the region W1 corresponding to the node N2 (overflow drain capacitance 22) is biased to the power supply potential VDD. Therefore, the signal charge 70 overflowing from the photodiode region W3 due to saturation is discharged without being accumulated in the overflow drain capacitance 22 (region W1). At this time, the potential of the region W2, that is, the region under the charge discharge gate, is based on a built-in voltage that forms the bottom of the potential well of the photodiode PD so that all signal charges are not extracted from the photodiode PD (region W3). Also needs to be set low. This is equivalent to appropriately designing the electrical resistance Rh when the control switch 24 is on (Vg = Vl) for the charge discharge gate DG as the variable resistance element described above.

  Referring to FIG. 7 again, the control switch 24 is turned off in the accumulated charge discharging circuit 20 at the time t1 to t2 of the charge discharging period Tdr when the control signal RO transitions from the H level to the L level from the state at the time t0. . Therefore, the leakage signal charge from the node N1 of each pixel circuit 10 is accumulated in the node N2 by the overflow drain capacitance 22.

  Referring to FIG. 8B, at time t1, region W1 (node N2) is disconnected from power supply potential VDD, and accumulation of inflow charges from photodiode region W3 (node N1) is started.

Referring to FIG. 8C, at time t2, as the signal charge flowing from photodiode region W3 (node N1) is accumulated in overflow drain capacitance portion W1 (node N2), the region below the charge discharge gate W2 potential increases. As a result, the resistance of the charge discharging gate DG is equivalent to a decrease, and the signal charge discharging operation from the node N1 in each pixel circuit 10 is promoted. Here, a potential barrier that alienates the charge discharging to the photodiode PD. If there is no pocket and the maximum potential of the charge discharge gate lower region W2 does not exceed the built-in voltage of the photodiode, the signal charge is transferred from the photodiode region W3 to the region W1 (node N2) as follows. It can be modeled by the subthreshold current equation of the n-MOS transistor 160 shown in the equation (1).

Ids = Id0 · exp {q / (n · k · T) · (Vg−Vs−Vt)} (1)
However, in the formula (1), Id0 is represented by the following formula (2).

Id0 = (W / L) · μn · C0 · (k · T / q) · exp (1) (2)
In equations (1) and (2), q is an elementary charge, k is a Boltzmann coefficient, T is an absolute temperature, μn is a carrier mobility (electron), and W and L are the n-MOS transistor 160 Indicates gate width and gate length. Vs represents the photodiode potential (the potential of the node N1), and Vt represents the threshold voltage of the n-MOS transistor 160. Note that n is a coefficient represented by n = (C0 + Cd) / C0 using the gate insulating film capacitance C0 and the depletion layer capacitance Cd of the n-MOS transistor 160.

  As described above, the subthreshold current Ids generated in the n-MOS transistor 160 during the charge discharging period, that is, the amount of signal charge discharged from the node N1 to the node N2 per unit time depends on the amount of incident light to the pixel group. According to the potential of the node N2, the output potential Vg of the inverting amplifier 26 is set.

  Here, when the saturation signal charge amount at the photodiode PD (node N1) is Q, the potential at each point when the signal charge amount Q is accumulated at the node N1 is obtained from a circuit constant such as a capacitance value. In addition, the time required for discharging all of the saturation signal charge amount Q from the node N1 by the stored charge discharging circuit 20 can be predicted in advance in correspondence with the estimated value of the subthreshold current Ids at this time. Therefore, the length of the charge discharge period can be set in correspondence with the predicted time. Note that since the charge discharging period can be provided by setting the control signal RO, the charge discharging period may be provided not only once but also a plurality of times within one frame period.

  Referring to FIG. 7 again, when control signal RO transitions from the L level to the H level between times t2 and t3, control switch 24 is turned on again, and the state at time t0 is reproduced. As a result, at the node N1, the signal charge accumulation operation corresponding to the amount of light incident on the pixel circuit 10 is resumed.

  Referring to FIG. 8D, when the incident light is strong at time t3 at which the signal charge accumulation operation is resumed, that is, at the end of the charge discharge period Tdr, as illustrated, in the charge discharge period Tdr. By the signal charge discharging operation of the accumulated charge discharging circuit 20, the signal charge in the photodiode region W3 (node N1) is once cleared. On the other hand, although illustration is omitted, when the incident light to the pixel group is weak, the signal charge discharging operation by the stored charge discharging circuit 20 is not executed, and the photodiode region W3 (node N1) has been stored so far. The signal charge is left as it is. In the intermediate incident light region, part of the signal charges accumulated so far remains at the node N1. Thus, in the charge discharging period Tdr, the accumulated charge discharging circuit 20 discharges an amount of signal charge corresponding to the amount of light incident on the pixel group from the photodiode region W3 (node N1).

  Referring to FIG. 7 again, in the pixel selection period in which pixel selection control signal PS is set to H level, first, reset control signal RF is set to H level for a predetermined period, so that reset switch 14 is turned on. Node Nf as a floating diffusion is connected to power supply potential VDD (time t4).

  Further, in the transfer period in which the transfer control signal TG is set to the H level, the transfer gate 12 is turned on, and the signal charge accumulated in the node N1 up to that point is transferred to the node Nf (time t5). Thereafter, the transfer control signal TG returns to the L level and the transfer period ends, whereby the transfer gate 12 is turned off (time t6). Furthermore, when the pixel selection control signal PS returns to the L level and the pixel selection period ends, the operation for one frame period ends.

  Referring to FIG. 8E, at time t4, the signal charge accumulated in the node N1 after the charge discharging period Tdr is held in the photodiode region W3 (node N1). On the other hand, floating diffusion region W5 (node Nf) is connected to power supply potential VDD, and signal charges accumulated in this region are cleared.

  Referring to FIG. 8F, at time t5, by turning on the transfer gate 12, the potential of the lower transfer gate region W4 increases, and the photodiode region W3 (node N1) in the one frame period. The signal charges accumulated so far are transferred to the floating diffusion region W5 (node Nf).

  When the incident light is strong and the signal charge discharging operation is completely performed during the charge discharging period Tdr, the signal charge transferred is the signal stored in the re-accumulation period Tag (FIG. 7) after the charge discharging period Tdr. When the amount of charge is low, the incident light is weak, and the signal charge discharging operation is not executed during the charge discharging period Tdr, the signal charge is accumulated in one frame period.

  Referring to FIG. 8G, at time t6, transfer gate 12 is turned off and the potential of transfer gate lower region W4 decreases, so that the signal charge transferred from photodiode region W3 (node N1). Are accumulated in the floating diffusion region W5 (node Nf). As a result, the floating diffusion region W5 (node Nf) has a potential corresponding to the accumulated signal charge amount at this time, that is, the accumulated signal charge amount of the node N1 at the end of one frame period, and the potential of the node Nf at this time The output voltage signal Vout corresponding to the output is output from the output node No. At time t6, the accumulated signal charge in the photodiode region W3 (node N1) is once cleared in response to switching of one frame period.

  As described above, in the semiconductor image pickup device according to the first embodiment, when the incident light to the pixel group is strong (at high illuminance) by the accumulated charge discharging circuit provided for each pixel group, each pixel circuit It is possible to discharge the signal charges accumulated in the frame once at an intermediate timing (charge discharge period) of one frame period. Therefore, at the time of high illuminance, the ratio of one frame period Tfr to the re-accumulation period Tag from the end of the charge discharge period (the last charge discharge period when provided multiple times) to the end of the transfer period is k = ( According to (Tfr / Tag), the dynamic range in each pixel circuit 10 can be expanded.

  On the other hand, when the incident light to the pixel group is weak (low illuminance), the signal charge discharging operation by the accumulated charge discharging circuit 20 is not executed, and the contrast is increased without expanding the dynamic range in each pixel circuit 10. Secured imaging can be performed.

  As a result, a simple light receiving detection element (photodiode) arranged in each pixel circuit 10 and a simple circuit configuration that detects the received light amount based only on the accumulated amount of signal charge generated by the received light detection element. By expanding the dynamic range at high illuminance, it is possible to detect sufficient contrast between the bright part and the dark part even when the luminance distribution in the field of view is large.

  Here, in the pixel circuit 10, the photodiode PD corresponds to the “first light receiving detection element” in the present invention, and the node N1 corresponds to the “first node” in the present invention. The transfer gate 12 corresponds to a “first initialization circuit” that clears the stored charge of the node N1, and the reset switch 14 corresponds to a “second initialization circuit” in the present invention. Further, the voltage amplifier 16 corresponds to a “read circuit” in the present invention. The “read circuit” may be arranged as an external element of the pixel circuit 10 so as to be shared among the plurality of pixel circuits 10, for example.

  Further, in the accumulated charge discharging circuit 20, the overflow drain capacitance 22 corresponds to the “capacitance portion” in the present invention, each charge discharge gate DG corresponds to the “variable resistance element” in the present invention, and the inverting amplifier 26 is Corresponding to the “control unit” in the present invention, the control switch 24 corresponds to the “control switch element” in the present invention.

  Further, in FIG. 3, an n− diffusion region 130 corresponds to a “first impurity diffusion region” in the present invention, and an n + diffusion region 110 corresponds to a “second impurity diffusion region” in the present invention. , N + diffusion region 120 corresponds to the “third impurity diffusion region” in the present invention. The n-MOS transistor 160 corresponds to the “first field effect transistor” in the present invention, and the n-MOS transistor 170 corresponds to the “second field effect transistor” in the present invention.

  FIG. 9 is a block diagram showing the overall configuration of the semiconductor imaging device according to the first embodiment configured by arranging the pixel circuit and the accumulated charge discharging circuit according to the first embodiment in a matrix.

  Referring to FIG. 9, a semiconductor imaging device 200 according to the embodiment includes a plurality of pixel circuits 10 arranged in a matrix on a light receiving surface that receives incident light, and four pixels adjacent to each other in the row direction and the column direction. The accumulated charge discharging circuit 20 arranged for each pixel group constituted by the circuit 10, the control signal generating circuit 210, the voltage latch circuit 220, the signal line 230 arranged extending in the row direction, and the column direction And a data line 240 arranged so as to extend.

  Based on the output of a vertical shift register (not shown) that performs scanning in the vertical direction (column direction) in correspondence with one frame period, the control signal generation circuit 210 has the pixel selection control signal PS, A control signal group including a reset control signal RF, a transfer control signal TG, and a control signal RO is generated for each pixel row.

  A control signal group generated by the control signal generation circuit 210 is transmitted through the signal line 230 and taken into each pixel circuit 10 and each accumulated charge discharging circuit 20 in the same pixel row.

  The data line 240 is provided for each pixel column, and is connected to the output node No of each pixel circuit 10 in the corresponding pixel column. The voltage latch circuit 220 is connected to each data line 240 and sequentially reads the voltage on the data line 240 based on the output of a horizontal shift register (not shown) that performs horizontal (row) scanning. The output voltage signal Vout from each pixel circuit 10 can be obtained in order according to the scanning order of the pixel circuit 10. Thereby, the data string signal Vdat in which the output voltage signal Vout from each pixel circuit 10 is serially arranged can be obtained according to the scanning order of the pixel circuit 10.

  In the case where pixel circuits belonging to the same pixel group extend over a plurality of (two) pixel rows as in the present embodiment, in the plurality of (two) pixel rows corresponding to the same pixel group, It is preferable to set the control signal group at a common timing. In this case, in each pixel column, since the output voltage signal Vout is output from a plurality (two) of pixel circuits 10 belonging to the same pixel group, a plurality (two) of data lines 240 are also provided for each pixel column. ) And a plurality of (two) pixel circuits 10 belonging to the same pixel group must be connected to a plurality (two) of data lines 240 respectively. This makes it possible to execute a reading operation with higher accuracy.

  In the embodiment of the present invention, the configuration for scanning each pixel circuit 10 and taking out the output voltage signal is not limited to the example shown in FIG. 9, and any method known to those skilled in the art is appropriately used. The points that can be used are described in a confirming manner. Also, a pixel group sharing the accumulated charge discharging circuit 20 can be configured over an arbitrary number of pixel rows and pixel columns.

(Modification of Embodiment 1)
In the first embodiment, the semiconductor imaging device including the pixel circuit 10 that constitutes the photodiode PD by the embedded diode is illustrated. However, the present invention can also be applied to a pixel circuit constituted by a photodiode other than a buried diode.

  As shown in FIG. 10, even if the pixel circuit 10 in FIG. 1 is replaced with a pixel circuit 11, the accumulated charge discharging circuit 20 is shared by a plurality of pixel circuits 11 in the same pixel group. 1 can be configured.

  Referring to FIG. 10, pixel circuit 11 is different from pixel circuit 10 shown in FIG. 1 in that the arrangement of transfer gate 12 is omitted. That is, the reset switch 14 is connected to directly reset the node N1, and the input node of the voltage amplifier 16 is directly connected to the node N1.

  Therefore, in the pixel circuit 11, in the structure shown in FIG. 6, the photodiode PD can be configured as a normal pn junction diode without being limited to the buried diode. In this case, since the n-type diffusion region corresponding to node N1 is provided on the main surface of p-type silicon substrate 100, it is possible to form a contact that makes direct physical contact with node N1. Become. Therefore, even if the arrangement of the transfer gate 12 in FIG. 1 (the n-MOS transistor 170 in FIG. 6) is omitted in each pixel circuit 11, a semiconductor image sensor similar to that in the first embodiment can be configured. .

  In other words, in the pixel circuit 11, the reset switch 14 corresponds to the “first initialization circuit” in the present invention, and the “second initialization circuit” in the present invention is not arranged.

  Next, the operation in one frame period in the semiconductor imaging device according to the modification of the first embodiment to which the pixel circuit 11 is applied will be described with reference to FIG.

  Referring to FIG. 11, in the semiconductor imaging device according to the modification of the first embodiment, control signal RO is set in the same manner as in the first embodiment (FIG. 7), while pixel selection control signal PS is Is set to the H level at a timing corresponding to time t5. Then, in response to the end of the pixel selection period (the H level period of the pixel selection control signal RS), the reset control signal RF is at the H level at the start of a new one frame period so as to correspond to the switching of one frame period. Set to Thereby, the accumulated signal charge of the node N1 can be cleared at the start of each frame period.

  During one frame period, the potential of the node N1 and the output voltage of the voltage amplifier 16 change from moment to moment according to the amount of signal charge accumulated at the node N1, but the L level of the control signal RO during the one frame period. An output voltage signal Vout similar to that of the pixel circuit 10 in the first embodiment is generated by the pixel circuit 11 by appropriately executing the signal charge discharging operation by the accumulated charge discharging circuit 20 by providing a period (charge discharging period). be able to.

(Embodiment 2)
FIG. 12 is a circuit diagram illustrating the configuration of the pixel circuit and the accumulated charge discharging circuit in the semiconductor imaging device according to the second embodiment.

  Referring to FIG. 12, in the semiconductor imaging device according to the second embodiment, an accumulated charge discharging circuit 21 is provided instead of accumulated charge discharging circuit 20 shown in FIG.

  The accumulated charge discharging circuit 21 has a circuit configuration in which the photodiode PD # as the “second light receiving detection element” is arranged between the node N2 and the ground node 6 in the accumulated charge discharging circuit 20 shown in FIG. Have.

  13 is a cross-sectional view showing the structure of the main part of the stored charge discharging circuit 21 corresponding to the cross-sectional view of the main part of the stored charge discharging circuit 21 shown in FIG. As understood from the comparison between FIG. 13 and FIG. 3, the accumulated charge discharging circuit 21 has a structure in which the arrangement of the light shielding plate 115 provided on the main surface side of the n + diffusion region 110 acting as an overflow drain is omitted. As a result, a photodiode PD # having the p-type silicon substrate 100 biased to the ground potential VSS as an anode and the n + diffusion region 110 as a cathode is formed. Since the configuration and structure of other parts of the stored charge discharging circuit 21 are the same as those of the stored charge discharging circuit 20, detailed description thereof will not be repeated.

  The accumulated charge discharging circuit 21 is provided for each pixel group as in the first embodiment, and is electrically connected to each node N1 of the pixel circuit 10 included in the same pixel group via the charge discharging gate DG.

  Referring to FIG. 12 again, in the accumulated charge discharging circuit 21, during the ON period of the control switch 24, the n + diffusion region 110 is biased to the power supply potential VDD, so that the accumulated charge discharging circuit according to the first embodiment. Like 20, it acts as an overflow drain. On the other hand, during the OFF period (charge discharge period) of the control switch 24, the photodiode PD # generates a light current incident on the accumulated charge discharge circuit 21, that is, a photocurrent corresponding to the amount of light incident on the pixel group. As the current is generated, the signal charge can be stored in the node N2.

  At this time, similarly to the layout illustrated in FIG. 2, the node N2 (that is, the photodiode PD #) is arranged so as to be substantially equidistant from each pixel circuit in the region surrounded by the pixel circuits belonging to the same pixel group. ), A photocurrent corresponding to the average amount of incident light in the pixel group can be generated by the photodiode PD # by direct exposure.

  As a result, in the accumulated charge discharging circuit 21, in the charge discharging period, in addition to the signal charge overflowing from each pixel circuit 10 in the charge discharging period, the signal charge generated by the photodiode PD # is also supplied to the node N2. Accumulated. For this reason, in the accumulated charge discharging circuit 21, signal charges are likely to be accumulated in the node N2, the signal charge discharging operation from the node N1 can easily occur, and the signal charge discharging speed can be increased.

  As a result, since one frame period necessary for obtaining the same dynamic range at high illuminance is relatively shortened, higher-speed imaging can be performed.

  Alternatively, in principle, it is possible to control the potential of the node N2, that is, the resistance of the charge discharge gate DG, only in accordance with the amount of received light detected by the photodiode PD # during the charge discharge period. In such a configuration, in the accumulated charge discharging circuit 21, each charge discharging gate DG is provided by separately providing a charge discharging unit (not shown) for discharging the signal charge from the node N1 of each pixel circuit 10. It may be disconnected from the node N2 and connected between the charge discharge port and the node N1 in each pixel circuit 10.

  In the semiconductor imaging device according to the second embodiment, the pixel circuit 10 can also be replaced with the pixel circuit 11 shown in the modification of the first embodiment. That is, the semiconductor imaging element according to the second embodiment can be configured by arranging the pixel circuit 10 or 11 and the accumulated charge discharging circuit 21 according to the second embodiment as shown in FIG. 9, for example.

(Embodiment 3)
As described above, the combination of the pixel circuit 10 or 11 and the accumulated charge discharging circuit 20 or 21 can constitute the semiconductor imaging device according to the embodiment of the present invention. Here, in the first and second embodiments, the circuit configuration in which the anode of the photodiode PD is fixed to the ground potential VSS is exemplified. However, the polarity in each circuit is inverted, and the cathode of the photodiode PD is set to the power supply potential VDD. A fixed circuit configuration is also possible.

  14 and 15 show pixel circuits 10 # and 11 # according to the third embodiment, which are modified examples in which the polarities of the pixel circuits 10 and 11 are inverted, respectively.

  In pixel circuits 10 # and 11 #, the cathode of photodiode PD is connected to power supply potential node 5. Compared to pixel circuits 10 and 11, each of node N1, power supply potential node 5, and ground node 6 is provided. The arrangement of circuit elements connected to each other is interchanged. In pixel circuits 10 # and 11 #, since node N1 corresponds to the anode of the photodiode, the accumulated signal charge is a positive charge.

  FIGS. 16 and 17 show accumulated charge discharging circuits 20 # and 21 # according to the third embodiment which is a modified example in which the polarities of accumulated charge discharging circuits 20 and 21 are inverted. In accumulated charge discharging circuits 20 # and 21 #, the arrangement of circuit elements connected between node N1, power supply potential node 5 and ground node 6 is switched as compared with accumulated charge discharging circuits 20 and 21. .

  Further, between the node N1 in each pixel circuit 10 # (or 11 #) and the node N2 in the accumulated charge discharging circuit 20 # (or 21 #), from the node N1 instead of the charge discharging gate DG. A charge discharge gate DG # for discharging positive charges is connected. Contrary to charge discharge gate DG, charge discharge gate DG # decreases in electrical resistance and increases in output potential Vg as output potential Vg of inverting amplifier 26 decreases (that is, the potential of node N2 increases). The electric resistance increases as the operation proceeds.

  Pixel circuits 10 #, 11 # and accumulated charge discharging circuits 20 #, 21 # can be configured by appropriately inverting n-type and p-type conductivity types in the structural example shown in FIG. 6 or FIG. It is. That is, in the pixel circuits 10 # and 11 #, the transfer gate 12 is configured by a p-MOS transistor, and in the accumulated charge discharging circuits 20 # and 21 #, the charge discharging gate DG is formed by a p-MOS transistor.

  Since the operations and functions of pixel circuits 10 #, 11 # and accumulated charge discharging circuits 20 #, 21 # are similar to those of pixel circuits 10, 11 and accumulated charge discharging circuits 20, 21, detailed description thereof will not be repeated. That is, the semiconductor image pickup device according to the embodiment of the present invention can be configured by a combination of the pixel circuit 10 # or 11 # and the accumulated charge discharging circuit 20 # or 21 #. However, since the mobility of positive charges (holes) is smaller than the mobility of negative charges (electrons), the semiconductor imaging device constituted by the pixel circuits 10 and 11 and the accumulated charge discharging circuits 20 and 21 is a pixel circuit. Compared to a semiconductor image pickup device constituted by 10 #, 11 # and accumulated charge discharging circuits 20 #, 21 #, it is relatively advantageous in terms of high-speed imaging.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  As described above, the semiconductor image pickup device according to the present invention can be used as an image pickup device having a high visual detection capability under various circumstances, and can be used for a surveillance camera including an outdoor or a vehicle-mounted camera. Is possible. Further, since the pixel size can be reduced due to a simple circuit configuration, it is suitable for increasing the number of pixels and also suitable for mounting on a portable device.

It is a circuit diagram explaining schematic structure of the principal part of the semiconductor image pick-up element by Embodiment 1 of this invention. FIG. 2 is a plan view illustrating an arrangement example of a pixel circuit and an accumulated charge discharging circuit illustrated in FIG. 1. It is III-III sectional drawing in FIG. FIG. 2 is a circuit diagram illustrating a configuration example of an inverting amplifier illustrated in FIG. 1. It is a conceptual diagram explaining the blooming phenomenon when the incident light to a photodiode is strong. It is a conceptual diagram explaining operation | movement of an overflow drain. 4 is a timing chart for explaining an operation in one frame period in the semiconductor imaging device according to the first embodiment. FIG. 8 is a conceptual diagram illustrating the formation of a potential barrier and the movement of signal charges at each point in the timing chart illustrated in FIG. 7. 1 is a block diagram illustrating an overall configuration of a semiconductor imaging device according to a first embodiment. It is a circuit diagram explaining schematic structure of the principal part of the semiconductor imaging device by the modification of Embodiment 1 of this invention. 6 is a timing chart for explaining an operation in one frame period in a semiconductor imaging device according to a modification of the first embodiment. It is a circuit diagram explaining schematic structure of the principal part of the semiconductor image sensor by Embodiment 2 of this invention. FIG. 13 is a cross-sectional view showing a specific structure example of the accumulated charge discharging circuit shown in FIG. 12. 6 is a circuit diagram illustrating a first configuration example of a pixel circuit according to Embodiment 3. FIG. 6 is a circuit diagram illustrating a second configuration example of a pixel circuit according to Embodiment 3. FIG. 6 is a circuit diagram showing a first configuration example of an accumulated charge discharging circuit according to Embodiment 3. FIG. FIG. 10 is a circuit diagram showing a second configuration example of the accumulated charge discharging circuit according to the third embodiment.

Explanation of symbols

  2 pixel group, 3 region (pixel group), 5 power supply potential node, 6 ground node, 10, 10 #, 11, 11 # each pixel circuit, 12 transfer gate, 14 reset switch, 16 voltage amplifier, 18 pixel selection switch, 20, 20 #, 21, 21 # Accumulated charge discharging circuit, 22 overflow drain capacity, 24 control switch, 26 inverting amplifier, 27, 28 n-MOS transistor, 30 arrangement region (photodiode), 32, 35 boundary region, 34 Arrangement region (overflow drain), 36 Arrangement region (peripheral circuit), 60, 65 potential well, 70 signal charge, 100 p-type silicon substrate, 110, 120 n + diffusion region, 115 light shielding plate, 120 N diffusion region, 130 n− Diffusion region, 140,150 Insulating layer, 145,155 Gate electrode, 160, 170 n-MOS transistor (field effect transistor), 200 semiconductor imaging device, 210 control signal generation circuit, 220 voltage latch circuit, 230 signal line, 240 data line, 260 inverting amplifier, DG charge discharge gate, N1 , N2, N3, Nf node, No output node, OFD lateral overflow drain, PD photodiode, PS pixel selection control signal, RF reset control signal, RO control signal, RS pixel selection control signal, SUB substrate region, Tag re-accumulation period , Tdr charge discharge period, Tfr 1 frame period, TG transfer control signal, Vdat data string signal, VDD power supply potential, Vout output voltage signal, VSS ground potential, W1 overflow drain capacitance section, W2 charge discharge gate lower region, W Photodiode region, W4 transfer gate region underneath, W5 floating diffusion region.

Claims (3)

A semiconductor imaging device,
A plurality of pixel circuits;
At least one stored charge discharging circuit;
Each of the accumulated charge discharging circuits is arranged for each of a plurality of pixel circuits of the plurality of pixel circuits,
Each of the pixel circuits
A first light receiving detection element for generating a signal charge corresponding to the amount of light incident on the pixel circuit;
A first node having a predetermined capacity in which the signal charge generated by the first light receiving detection element is accumulated;
A first initialization circuit for clearing the signal charge accumulated in the first node in response to switching of a frame period;
Each of the accumulated charge discharging circuits is in accordance with the amount of light incident on a region where the plurality of pixel circuits corresponding to the accumulated charge discharging circuit are arranged in a predetermined charge discharging period provided in each of the frame periods. , Configured to perform a signal charge discharging operation for draining the signal charge from the first node,
The accumulated charge discharging circuit, when the amount of incident light to the plurality of pixel circuits corresponding to the accumulated charge discharging circuit is small, the signal charge discharging operation in the charge discharging period is not executed,
The accumulated charge discharging circuit includes:
A variable resistor for forming a path through which the signal charge flows out from the first node, which is electrically connected to the first node of each of the plurality of pixel circuits corresponding to the stored charge discharging circuit. Mechanism,
A controller for outputting a potential according to the amount of light incident on the region,
The electric resistance of the variable resistance mechanism is such that the amount of signal charge per unit time flowing out from the first node relatively increases as the amount of light incident on the region increases. Is controlled according to the output potential,
The semiconductor imaging device is:
For each of the pixel circuits, an electric signal corresponding to the amount of the signal charge accumulated in the first node is output at an output timing set at a predetermined timing after the charge discharging period in each frame period. A semiconductor imaging device further comprising a readout circuit configured as described above. A semiconductor imaging device,
A plurality of pixel circuits;
At least one stored charge discharging circuit;
Each of the accumulated charge discharging circuits is disposed adjacent to a plurality of pixel circuits of the plurality of pixel circuits,
Each of the pixel circuits
A first light receiving detection element for generating a signal charge corresponding to the amount of light incident on the pixel circuit;
A first node having a predetermined capacity in which the signal charge generated by the first light receiving detection element is accumulated;
Floating diffusion,
A transfer gate for transferring the signal charge stored in the first node to the floating diffusion in the ON period in the ON period of the transfer control signal that is turned on for a predetermined period according to a predetermined cycle;
Prior to an on period of the transfer control signal, including a reset switch for clearing the signal charge accumulated in the floating diffusion,
Each of the accumulated charge discharging circuits is arranged with the plurality of pixel circuits corresponding to the accumulated charge discharging circuit in a charge discharging period provided at a predetermined timing during an ON period of the transfer control signal for each predetermined period. In response to the amount of light incident on the region, the signal charge is discharged from the first node to perform a signal charge discharging operation.
The accumulated charge discharging circuit, when the amount of incident light to the plurality of pixel circuits corresponding to the accumulated charge discharging circuit is small, the signal charge discharging operation in the charge discharging period is not executed,
Each of the stored charge discharging circuits
A variable resistor for forming a path through which the signal charge flows out from the first node, which is electrically connected to the first node of each of the plurality of pixel circuits corresponding to the stored charge discharging circuit. Mechanism,
A controller for outputting a potential according to the amount of light incident on the region,
The electric resistance of the variable resistance mechanism is such that the amount of signal charge per unit time flowing out from the first node relatively increases as the amount of light incident on the region increases. Is controlled according to the output potential,
The semiconductor imaging device is:
Each pixel circuit further includes a readout circuit configured to output an electrical signal according to the amount of the signal charge transferred to the floating diffusion during an ON period of the transfer control signal according to the predetermined period. Semiconductor image sensor. Each of the stored charge discharging circuits
A second light receiving detection element for generating a signal charge corresponding to the amount of light incident on the region where the plurality of pixel circuits corresponding to the accumulated charge discharging circuit is disposed;
The generated by the second light receiving detection element signal charges are accumulated, and a second node of the predetermined capacity,
The control unit is configured to change the potential according to the potential of the second node,
The variable resistance mechanism is
Connected between the first node of each of the plurality of pixel circuits and a charge discharging unit set to a predetermined potential for attracting the signal charge, and according to the potential output by the control unit is constituted by a discharge gate for controlling the magnitude of the signal charge exhaust current flowing to the charge discharging portion from each of said first node Te,
It said control section, the higher the discharge current is large accumulation of the signal charges at the second node alters the potential to increase, semiconductor imaging device according to claim 1 or 2.

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