JP2874662B2 - Bolometer type infrared detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bolometer type infrared detector.

[0002]

2. Description of the Related Art In general, infrared detectors are widely used for crime prevention, monitoring, guidance, medical treatment, industrial measurement, and the like. FIG. 25 shows a two-dimensional bolometer-type infrared detecting device already proposed by the present applicant (see Japanese Patent Application No. 6-189144).
No., filed on August 11, 1994). In Figure 25, signal lines X _1, X _2, ─, X _m are arranged parallel to the X direction, the signal lines _{Y 1, Y 2, ─,} Y n and the source lines _{S 1, S 2, ─,} S n Are arranged parallel to the Y direction. In addition, source lines S ₁ ,
S _2, ─, S _n is grounded.

The pixel P _ij has signal lines X ₁ , X ₂ , ─, X _m and signal lines Y ₁ , Y ₂ , ─, Y _n (source lines S ₁ , S ₂ , ─, _Sn ).
Is provided at the point of intersection. For example, the pixel P ₂₂
Is composed of an N-channel MOS transistor Q and a bolometer R. In this case, the MOS transistor Q
Of the MOS transistor Q is connected to the signal line Y ₂ via the bolometer R, and further the output terminal OUT is connected via the transfer gate TG _2.
It is connected to the. The gate of the MOS transistor Q is connected to the signal line X _2.

The bolometer R is made of titanium or an alloy thereof. As a result, the 1 / f noise when the current flows through the bolometer R can be reduced, and therefore, the S / N ratio can be improved together with the sensitivity. Further, since the specific resistance of the bolometer R using titanium is small, thermal noise can be reduced. Further, since the resistance change and the thermal conductivity per unit temperature are small, the sensitivity can be improved.

Since the bolometer R is connected to the drain of the MOS transistor Q, the resistance of the bolometer R determines the current flowing through the MOS transistor Q. Therefore, 1 / f noise, which is a variation in the resistance, is hardly observed. . The bolometer R is connected to the ground terminal GND and the MOS.
When connected between the source of the transistor Q, M
When the OS transistor Q is turned on, the voltage drop caused by the bolometer R increases the source potential of the MOS transistor Q. As a result, the on-resistance of the MOS transistor Q increases, and 1 / f noise increases. .

[0006] Transfer gates TG ₁ and TG composed of a P-channel MOS transistor and an N-channel MOS transistor are provided between the signal lines Y ₁ , Y ₂ ,..., Y _n and the horizontal signal line Y _O, ie, the output terminal OUT. ₂ , ─, TG
_n is connected. In this case, the current flowing through the bolometer R depends on the required signal amount, and the voltage drop by the bolometer R depends on this signal amount. As a result,
The operating points of the transfer gates TG ₁ , TG ₂ , ─, TG _n change according to the corresponding bolometer R. However, in the P-channel MOS transistor of each transfer gate, the on-resistance is large when the source potential is small, and in the N-channel MOS transistor, the on-resistance is small when the source potential is small. Therefore, at any operating point, the on-resistance of each transfer gate is reduced, and 1 / f noise can be minimized.

The signal lines X ₁ , X ₂ ,..., And X _m are sequentially selected by the vertical register 1 and the AND circuits 2-1 2-2,. For example, when the output signal φ _V2 of the vertical shift register 1 is “1” (high level), the signal line X
The voltage of No. 2 is set to high (= V _V ). For example, V _V = 5
V. The vertical shift register 1 receives a vertical synchronization signal V _SYNC
And shifts it by receiving the horizontal synchronization signal _HSYNC .

The signal lines Y ₁ , Y ₂ ,..., Y _n are sequentially selected by the horizontal register 3 and the AND circuits 4-1 4-2,. For example, when the output signal φ _H2 of the horizontal shift register 3 is “1” (high level), the output of the AND circuit 4-2 is high (= V _H ). For example,
V _H = 5V. The horizontal shift register 3 receives the horizontal synchronizing signal H _SYNC ′ and shifts it by receiving the synchronizing clock signal SCK.

The horizontal synchronization signal H _SYNC ′ is the horizontal synchronization signal H
The those delayed by T _B horizontal blanking time _SYNC. Therefore, a delay circuit 5 having a delay time T _B is provided. That is, the signal lines X ₁ , X ₂ , ─, X _m are made of, for example, polysilicon having a relatively large resistance value, and the signal lines Y ₁ , Y ₂ , ─, Y _n and the source lines S ₁ , S ₂ , ─ S _n
Is made of, for example, aluminum or an alloy thereof having a relatively small resistance value. Also, signal lines X ₁ , X ₂ , ─, X _m
Has a large capacitance including the gate capacitance of the MOS transistor Q. Therefore, the signal lines X _1, X _2, ─, constant signal lines Y ₁ when the voltage of the X _m, Y _2, ─, greater than the time constant of the voltage of the Y _n. Therefore, in order to perform a sufficient horizontal operation after applying a pulse to the signal lines X ₁ , X ₂ , ─, and X _m , it is necessary to delay the horizontal synchronization signal H _SYNC .

The output terminal OUT is connected to the integrating circuit 6. The integrating circuit 6 includes a bipolar transistor 61 having an emitter connected to the output terminal OUT, a capacitor 62 connected to the collector of the bipolar transistor 61, and a reset transistor 6 connected to the capacitor 62.
Consists of three. Bipolar transistor 61 transfer gate TG _1, TG _2, ─, operated by the integration bias signal phi _B corresponding to each operation time of TG _n. The reset transistor 63 is operated by a signal phi _R, the integrated output signal S _OUT of the integrating circuit 6 to V _R.

In the integration circuit 6, the integration time T _S determined by the integration bias signal φ _B is equal to the transfer gate T determined by one period of the synchronous clock signal SCK.
It is smaller than the operation time of G ₁ , TG ₂ , ─, TG _n , thereby removing random noise and fixed patterns caused by variations in the operation time of transfer gates TG ₁ , TG ₂ , ─, TG _n . Note that the integration period T _S is determined by the width of the pulse output from the horizontal shift register 3, and assuming that the base voltage of the bipolar transistor 61 is constant, the MOS transistor and the AND circuit 4-1 of the horizontal shift register 3 , 4-2, .SIGMA., And 4-n cause variations in the operation of the MOS transistor Q of the pixel. As a result, the occurrence of self-heating of the bolometer varies, and random noise and fixed pattern noise are generated.

The voltage applied to one pixel constituted by the MOS transistor Q and the bolometer R is the difference voltage between the emitter of the bipolar transistor 61 and the ground terminal GND, ie, the difference voltage between the base of the bipolar transistor 61 and the ground terminal GND. The voltage is determined by subtracting the built-in voltage of the bipolar transistor. Therefore, the voltage of the integrated output signal S _OUT is separated from each pixel. As a result, when the integration period T _S increases and the noise decreases, or when the current flowing through the bolometer increases and the sensitivity increases, the amount of charge stored in the capacitor 62 increases. However, in this case, the reset voltage V _R can be set independently of the voltage applied to the pixel. Thus, the state of the bolometer R can be read.

[0013]

However [0005] In the bolometer-type infrared detection device of the above-mentioned prior application, MOS transistor source the source lines S _1, S ₂ of Q of each pixel P _ij, ─, each S _n Grounded. Therefore, when sequentially reading each pixel P _ij , each pixel P _{ij is connected} to the ground terminal.
In the current paths through the _ij to output terminal OUT, and the wiring resistance involved horizontal signal lines Y ₀ varies depending on the pixel. In the first place, since the change in the resistance of the bolometer R due to the incident infrared ray is slight, there is a problem that the above-described variation in the wiring resistance causes large variation between pixels. The signal lines Y ₁ , Y ₂ , ─, Y _n , the source lines S ₁ , S ₂ ,
─, S _n , even if the horizontal signal line Y ₀ is made of aluminum or an alloy thereof to reduce the resistance and reduce the variation in the wiring resistance, the variation in the wiring resistance remains, and it is not possible to eliminate the variation between pixels. It is enough. Therefore, the object of the present invention is to
It is an object of the present invention to provide a bolometer-type infrared detection device in which variation between pixels is reduced.

[0014]

According to the present invention, a current path flowing through each pixel is substantially diagonal in a group of a plurality of pixels.

[0015]

FIG. 1 is a circuit diagram showing a first embodiment of a bolometer type infrared detector according to the present invention. In FIG. 1, the ground terminal GND and the output terminal OUT
Are arranged diagonally to each other. This equalizes the length of the electrical path passing through any pixel _Pij between the ground terminal GND and the output terminal OUT. Further, signal lines Y ₁ , Y ₂ , ─, Y _n and source lines S ₁ , S ₂ , ─, S _n
, And the horizontal signal line Y ₀ and the horizontal source line S ₀ have the same wiring width.

In this case, the vertical lines Y ₁ , Y ₂ ,.
It is not necessary to make the wiring width of Y _n , S ₁ , S ₂ ,..., Sn _{equal to} the wiring width of horizontal lines Y ₀ , S ₀ . For example, the vertical line Y
₁ , Y ₂ , ─, and Y _n use thin wiring of several μm in order to increase the aperture ratio of the pixel (the ratio of the light receiving area to the pixel area). Since the horizontal lines Y ₀ and S ₀ have a relatively large space, the resistance is reduced by using a thick wiring of several tens μm. In this way, the resistance of the wiring passing through any pixel _Pij between the ground terminal GND and the output terminal OUT is equalized. Note that the output terminal OUT is connected to the ground terminal GND.
Does not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by a dotted line. In short, the current flowing through the pixel P _ij flows almost diagonally from the lower right to the upper left in the figure on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 2A is a detailed circuit diagram of the vertical shift register 1 of FIG. That is, the D flip-flops 1-1, 1-2,..., 1-m are connected in series. D
The flip-flop 1-1 receives the vertical synchronization signal V _SYNC , while all the D flip-flops 1-1, 1-
2, ─, 1-m are operated by the horizontal synchronization signal H _SYNC . As a result, the vertical shift register 1 sequentially generates the vertical selection signals φ _V1 , φ _V2 , ─, φ _Vm and outputs the signal lines X ₁ , X ₂ ,
M and X _m are sequentially selected and operated.

FIG. 2B is a detailed circuit diagram of the horizontal shift register 3 of FIG. That is, the D flip-flops 3-1, 3-2,..., 3-n are connected in series. D
The flip-flop 3-1 receives the horizontal synchronization signal H _SYNC ′, while all the D flip-flops 3-1 and 3-
2,..., 3-n are operated by the synchronous clock signal SCK. Thereby, the horizontal shift register 3 sequentially generates the horizontal selection signals φ _H1 , φ _H2 , ─, φ _Hn , and outputs the signal lines Y ₁ ,
Y ₂ , ─, and Y _n are sequentially selected and operated.

The operation of the bolometer type infrared detector shown in FIG. 1 will be described with reference to FIG. The vertical shift register 1 includes a vertical synchronization signal V _SYNC shown in FIG. 3A and a vertical synchronization signal V _SYNC shown in FIG.
When the horizontal synchronization signal H _SYNC shown in FIG. 3 is received, the vertical selection signals φ _V1 , φ _V2 , φ _V3 , ─, φ _Vm are changed as shown in (C), (D), (E), and (F) of FIG. Occurs sequentially. As described above, the horizontal synchronization signal H _SYNC is delayed by the delay circuit 5, and becomes the horizontal synchronization signal H _SYNC ′ shown in FIGS. FIG. 3H is a partially enlarged view of FIG. 3G.

When the horizontal shift register 3 receives the horizontal synchronization signal H _SYNC ′ shown in FIG. 3H and the synchronization clock signal SCK shown in FIG.
As shown in (K), (L) and (M), the horizontal selection signal φ
_H1 , _φH2 , _φH3 , ─, _φHn are sequentially generated.

[0021] The input to the integrator bias signal phi _B shown in (N) of FIG. 3 and input to the bipolar transistor 61, the reset transistor 63 reset signal phi _R shown in (O) in FIG. 3 after each integration period T _S I do. Thus, an integrated output signal S _OUT shown in FIG. 3 (P) is obtained.

FIG. 4 shows a modified example of the bolometer type infrared detector of FIG. In FIG. 4, the ground terminal GND and the output terminal OUT are arranged diagonally to each other on the device (chip) in a manner different from the case of FIG. Also, instead of the transfer gates TG ₁ , TG ₂ , ─, TG _n of FIG. 1, N-channel MOS transistors G ₁ , G ₂ , ─, G
_n is provided. Thus, in FIG. 4, any pixel P between the ground terminal GND and the output terminal OUT can be used.
_Equalize the resistance of the wiring passing through _ij . In FIG. 4 as well, the ground terminal GND and the output terminal OUT do not necessarily have to be diagonal, and the ground terminal GND may be arranged as shown by a dotted line. In short, the current flowing through the pixel P _ij flows almost diagonally from the upper right to the lower left in the figure on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 5 is a circuit diagram showing a second embodiment of the bolometer type infrared detector according to the present invention. In FIG. 5, an output terminal OUT ′ and an integration circuit 6 ′ connected to the output terminal OUT ′ are added to the components in FIG. Note that the integration circuit 6 'has the same configuration as the integration circuit 6. In this case, the transfer gates TG ₁ , TG ₃ ,
Ｔ, TG _n-1 are connected to the output terminal OUT via the horizontal signal line Y _0.
And transfer gates TG ₂ , TG ₄ , ─, T
G _n is connected to the 'output terminal OUT via the' horizontal signal lines Y _0. Further, the sum of the wiring widths of the horizontal signal lines Y ₀ and Y ₀ ′ is the wiring width of the horizontal lease line S ₀ . That is, the width of the horizontal source line S ₀ is equal to the width of each horizontal signal line Y ₀ , Y ₀ ′.
Is twice as large as the wiring width. As a result, the voltage drop per unit length of the horizontal signal lines Y ₀ and Y ₀ ′ is reduced by the horizontal source line S _0.
Is the same as the voltage drop per unit length. Furthermore, the horizontal shift register 3 and the transfer gate TG _1, TG ₂ of FIG 1, ─, is provided with a latch circuit 7 between the TG _n. The latch circuit 7 receives the horizontal selection signals φ _H1 , φ _H2 , ─, φ _Hn from the horizontal shift register 3 and responds to the strobe signal ST in response to the horizontal selection signals φ _H1 ′, φ _H2 ′, φ, φ.
_Hn 'occurs. In FIG. 5, two pixels can be read simultaneously, that is, the integration period is set to 2 in FIG.
Can be doubled. In this way, the resistance of the wiring passing through any pixel _Pij between the ground terminal GND and the output terminals OUT and OUT ′ is equalized.

FIG. 6 is a detailed circuit diagram of the latch circuit of FIG. That is, as shown in FIG.
-1, 7-2,..., 7-n are connected in parallel, and the respective latches 7-1, 7-2,..., 7-n are supplied with horizontal selection signals φ _H1 , φ _H2 ,. , Φ _Hn and is controlled by the strobe signal ST. Each latch 7-
1, 7-2,..., 7-n are shown in FIG. That is, when ST = "0" (low level),
Latch 7-i is in the holding state, and when ST = "1" (high level), latch 7-i is in the passing state, that is,
The horizontal selection signal φ _Hi ′ is the same as the horizontal selection signal φ _Hi .
Therefore, when the strobe signal ST switches from "1" to "0", the latch 7-i switches from the passing state to the holding state and holds the value immediately before.

First of the bolometer type infrared detectors shown in FIG.
Will be described with reference to FIG. The vertical shift register 1 is provided with a vertical synchronization signal V _SYNC shown in FIGS. 7A and 7B.
And so it operated as in the Figure 1 using the vertical synchronizing signal H _SYNC, signal φ _V1, φ _V2, ─, description of phi _Vm is omitted. As shown in FIGS. 7C and 7D, the delayed horizontal synchronization signal H _SYNC ′ has a pulse width that sufficiently covers two clocks of the synchronization clock signal SCK shown in FIG. 7E. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC ′ shown in FIG. 7D and the synchronization clock signal SCK shown in FIG.
As shown in (L) and (M), (J), (K),
The horizontal selection signals φ _H1 , φ _H2 , ─, φ _Hn having a pulse width twice as large as those in the cases (L) and (M) are generated. (E) of FIG.
As shown in (I), the frequency of the strobe signal ST is の of the frequency of the synchronous clock signal SCK. Therefore, the latch circuit 7 has the same horizontal selection signals φ _H1 ′ and φ _H2 ′ shown in (J) and (K) of FIG.
The same horizontal selection signals φ _H3 ′ and φ _H4 ′ as shown in FIG.

The integration bias signals φ _B and φ _B ′ are the same as shown in FIG.
6 '. In this case, the pulse width of the integral bias signals φ _B and φ _B ′ shown in FIG. 7 (N) is twice the pulse width of the integral bias signal φ _B shown in FIG. 3 (N). Further, the same reset signals φ _R and φ _R ′ shown in FIG.
It is supplied to the integrating circuit 6, 6 'after each integration period 2T _S. In this way, integrated output signals S _OUT and S _OUT ^′ shown in FIGS. 7 (P) and (Q) can be obtained.

The second example of the bolometer type infrared detector shown in FIG.
Will be described with reference to FIG. In the second operation, as shown in FIG. 8I, the strobe signal ST is always "1" (high level). Therefore, the latch circuit 7 is in the passing state, and as a result, as shown in FIG.
As shown in (G), (H), (J), (K), and (L), φ _Hn ′ is the same as the horizontal selection signals φ _H1 , φ _H2 , ─, φ _Hn . Further, (M), (N), (P), (Q) in FIG.
As shown in the figure, the integration bias signal φ _B ′ for the integration circuit 6 ′
The reset pulse φ _R ′ is shifted by one clock of the synchronous clock signal SCK with respect to the integration bias signal φ _B for the integration circuit 6 and the reset signal φ _R. As a result, as shown in FIGS. 8 (O) and (R), integrated output signals S _OUT and S _OUT ^′ are obtained.

In each of the first and second operations shown in FIGS. 7 and 8, the integration period (2T _S ) is set in the case of FIG. 1 (T _S ).
Can be doubled.

FIG. 9 shows a modified example of the bolometer type infrared detector of FIG. In FIG. 9, one integration circuit 6 is connected to output terminals OUT and OUT '.

The operation of the bolometer type infrared detector shown in FIG. 9 will be described with reference to FIG. Vertical shift register 1
Is a vertical synchronization signal V _SYNC shown in FIGS. 10A and 10B.
The operation is the same as that of FIG. 1 using the vertical synchronizing signal H _SYNC and the description of the signals φ _V1 , φ _V2 ,..., Φ _Vm is omitted. As shown in FIGS. 10C and 10D, the delayed horizontal synchronization signal H _SYNC ′ has a palace width that sufficiently covers one clock of the synchronization clock signal SCK shown in FIG. 10E. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC ′ shown in FIG. 10D and the synchronization clock signal SCK shown in FIG.
As shown in (G) and (H), (J), (K),
The horizontal selection signals φ _H1 , φ _H2 ,..., Φ _Hn having the same palace width in the cases (L) and (M) are generated.

Further, as shown in FIG. 10I, the strobe signal ST is always "1" (high level).
Therefore, the latch circuit 7 is in the passing state, and as a result, (F), (G), (H), (J), (K),
As shown in (L), the horizontal selection signals φ _H1 ′, φ _H2 ′,
, Φ _Hn ′ are the same as the horizontal selection signals φ _H1 , φ _{H2 ,.} Further, (M) in FIG. 10, the integration bias signal shown in (N) phi _B and the reset signal phi _R 'is supplied to the integrating circuit 6. As a result, an integrated output signal S _OUT is obtained as shown in FIG. As described above, the infrared detecting device of FIG. 9 having the latch circuit 7 operates in the same manner as the infrared detecting device of FIG. 1 having no latch circuit.

FIG. 11 shows a modified example of the bolometer type infrared detector of FIG. In FIG. 11, the ground terminal GND
The output terminal OUT and the output terminal OUT are arranged diagonally to each other on the device (chip) in a manner different from the case of FIG. Also,
The transfer gate TG _1, TG ₂ of Fig. 5, ..., TG _n
Instead of N-channel MOS transistors G ₁ , G ₂ ,
.., G _n are provided. In this way, in FIG. 11 as well, the resistance of the wiring passing through any pixel _Pij between the ground terminal GND and the output terminal OUT is equalized. FIG.
Also in 1, the ground terminal GND and the output terminal OUT are not necessarily diagonal, and the ground terminal GND may be arranged as shown by a dotted line. In short, the current flowing through the pixel P _ij flows almost diagonally from the upper right to the lower left in the figure on the device (chip), so that the wiring resistance can be equalized regardless of the pixel P _ij .

FIG. 12 is a circuit diagram showing a third embodiment of the infrared detecting apparatus according to the present invention, and shows a one-dimensional infrared detecting apparatus. In FIG. 12, the ground terminal G
Horizontal source line S ₀ connected to ND and output terminal OUT
Horizontal signal lines Y ₀ is connected to be arranged parallel to the X direction, the signal lines _{Y 1 ', Y 2',} ..., Y n ' is arranged parallel to the Y direction.

The pixel _{P j (j = 1,2, ...} , n) is the horizontal source line S ₀ and the signal lines _{Y 1 ', Y 2' ...} , are provided on the points of intersection between the Y _n '. For example, the pixel P ₂ is constituted by N-channel MOS transistor Q and the bolometer R. In this case, the source of the MOS transistor Q is connected to the ground terminal GND, and the drain of the MOS transistor Q is connected to the output terminal OUT via the bolometer R. The gate of the MOS transistor Q is connected to the signal line Y ₂ ′.

Since the bolometer R is connected to the drain of the MOS transistor Q, the resistance of the bolometer R determines the current flowing through the MOS transistor Q. Therefore, 1 / f noise, which is a variation in the resistance, is hardly observed. .

In FIG. 12, the ground terminal GND and the output terminal OUT are arranged diagonally to each other. Thereby, the equalize the length of the electrical path through any pixel P _J between the output terminal OUT and the ground terminal GND. Further, the horizontal signal line Y ₀ and the horizontal source line S ₀ have the same wiring width. Thus, to equalize the resistance of the wiring through any pixel P _J between the output terminal OUT and the ground terminal GND. Note that the ground terminal GND and the output terminal OUT need not always be diagonal, and the ground terminal GND may be arranged as shown by a dotted line. In short, the flow in substantially diagonal from the lower right of FIG on current device (chip) flowing in the pixel P _j to the upper left, thereby, it is sufficient equalizing wiring resistance regardless of the pixel P _j.

The operation of the bolometer type infrared detector shown in FIG. 12 will be described with reference to FIG. Horizontal shift register 3
FIG. 1A shows the horizontal synchronization signal H _SYNC ′ shown in FIG.
When the synchronous clock signal SCK shown in (B) of FIG. 3 is received, as shown in (C), (D), (E) and (F) of FIG. 13, the horizontal selection signals φ _H1 , φ _H2 , φ _H3,. , Φ _Hn are sequentially generated.

Further, the integral bite signal φ _B shown in FIG.
3 of a reset signal phi _R shown in (H) is input to the reset transistor 63 after each integration period T _S. This allows
An integrated output signal S _OUT shown in FIG. 13 (I) is obtained.

FIG. 14 is a circuit diagram showing a fourth embodiment of the bolometer type infrared detector according to the present invention. FIG.
4, the output terminal OUT ′ and the output terminal OU
An integrating circuit 6 'connected to T' is added to the components in FIG. Note that the integration circuit 6 'has the same configuration as the integration circuit 6. The sum of the wiring widths of the horizontal signal lines Y ₀ and Y ₀ ′ is the wiring width of the horizontal source line S ₀ .
That is, the wiring width of the horizontal source line S ₀ is twice the wiring width of each of the horizontal signal lines Y ₀ and Y ₀ ′. Thereby, the voltage drop per unit length of the horizontal signal lines Y ₀ and Y ₀ ′ is made equal to the voltage drop per unit length of the horizontal source line S ₀ .

Further, a latch circuit 7 is provided between the horizontal shift register 3 in FIG. 12 and the AND circuits 4-1, 4-2,..., 4-n. The latch circuit 7 receives horizontal selection signals φ _H1 , φ _H2 ,..., Φ _Hn from the horizontal shift register 3,
In response to the strobe signal ST, the horizontal selection signals φ _H1 ', φ
_H2 ', ..., _φHn ' are generated. In FIG. 14, two pixels can flow out simultaneously, that is, the integration period can be doubled as in the case of FIG. Thus, to equalize the resistance of the wiring through any pixel P _j between the ground terminal GND connected to an output terminal OUT, and OUT '

The first operation of the bolometer type infrared detector of FIG. 14 will be described with reference to FIG. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC shown in FIG. 15A and the synchronization clock signal SCK shown in FIG. 15B, and receives the horizontal synchronization signal _HSYNC shown in FIG. 15B and FIG. As shown in FIG. 13, the horizontal selection signals φ _H1 , φ _H2 ,..., Φ _Hn having a pulse width twice as large as those in the cases (C), (D), (E), and (F) of FIG. As shown in FIGS. 15B and 15F, the frequency of the strobe signal ST is の of the frequency of the synchronous clock signal SCK. Therefore, the latch circuit 7 outputs the same horizontal selection signals φ _H1 ′ and φ _H2 ′ as shown in FIGS. 15 (G) and (H) and the same horizontal selection signals as shown in FIGS. 15 (I) and (J). The signals φ _H3 ′, φ _H4 ′, etc. are generated.

The integration bias signals φ _B , φ _B ′,
Are the same as shown in FIG. 15 (K) and are supplied to the integration circuits 6, 6 ′. In this case, the pulse widths of the integration bias signals φ _B and φ _B ′ shown in FIG.
It is twice the pulse width of the integration bias signal phi _B shown in the (G). Further, the same reset signal phi _R shown in (L) of FIG. 15, phi _R 'is an integration circuit 6 after each integration period 2T _S,
6 '. Thus, (M) of FIG.
The integrated output signals S _OUT and S _OUT ′ shown in FIG.

The second operation of the bolometer type infrared detecting device shown in FIG. 14 will be described with reference to FIG. In the second operation, as shown in FIG. 16F, the strobe signal ST is always "1" (high level). Therefore, the latch circuit 7 is in the passing state, and as a result, (C), (D), (E), (F), (G), (H),
As shown in (I), the horizontal selection signals φ _H1 ′, φ _H2 ′,
, Φ _Hn ′ are the same as the horizontal selection signals φ _H1 , φ _{H2 ,.} Also, (J), (K), (M),
As shown in (N), the integration bias signal φ _B ′ and the reset signal φ _R ′ for the integration circuit 6 ′ are different from the integration bias signal φ _B and the reset signal φ _R for the integration circuit 6 with respect to the synchronous clock signal SCK. It is shifted by one clock. As a result, integrated output signals S _OUT and S _OUT ′ are obtained as shown in (L) and (O) of FIG.

In each of the first and second operations shown in FIGS. 15 and 16, the integration period (2T _S ) can be doubled as compared with the case of FIG. 12 (T _S ).

FIG. 17 shows a modification of the bolometer type infrared detector of FIG. In FIG. 17, one integration circuit 6 is connected to output terminals OUT and OUT ′.

The operation of the bolometer type infrared detector shown in FIG. 17 will be described with reference to FIG. (A) of FIG.
As shown in (B), the delayed horizontal synchronizing signal H _SYNC has a pulse width sufficiently covering one clock of the synchronizing clock signal SCK. The horizontal shift register 3 receives the horizontal synchronization signal H _SYNC shown in FIG. 18A and the synchronization clock signal SCK shown in FIG. 18B, and receives the horizontal synchronization signal _HSYNC shown in FIG. 18B. As shown in FIG. 13, horizontal selection signals φ _H1 , φ _H2 ,..., Φ _Hn having the same palace width in the cases of (C), (D), (E), and (F) of FIG.

Further, as shown in FIG. 18F, the strobe signal ST is always "1" (high level).
Therefore, the latch circuit 7 is in the passing state, and as a result, (C), (D), (E), (F), (G),
As shown in (I), the horizontal selection signals φ _H1 ′, φ _H2 ′,
, Φ _Hn ′ are the same as the horizontal selection signals φ _H1 , φ _{H2 ,.} Further, (J) of FIG. 18, the integration bias signal shown in (K) φ _B and the reset signal phi _R 'is supplied to the integrating circuit 6. As a result, an integrated output signal S _OUT is obtained as shown in FIG. As described above, the infrared detecting device of FIG. 17 having the latch circuit 7 operates in the same manner as the infrared detecting device of FIG. 12 having no latch circuit.

FIG. 19 shows the integration circuit 6 shown in FIGS. 25, 1, 4, 5, 9, 9, 11, 12, 14, and 17.
An example of modification of 6 ′ is shown. That is, a junction FET 64 is provided in place of the bipolar transistor 61 (61 '). In this case, the junction type FET 64 operates in the same manner as the bipolar transistor 61 (61 '). Joint type FE
T64 is inferior in the mutual conductance as compared with the bipolar transistor 61 (61 '), but has an advantage that there is no shot noise. Also, it corresponds to the base resistance of a bipolar transistor. There is an advantage that the value of the resistor is small and therefore the Johnson noise is also small.

FIG. 20 is a view similar to FIG. 1, FIG. 4, FIG. 5, FIG.
FIG. 18 is a block circuit diagram illustrating an infrared processing system including the bolometer-type infrared detection device of FIG. 1, 12, 14, or 17. 1, 4, 5, 9, 11, 12,
Bolometer type infrared detector 23 of FIG. 14 or FIG.
00 is a Peltier element 23 except for the integrating circuit 6 (6 ′).
01 and keeps the infrared detector at a constant temperature. Peltier element 2301 is a central processing unit (CPU) 2
303. Further, the CPU 2303 controls the drive circuit 2304 to send control signals such as a vertical synchronization signal V _SYNC , a horizontal synchronization signal H _SYNC , a synchronization clock signal SCK, and a strobe signal ST to the infrared detection device 2300. In this case, the infrared detecting device 2300 is used in FIGS.
12, the strobe signal ST is not supplied. In addition, the infrared detection device 2300
14 and 17, the vertical synchronization signal V
_SYNC is not supplied.

Each output OUT of the infrared detector 2300,
OUT ′ is connected to the integration circuits 6, 6 ′, and each of the integration circuits 6, 6 ′ receives the integration bias signals φ _B , φ _B ′ and the reset signals φ _R , φ _R ′ from the driving circuit 2304. The output of each integration circuit 6, 6 'is connected to sample / hold circuits 2305, 2305', and each sample / hold circuit 2305, 2305 'is connected to analog / digital (A / D) converters 2306, 2306'. I have. In this case, the infrared detecting device 2300 is used in FIGS.
9, 12, and 17, the integration circuit 6 ', the sample / hold circuit 2305', and the A / D converter 2306 'do not exist.

In FIG. 20, reference numeral 2307 denotes a ROM for storing programs and constants, 2308 a RAM for storing pixel data, and 2309 a digital / analog (D / A) converter for generating NTSC signals and the like. CP
U2303, A / D converter 2306, 2306'ROM
The 2307, the RAM 2308, and the D / A converter 2309 are mutually connected by a data bus DB and an address bus AB. Note that the integration circuits 6 and 6 ′ can be built in the infrared detection device 2300. That is, the infrared detection device 2300 and the integration circuits 6 and 6 ′ can be configured by one single chip.

Next, the pixel _Pij in FIGS. 1, 4, 5, 9, and 11 will be described with reference to FIGS. 21, 22, and 23. FIG. 21 is a sectional view, FIGS. 22 and 23 are plan views, FIG. 22 mainly shows a first-floor portion for reading out signals, and FIG. 23 mainly shows a second-floor portion for converting infrared rays into electric signals. First, referring to FIGS. 22 and 23, P
^A thick silicon oxide layer 2402 is formed on a-type single crystal silicon substrate 2401 to divide each pixel. Furthermore, thereon to form a thin silicon oxide layer 2403, also to form a polysilicon layer 2404 by patterning, to form a signal line X _i. Also, the silicon substrate 24
01, the N-type impurity layers 2401S, 2401S and 24
01D is formed. These N-type impurity layers 2401S,
2401D functions as a source region and a drain region. In this case, the silicon substrate 2401 below the polysilicon layer 2404 functions as a channel region 2401C.
Thus, N-channel MOS transistor Q is the gate electrode (polysilicon layer 2404) of the pixel P _ij, is composed of a source region 2401S and the drain region 2401D. In this case, the gate electrode has a folded shape, that is, a zigzag shape.
The width of the gate electrode is increased to increase the current flowing through the transistor Q. In FIG. 21, a thick silicon oxide layer 2405 is formed on the surface, and a cavity 240
5a is formed. The cavity 2405a is formed by embedding a polysilicon layer in the silicon oxide layer 2405 and finally removing the polysilicon layer by etching. Cavity 2405
a improves the thermal insulation of the bolometer R.

Next, referring to FIGS. 21 and 23, an aluminum layer 2406 is formed by forming and patterning aluminum or its alloy. The aluminum layer 2406 includes the source lines S _j and S _{j + 1} and the signal line Y.
_{Acts j} . In this case, the source lines S _j and S _{j + 1} are connected to the source region 2401 via the contact hole CONT1.
S (FIG. 22). The aluminum layer 2406 functions as a contact to the drain region 2401D via the contact hole CONT2. 21 and 23, a titanium layer 2407, a silicon oxide layer 2408, and a titanium nitride layer 2409 that function as a bolometer R are formed. The titanium layer 2407, the silicon oxide layer 2408, and the titanium nitride layer 2409 also form an infrared absorption layer, and together with the cavity 2405a, the slit 2
410 forms a light receiving surface (diaphragm) having long legs that are thermally insulated. That is, the infrared light reflected from the titanium layer 2407 is
Is absorbed by the electromagnetic effect. In order to efficiently exert this electromagnetic effect, the heat of the silicon oxide layer 2408 is λ / (4n), where λ is the wavelength of infrared rays and n is the refractive index of the silicon oxide layer 2408. The thickness of the titanium nitride layer 2409 is several hundred Å. Further, in order to reflect infrared rays efficiently, the titanium layer 2407 has a dense folded shape.

In the pixels shown in FIGS. 21, 22, and 23, when infrared rays enter the thermally insulated diaphragm, the diaphragm is heated, and as a result, the resistance of the bolometer R (2407), that is, the resistance of the titanium layer 2407 is reduced. The resistance value changes. In this case, the bolometer R (2407)
Since the temperature of the foot part of the part hardly changes, the resistance value of that part hardly changes. Bolometer R
Has a zigzag shape as shown in FIG. 23. As a result, the bolometer R has gained a substantial length with respect to receiving infrared rays. Accordingly, the resistance value of the long and odd-shaped portion of the bolometer R is the resistance value of the foot portion of the bolometer R, the ON resistance of the MOS transistor Q, the wiring resistance between the ground terminal GND and the output terminal OUT, or a transfer gate such as TG _It becomes larger than the resistance value of _j .

FIG. 24 shows a modified example of the diaphragm shown in FIGS. 21, 22 and 23.
Are formed on a silicon substrate 2601 in the same manner as in FIGS. 21, 22 and 23. Also, the diaphragm 26
02 is made of silicon nitride or silicon oxide and has two feet 2602a, 2602
602b. In addition, titanium bolometer 260
Reference numeral 3 denotes a zigzag shape on the diaphragm 2602, and is electrically connected to the silicon substrate 2601. Therefore, also in this case, the bolometer 2603 has gained a substantial length in receiving infrared light. Therefore, the resistance value of the long zigzag shape of the bolometer 2603 is
The resistance value of the foot portion of the bolometer R, the ON resistance of the MOS transistor Q, the wiring resistance between the ground terminal GND and the output terminal OUT, or a transfer gate such as TG
_It becomes larger than the resistance value of _j .

In FIG. 5, FIG. 9, FIG. 11, FIG. 14, and FIG. 17, two output terminals OUT and OUT ′ are provided, but three or more output terminals may be provided. For example, in the case of three output terminals, signal lines Y ₁ , Y
_4, a ... to the first output terminal, the signal line Y _2, Y _5, ... the second
, And signal lines Y ₃ , Y ₆ ,... May be connected to the third output terminal. In this case, the horizontal source line S ₀
May be set to be three times the wiring width of the horizontal signal line.

[0057]

As described above, according to the present invention, the current paths flowing through the respective pixels are substantially diagonal in the group of the plurality of pixels, so that the wiring resistance of the current paths of the respective pixels can be equalized. In addition, the variation of each pixel can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a bolometer-type infrared detection device according to the present invention.

FIG. 2 is a circuit diagram of a vertical shift register and a horizontal shift register of FIG. 1;

FIG. 3 is a timing chart showing the operation of the device of FIG. 1;

FIG. 4 is a circuit diagram showing a modification of the device of FIG. 1;

FIG. 5 is a circuit diagram showing a second embodiment of the bolometer-type infrared detection device according to the present invention.

FIG. 6 is a circuit diagram of the latch circuit of FIG. 5;

FIG. 7 is a timing chart showing a first operation of the device of FIG. 5;

FIG. 8 is a timing chart showing a second operation of the device of FIG. 5;

FIG. 9 is a circuit diagram showing a modification of the device of FIG. 5;

FIG. 10 is a timing chart showing the operation of the device of FIG. 9;

FIG. 11 is a circuit diagram showing a modification of the device of FIG. 5;

FIG. 12 is a circuit diagram showing a third embodiment of the bolometer-type infrared detection device according to the present invention.

FIG. 13 is a circuit diagram showing a modification of the device of FIG.

FIG. 14 is a circuit diagram showing a fourth embodiment of the bolometer-type infrared detection device according to the present invention.

FIG. 15 is a timing chart showing a first operation of the device of FIG. 14;

FIG. 16 is a timing chart showing a second operation of the device of FIG. 14;

FIG. 17 is a circuit diagram showing a modification of the device of FIG. 14;

FIG. 18 is a timing chart showing the operation of the device of FIG.

19, FIG. 4, FIG. 5, FIG. 9, FIG. 11, FIG.
FIG. 21 is a circuit diagram showing a modified example of the integration circuits of FIGS. 14 and 20.

20, FIG. 4, FIG. 5, FIG. 9, FIG. 11, FIG.
FIG. 18 is a block circuit diagram showing an infrared processing system including the bolometer-type infrared detection device shown in FIG. 14 or 17.

FIG. 21 is a cross-sectional view illustrating an example of a pixel of the device of FIGS. 1, 4, 5, 9, and 11;

FIG. 22 is a plan view of FIG. 21.

FIG. 23 is a plan view of FIG. 21;

FIG. 24 is a sectional view showing another example of the pixel of the device of FIGS. 1, 4, 5, 9 and 11;

FIG. 25 is a circuit diagram showing a conventional bolometer-type infrared detection device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Vertical shift register 2-1, 2-2, ..., 2-m ... AND circuit 3 ... Horizontal shift register 4-1, 4-2, ..., 4-n ... AND circuit 5 ... Delay circuit 6, 6 ' ... integrating circuit 7 ... latch circuit _{X 1, X 2, ...,} X m ... signal line _{Y 1, Y 2, ...,} Y n ... signal line Y _0, Y ₀ '... horizontal signal lines S _1, S _2, ... , S _n ... source line S ₀ ... common source line P ₁₁ , P ₁₂ , ..., P _mn , P ₁ , P ₂ , ..., P ₃ ... pixel R ... bolometer GND ... ground terminal OUT, OUT '... output terminal TG _{1, TG 2, ..., TG} n ... transfer gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01J 1/02 G01J 5/02 G01J 5/48 H04N 5/33

Claims (16)

(57) [Claims] 1. A power supply terminal (GND) and a plurality of first signal lines (X) arranged in a first direction (Y).
_1, X _2, ..., and X _m), the plurality of second signal lines arranged in a second direction substantially perpendicular to the direction of said _{1 (X) (Y 1,} Y 2, ..., Y n ), And a plurality of source lines (S ₁ , S ₁ ) arranged in the second direction.
_2, ..., S and _n), the are arranged in a first direction, a horizontal source line for connecting the power supply terminal and respective source lines and (S _0), a plurality of pixels arranged in a two-dimensional (P _11, P _12, ...,
P _mn ), wherein each of the pixels has a source connected to one of the source lines, a gate connected to one of the first signal lines, and a drain (Q), and a bolometer (R) connected to one of the drains of the first MOS transistor and the second signal line. A bolometer-type infrared detector that is almost diagonal in the group. 2. A plurality of transfer gates (TG ₁ , TG ₂ ,..., TG _n ) connected to each of the second signal lines, an output terminal (OUT), and an array in the first direction. And a horizontal signal line (Y ₀ ) connecting each of the transfer gates and the output terminal, wherein a connection point between the horizontal source line and the power supply terminal is substantially equal to the output terminal on the device. Claim 1 located diagonally
The bolometer-type infrared detection device according to 1. 3. The bolometer type infrared ray according to claim 2, wherein the wiring widths of the second signal lines and the source lines are the same, and the wiring widths of the horizontal source lines and the horizontal signal lines are the same. Detection device. 4. A plurality of second MOS transistors (G ₁ , G ₂ ,..., G) provided between each of the source lines and the horizontal source line.
_n ), an output terminal (OUT), and a horizontal signal line (Y ₀ ) arranged in the first direction and connecting each of the second signal lines to the output terminal. The bolometer-type infrared detection device according to claim 1, wherein a connection point between a line and the power terminal is located substantially diagonally on the device with respect to a connection point between the horizontal signal line and the output terminal. 5. The bolometer-type infrared ray according to claim 4, wherein the wiring widths of the second signal lines and the source lines are the same, and the wiring widths of the horizontal source lines and the horizontal signal lines are the same. Detection device. 6. A plurality of transfer gate groups (TG ₁ , TG ₂ ,..., TG _n ) connected to each of the second signal lines; a plurality of output terminals (OUT); And a plurality of horizontal signal lines (Y ₀ , Y ₀ ′) that connect one of the transfer gate groups and one of the output terminals. 2. The bolometer-type infrared detection device according to claim 1, wherein a connection point is located substantially diagonally on the device with respect to each of the output terminals. 7. The wiring width of each of the second signal lines and each of the source lines is the same, and the wiring width of the horizontal source lines is n times the wiring width of each of the horizontal signal lines, where n is the width of the horizontal signal lines. The bolometer-type infrared detection device according to claim 6, wherein the number of output terminals is the number of output terminals. 8. A plurality of second MOS transistors (G ₁ , G ₂ ,..., G) provided between each of the source lines and the horizontal source line.
_n ), a plurality of output terminals (OUT, OUT ′), and a plurality of horizontal signal lines (Y ₀ ) arranged in the first direction and connecting the second group of signal lines to each of the output terminals. , Y
₀ ′), and a connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to a connection point between each of the horizontal signal lines and the output terminal. The bolometer-type infrared detection device according to 1. 9. The wiring width of each of the second signal lines and each of the source lines is the same, and the wiring width of the horizontal source lines is n times the wiring width of each of the horizontal signal lines, where n is the width of the horizontal signal lines. 9. The bolometer-type infrared detection device according to claim 8, wherein the number of output terminals is equal to the number of output terminals. 10. A power supply terminal (GND), an output terminal (OUT), a horizontal signal line (Y ₀ ) arranged in a first direction (Y) and connected to the output terminal, A plurality of signal lines (Y ₁ ′, Y ₂ ′,..., Y _n ′) arranged in a second direction (X) substantially perpendicular to the direction, and the power supply terminals arranged in the first direction. A horizontal source line (S ₀ ) to be connected, and a plurality of pixels (P ₁ , P ₂ ,..., P _n ) arranged one-dimensionally in the first direction. A first MOS transistor (Q) having a source connected to a horizontal source line, a gate connected to one of the second signal lines, and a drain; a drain of the first MOS transistor and the horizontal A bolometer (R) connected to a signal line, wherein a current path flowing through each pixel is A bolometer-type infrared detector that is substantially diagonal in a group of pixels. 11. The bolometer according to claim 10, wherein a connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to a connection point between the horizontal signal line and the output terminal. Type infrared detector. 12. The bolometer-type infrared detector according to claim 10, wherein the horizontal source line and the horizontal signal line have the same wiring width. 13. A power supply terminal (GND), a plurality of output terminals (OUT), and a plurality of horizontal signal lines (Y ₀ , Y ₀ ) arranged in a first direction (Y) and connected to each of the output terminals. ₀ ′); a plurality of signal lines (Y ₁ ′, Y ₂ ′,..., Y _n ′) arranged in a second direction (X) substantially perpendicular to the first direction; horizontal source lines for connecting the power supply terminal are arranged in a direction (S _0), said first plurality of pixels arranged in one dimension in the direction of _{(P 1, P 2, ...} , P n) and the A first MOS transistor (Q), wherein each pixel has a source connected to the horizontal source line, a gate connected to one of the second signal lines, and a drain; And a bolometer (R) connected to one of the horizontal signal lines. And has bolometer-type infrared detection device almost diagonal current path within the group of the plurality of pixels. 14. The device according to claim 13, wherein a connection point between the horizontal source line and the power supply terminal is located substantially diagonally on the device with respect to a connection point between the horizontal signal line and each of the output terminals. Bolometer type infrared detector. 15. The bolometer-type infrared detecting apparatus according to claim 13, wherein a wiring width of the horizontal source line is n times a wiring width of the horizontal signal line, where n is the number of the output terminals. 16. The output terminal is an integration circuit (6, 6 ′).
A junction FET (64) connected to the output terminal and turned on by an integration bias signal (φ _B ); and a capacitor (62) connected to the junction FET. The reset transistor (6) connected to the capacitor
The bolometer-type infrared detection device according to claim 1, 10 or 13, comprising: