JP3655232B2 - Infrared sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an infrared sensor, and more particularly to a thermal infrared sensor.
[0002]
[Prior art]
The infrared sensor is capable of measuring the temperature of a subject, and can capture images regardless of day or night. Infrared rays are characterized by being more permeable to smoke and fog than visible light, and thus have a wide range of applications as surveillance cameras and fire detection cameras in the defense field.
[0003]
Conventional quantum infrared sensors, which have been mainstream, require a cooling mechanism because they must be operated at a low temperature below room temperature. However, since such a cooling mechanism causes an increase in the number of parts, there are problems that the cost is increased and the element cannot be reduced in size.
[0004]
In recent years, therefore, development of thermal infrared sensors that do not require a cooling mechanism has been actively performed.
[0005]
The thermal infrared sensor converts an incident infrared ray having a wavelength of about 10 μm into heat by a heat-sensitive part, converts this weak temperature change into an electrical signal by thermoelectric conversion means, and reads out the electrical signal to read an infrared image. Get information.
[0006]
As one of such thermal infrared sensors, a silicon layer formed on an insulating film of an SOI (Silicon On Insulator) substrate in which an insulating film is formed on a silicon substrate and a silicon layer is formed thereon. A device formed in the (SOI) region has been reported (Tomohiro Ishikawa, et al., Proc. SPIE Vol. 3698, p. 556, 1999). This element converts a temperature change into a voltage change by passing a constant forward current through the silicon pn junction.
[0007]
Such an infrared sensor using a silicon pn junction can be manufactured using a silicon LSI manufacturing process, and thus is an element excellent in mass productivity.
[0008]
By the way, in such an infrared sensor, it is very important that the temperature of the bulk silicon substrate supporting the SOI region is uniform over the entire imaging region. This is because the temperature of the infrared detection pixel is determined by comparing the temperature increase due to heat generated by absorbing incident infrared rays with the temperature of the bulk silicon substrate.
[0009]
However, in reality, the temperature of the bulk silicon substrate rises in the periphery of the imaging region due to the heat generated in the digital circuit such as the row selection circuit, the column selection circuit, or the timing generator arranged adjacent to the imaging region. Therefore, so-called shading occurs in which the amount of temperature rise generated by infrared rays cannot be accurately compared.
[0010]
Therefore, conventionally, in order to prevent shading caused by heat generation of adjacent digital circuits, it has been performed to design a wide interval between the imaging region and the digital circuit so that heat is not transmitted.
[0011]
However, even in such a thermal infrared sensor, it is required to further reduce the chip size in the same way as a normal LSI chip, and the design for widening the interval between the imaging region and the digital circuit described above is based on the chip size. In order to reduce this, it has been regarded as a problem of going backwards.
[0012]
[Problems to be solved by the invention]
As described above, the conventional thermal infrared sensor has been designed to increase the distance between the imaging region and the digital circuit, thereby preventing heat transfer between them and preventing shading. However, to meet the demand for reducing the chip size, this method goes backwards and is problematic.
[0013]
The present invention has been made in view of the above problems, and can prevent the heat transfer and the shading without reducing the distance between the imaging region and the digital circuit, thereby reducing the chip size. An object is to provide an infrared sensor.
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a plurality of thermoelectric conversions arranged in a matrix of a plurality of rows and columns and taking out heat generated by absorbing incident infrared light and taking it out as a change in resistance value. Pixels,
A plurality of selection lines respectively connected to either one of each row or each column of the thermoelectric conversion pixels;
A plurality of signal lines respectively connected to the other of each row or each column of the thermoelectric conversion pixels;
A pixel selection circuit that is connected to each of the selection lines and selectively applies a read voltage to the thermoelectric conversion pixel for each selection line to generate an electric signal on the signal line;
A signal readout circuit that is connected to each signal line and reads an electrical signal generated in the signal line is disposed on a semiconductor substrate,
An infrared sensor, wherein a groove is provided on a surface of the semiconductor substrate between a region where the thermoelectric conversion pixels are arranged and a region where at least one of the pixel selection circuit and the signal readout circuit is arranged. I will provide a.
[0016]
In addition, a material having a higher thermal conductivity than the semiconductor substrate is provided on or on the surface of the semiconductor substrate between the region where at least one of the pixel selection circuit and the signal readout circuit is disposed and the groove. It is preferable.
[0017]
Moreover, it is preferable that the groove is provided so as to surround a region where the thermoelectric conversion pixel is disposed.
[0018]
The semiconductor substrate is preferably an SOI substrate.
[0019]
The thermoelectric conversion pixel preferably includes a pn junction formed in an SOI region of the SOI substrate, and thermoelectric conversion is performed by the pn junction.
[0020]
According to the present invention, by providing a groove between an imaging region where uniformity of substrate temperature is required and a digital circuit that is a heat generation source, it is possible to thermally separate them. This makes it possible to reduce the chip size while preventing shading.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below exemplify elements that embody the technical idea of the present invention. The structure of the elements of the present invention is not limited to the following, and various modifications are made. It is something that can be done.
[0022]
(Embodiment 1)
FIG. 1 is a diagram showing a two-dimensional matrix configuration of m rows and n columns (m × n pixels) of the infrared sensor according to Embodiment 1 of the present invention. Here, m and n are natural numbers of 2 or more.
[0023]
As shown in FIG. 1, an infrared detection pixel 1 that converts incident infrared light into an electrical signal is two-dimensionally arranged on a semiconductor substrate 2 to form an imaging region 3. The infrared detection pixel 1 rises in temperature when irradiated with infrared rays, and converts the temperature rise into an electrical signal. Here, a diode having a silicon pn junction region 115 is formed.
[0024]
In the imaging region 3, parallel row selection lines 4 (4-1, 4-2...) And vertical column signal lines 5 (5-1, 5-2...) Are provided. The row selection lines 4 (4-1, 4-2...) Are each connected to one of the pn junction regions of the infrared detection pixel 1. The column signal lines 5 (5-1, 5-2...) Are connected to the other pn junction region of the infrared detection pixel 1.
[0025]
The row selection lines 4 (4-1, 4-2...) Are connected to the row selection circuit 40 so that arbitrary infrared detection pixels 1 in the imaging region 3 can be selected, and the column signal lines 5 (5-1, 5-1). 5-2... Are connected to the column selection transistor 6 via the amplifier circuit 9, and the signal of the pixel selected by the column selection circuit 70 is output.
[0026]
As a constant current source 80 for obtaining an output voltage from the infrared detection pixel 1, load MOS transistors 8-1, 8-2,... Are connected to the column signal line 5 of each column.
[0027]
In FIG. 1, the substrate voltage: Vs is applied to the source of the load MOS transistor. However, the source voltage can be adjusted as necessary, which is more preferable.
[0028]
A power supply voltage Vd is applied to the row selection line 4 selected by the row selection circuit 40, for example, 4-1 and Vs is applied to a row selection line not selected by the row selection circuit 40. As a result, the pn junction region 115 in the infrared detection pixel 1 of the selected row selection line 4-1 becomes a forward bias, a bias current flows, and the temperature of the pn junction region 115 existing in the infrared detection pixel 1. The operating point is determined by the forward bias current, and an output voltage serving as a signal of the infrared detection pixel 1 is generated on the column signal lines 5-1 and 5-2 of each column. At this time, the pn junction region 115a of the infrared detection pixel 1 that is not selected by the selection circuit 40 is reverse-biased. In other words, the pn junction region 115 existing inside the infrared detection pixel has a pixel selection function.
[0029]
At this time, the signal voltage generated in the column signal line 5 is extremely low. Assuming that the ratio of subject temperature change: dTs and pixel temperature change: dTd is 5 × 10 ⁻³ , thermoelectric conversion sensitivity when this value and eight pn junctions of pixels are connected in series: dV / From dTd = 10 [mV / K], it can be seen that when dTs = 0.1 [K], it is only 5 [μV].
[0030]
Therefore, in order to recognize this subject temperature difference, it is necessary to reduce the noise generated in the column signal line to 5 [μV] or less. The value of this noise is as low as about 1/80 of the noise of a CMOS sensor which is a MOS type visible light image sensor.
[0031]
For this reason, a column amplifier circuit 9 is connected between the signal lines 5-1 and 5-2 and the column selection transistor circuit 60. Each signal line is connected to the gate 10g of the amplification MOS transistor 10 of the amplifier circuit 9. A storage capacitor 12 for integrating and storing the signal current amplified is connected to the drain 10d side of the MOS transistor 10. The accumulation time for integrating the signal current is determined by the row selection pulse applied to the row selection line 4 by the row selection circuit 40.
[0032]
The storage capacitor 12 is connected to a reset transistor 14 for resetting the voltage of the storage capacitor, and the reset operation is performed after the signal voltage is read by the column selection transistor 6. Terminal 24 is an output terminal.
[0033]
Here, the row selection circuit 40 and the column selection circuit 70 are so-called digital circuits, and the other circuits are analog circuits.
[0034]
1 shows a structure in which the row selection circuit 40 is arranged adjacent to only the right side of the imaging region 3. However, a row selection circuit that performs the same operation is also arranged adjacent to the left side of the imaging region 3, so-called both sides. It is also possible to drive, and the load on the row selection circuit 40 can be reduced.
[0035]
Furthermore, in order to make it possible to use this infrared sensor easily, it is also possible to obtain a sensor output simply by providing a few inputs such as a reference clock signal, start pulse, power supply voltage, and ground. In that case, a timing generator for generating various pulses for driving the digital circuit inside the chip can be arranged above the imaging region 3. Of course, this timing generator is a digital circuit.
[0036]
In the present invention, a groove is provided between the row selection circuit 40 and the imaging region 3 . Thus, by providing a groove between the row selection circuit 40 that is a heat generation source and the imaging region 3, it is possible to prevent heat from being conducted to the imaging region 3.
[0037]
Further, although the column selection circuit 70 is also a heat generation source, the amplification circuit 9 and the selection transistor circuit 60 are present between them, so that heat is hardly transmitted from the row selection circuit 40. However, it is preferable that a groove is also formed between the column selection circuit 70 and the imaging region 3. In this case, a groove may be formed between the column selection circuit 70 and the selection transistor circuit 60, between the selection transistor circuit 60 and the amplification circuit 9, and between the amplification circuit 9 and the imaging region 3.
[0038]
Next, FIG. 2 shows the structure of the infrared detection pixel 1 of the infrared sensor shown in FIG. Here, FIG. 2A is a plan view and FIG. 2B is a cross-sectional view.
[0039]
As shown in FIG. 2, the infrared detection pixel 1 includes a pn junction region 115 for thermoelectric conversion, and an infrared absorption unit 118 is formed on the hollow structure 107 formed inside the single crystal silicon semiconductor substrate 2. 120, a pn junction region 115 formed in the SOI layer 108 formed for thermoelectric conversion, wirings 117 and 121 connecting them, a buried silicon oxide film 114 formed on the lower surface of the SOI layer 108, Consists of. Here, the SOI (Silicon On Insulator) substrate is a substrate including a silicon substrate, an insulating layer such as silicon oxide formed on the silicon substrate, and a single crystal silicon layer formed on the insulating film. is there. Typically, the insulating layer is formed on a silicon substrate. By using this SOI substrate, it is possible to reduce the element capacitance, and to achieve high speed and low noise. An SOI layer is a single crystal silicon layer formed over an insulating film in an SOI substrate.
[0040]
For the sake of explanation, FIG. 2 shows a diode structure in which two pn junction regions are arranged in series. Further, a support portion 111 for supporting the infrared detection pixel 1 via the hollow bottom portion 107 and the hollow side portion 119 having a hollow structure and outputting an electric signal from the infrared detection pixel 1 is provided. The infrared detection pixel 1 is connected to the column signal line 5 and the row selection line 4 through this support portion.
[0041]
By providing the infrared detection pixel 1 and the support part 111 on the hollow structure 107, heat dissipation of the infrared detection pixel 1 becomes slow, and the temperature of the infrared detection pixel 1 is efficiently modulated by incident infrared rays. .
[0042]
Next, FIG. 3 shows a top view of the entire chip of such an infrared sensor as viewed from above.
[0043]
As shown in FIG. 3, this infrared sensor has an imaging region 3 formed on a single crystal silicon substrate 2. Row selection circuits 40 are formed at positions adjacent to the left and right of the imaging region. This drives both sides.
[0044]
A column selection circuit 70 is formed at a position adjacent to the lower side of the imaging region 3 in the figure. A timing generator 90 is formed at a position adjacent to the upper side of the imaging region 3 in the figure.
[0045]
As shown in FIG. 3, in this infrared sensor, a groove 301 for heat separation is formed on the surface of the substrate 2 between the imaging region 3 that is an analog circuit and the row selection circuit 40 that is a digital circuit arranged on both the left and right sides. Is provided.
[0046]
In the structure without a groove, the bulk silicon substrate temperature rises in the peripheral portion adjacent to the row selection circuit 40 in the imaging region 3 due to heat generated by the digital circuit 40 or the like.
[0047]
In the present embodiment, as shown in FIG. 3, by forming a heat insulating groove on the surface of the substrate 2 between the row selection circuit 40 and the imaging region 3, a bulk inside the imaging region 3 by a circuit disposed in the periphery is formed. An increase in the temperature of the silicon substrate is suppressed. For this reason, it becomes possible to measure only the heat generated by the incident infrared rays, and the shading phenomenon can be suppressed.
[0048]
FIG. 4 shows another example of this embodiment.
[0049]
In this example, in addition to providing a groove on the surface of the substrate 2 between the imaging region 3 and the row selection circuit 40 as shown in FIG. 3, between the imaging region 3 and the column selection circuit 70, and further, the imaging region 3 and the timing generator 90. A groove is provided between them. That is, the groove 302 is formed in a closed curve shape so as to completely surround the imaging region 3 which is an analog circuit region on the surface of the substrate 2.
[0050]
By doing so, not only the influence of heat generation from the row selection circuit 40 but also the influence of heat generation from the column selection circuit 70 and the timing generator 90 can be substantially completely eliminated. , Without vertical shading.
[0051]
5 and 6 specifically show the structure of the groove peripheral surface portion described above for the infrared sensor according to the first embodiment. FIG. 5A is a top view, and FIG. 5B is a cross-sectional view along the line AA ′. FIG. 6A is a top view, and FIG. 6B is an AA ′ cross-sectional view thereof.
[0052]
First, as shown in FIG. 5A, a groove 301 is formed between the imaging region 3 and the row selection circuit 40. A row selection line 4 is provided from the imaging region 3 to the row selection circuit 40. As described above, the grooves 301 are not formed in the portion of the wiring 4 but are distributed in a well shape here. This case is also expressed as a groove.
[0053]
Next, FIG. 5B shows a cross-sectional view taken along the line AA ′, which is a portion where the row selection line 4 in FIG. 5A is not provided and where the groove 301 is provided.
[0054]
As shown in FIG. 5B, the groove 301 is dug until reaching the bulk silicon substrate 2.
[0055]
This groove 301 can be formed simultaneously with the formation process of the hollow structure 107 (FIG. 2) in the infrared detection pixel 1. That is, after depositing the silicon oxide film 120 and the silicon nitride film 118 which are infrared absorption parts, the thermal separation structure 300 is also formed simultaneously with the formation of the etching hole 119 (FIG. 2) in the infrared detection pixel 1. Subsequently, by performing silicon anisotropic etching such as TMAH, the groove 301 is completed simultaneously with the formation of the hollow structure 107 (FIG. 2) of the infrared detection pixel 1.
[0056]
Here, reference numeral 150 denotes a gate wiring of a CMOS transistor, reference numeral 151 denotes a row selection circuit wiring , and reference numeral 114 denotes a buried insulating film.
[0057]
FIG. 6A is a diagram corresponding to FIG.
[0058]
FIG. 6B shows a cross-sectional view taken along the line AA ′, which is a portion where the row selection line 4 in FIG. 6A is provided.
[0059]
As shown in FIG. 6B, no trench 301 is formed under the row selection wiring 4. In this way, disconnection of the row selection wiring 4 can be prevented.
[0060]
Here, as shown in FIG. 6B, the groove 301 is not formed in the region where the row selection line 4 from the row selection circuit 40 which is a digital circuit exists, but the general pixel size is about 40 microns. On the other hand, since the width of the row selection line 4 is 1 micron or less, there is virtually no problem with respect to heat insulation.
[0061]
(Embodiment 2)
Next, Embodiment 2 of the present invention will be described.
[0062]
7 and 8 specifically show the structure of the groove peripheral surface portion described above for the infrared sensor according to the second embodiment. In this embodiment, a material having higher heat conductivity than that of the silicon substrate is embedded between the groove and the digital circuit region.
[0063]
FIG. 7A is a top view, and FIG. 7B is an AA ′ sectional view thereof. FIG. 8A is a top view, and FIG. 8B is an AA ′ sectional view thereof. Also in this embodiment, the groove 301 can be arranged as shown in FIGS.
[0064]
First, as shown in FIG. 7A, a groove 301 is formed between the imaging region 3 and the row selection circuit 40. Between the groove 301 and the row selection circuit 40, heat sinks 150 ′ and 151 ′ made of metal having higher thermal conductivity than the silicon substrate 2 are embedded. The heat sink 150 ′ can be formed at the same time as the gate wiring 150 is formed. The heat sink 151 ′ can be formed at the same time as the wiring 151 is formed . Further, the heat sinks 151 ′ and 150 ′ may be wired to the substrate surface and radiated by a metal plate or the like. Further, the heat sink 150 ′ may be wired to the surface of the substrate 2 to radiate heat. The substrate 2 is dissipated by being mounted on the package.
[0065]
A row selection line 4 is provided from the imaging region 3 to the row selection circuit 40. A heat sink 310 made of single crystal silicon is also embedded under the heat sink 150 ′. The heat sink 310 can also dissipate heat as described above. The heat sink 310 is surrounded and insulated by an insulating film 320 such as silicon oxide. Other structures are the same as those in FIG.
[0066]
FIG. 8A is a diagram corresponding to FIG.
[0067]
FIG. 8B is a cross-sectional view taken along the line AA ′, which is a portion where the row selection line 40 in FIG. 7A is provided.
[0068]
As shown in FIG. 8B, no trench 301 is formed under the row wiring 4. By doing so, disconnection of the row wiring 4 can be prevented. In this case, however, the heat sinks 151 ′ , 150 ′, and 310 are embedded even under the row selection line 4.
[0069]
In this way, it is possible not only to insulate the heat generated in the digital circuit by the groove 301 but also to prevent the occurrence of the shading phenomenon by letting it escape to the outside of the chip by the heat sinks 151 ′ , 150 ′ and 310.
[0070]
The analog circuit can be designed and driven so that the characteristics of the infrared sensor can be fully exhibited, so that high sensitivity can be achieved.
[0071]
Furthermore, in the manufacturing process, it is possible to obtain the above-described effects only by changing the mask pattern in the photolithography process, and it is possible to obtain a highly sensitive infrared sensor at a low cost without causing an increase in process cost. .
[0072]
In FIG. 1, the output signal amplifier is described as a column amplifier circuit composed of a single amplifier MOS transistor having a first input as a gate and a second input as a source. Since this amplifier circuit has a simple configuration, it is preferable for manufacturing. However, other amplifier circuits such as a differential amplifier can be used as long as they have two inputs.
[0073]
Further, the thermoelectric conversion pixels have been described using silicon pn junctions, but the present invention is not limited thereto, and can be applied to an infrared sensor device including thermoelectric conversion pixels using a bolometer such as vanadium oxide, for example. It is.
[0074]
In that case, it goes without saying that a selection transistor for pixel selection is required in each pixel.
[0075]
【The invention's effect】
According to the present invention, it is possible to provide an infrared sensor capable of preventing heat transfer and preventing shading without reducing the space between the imaging region and the digital circuit and reducing the chip size.
[Brief description of the drawings]
FIG. 1 is a top view of an infrared sensor according to Embodiment 1 of the present invention.
2A and 2B are diagrams for explaining a thermoelectric conversion pixel of an infrared sensor according to Embodiment 1 of the present invention, in which FIG. 2A is a plan view, and FIG.
FIG. 3 is a top view showing the entire chip of the infrared sensor according to the first embodiment of the present invention.
FIG. 4 is a top view showing an entire chip of another infrared sensor according to the first embodiment of the present invention.
FIGS. 5A and 5B are enlarged views for explaining the structure around the groove of the infrared sensor according to the first embodiment of the present invention, wherein FIG. 5A is a top view, and FIG. Sectional view.
FIGS. 6A and 6B are enlarged views for explaining the structure around the groove of the infrared sensor according to the first embodiment of the present invention, where FIG. 6A is a top view and FIG. Sectional view.
FIGS. 7A and 7B are enlarged views for explaining the structure around the groove of the infrared sensor according to the second embodiment of the present invention, where FIG. 7A is a top view and FIG. Sectional view.
FIGS. 8A and 8B are enlarged views for explaining the structure around the groove of the infrared sensor according to the second embodiment of the present invention, wherein FIG. 8A is a top view and FIG. 8B is taken along the line AA ′ in FIG. Sectional view.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Infrared detection pixel 2 ... Semiconductor substrate 3 ... Imaging region 4 ... Row selection line 5 ... Column signal line 6 ... Column selection transistor 8 ... Load transistor 9 ... Column amplification circuit 10 ... MOS amplification transistor 12 ... Storage capacitor 14 ... Reset transistor 22 ... Source voltage input section 40 of amplification transistor ... Row selection circuit 60 ... Column selection transistor group 70 ... Column selection circuit 80 ... Constant current circuit 90 ... Timing generator 107 ... Hollow bottom 108 ... SOI layer 111 ... Support leg 114 ... Embedded oxide film 115 ... pn junction region 118 ... infrared absorption part 119 ... hollow side part 120 ... infrared absorption part 150 ... MOS transistor gate and gate wiring 300 ... groove 301 ... groove 302 ... groove 310 ... heat sink 320 ... insulating film 151 '... Heat sink 150 '... heat sink

Claims (5)

A plurality of thermoelectric conversion pixels arranged in a matrix of a plurality of rows and columns, and thermoelectrically converting heat generated by absorbing incident infrared light and taking out as a change in resistance value;
A plurality of selection lines respectively connected to either one of each row or each column of the thermoelectric conversion pixels;
A plurality of signal lines respectively connected to the other of each row or each column of the thermoelectric conversion pixels;
A pixel selection circuit that is connected to each of the selection lines and selectively applies a read voltage to the thermoelectric conversion pixel for each selection line to generate an electric signal on the signal line;
A signal readout circuit that is connected to each signal line and reads an electrical signal generated in the signal line is disposed on a semiconductor substrate,
An infrared sensor, wherein a groove is provided on a surface of the semiconductor substrate between a region where the thermoelectric conversion pixels are arranged and a region where at least one of the pixel selection circuit and the signal readout circuit is arranged. . A material having a higher thermal conductivity than that of the semiconductor substrate is provided on or over the surface of the semiconductor substrate between the region where at least one of the pixel selection circuit and the signal readout circuit is disposed and the trench. The infrared sensor according to claim 1 . The infrared sensor according to claim 1 , wherein the groove is provided so as to surround a region where the thermoelectric conversion pixel is arranged. The infrared sensor according to claim 1, wherein the semiconductor substrate is an SOI substrate. The infrared sensor according to claim 4 , wherein the thermoelectric conversion pixel includes a pn junction formed in an SOI region of the SOI substrate, and thermoelectric conversion is performed by the pn junction.

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