JPH0575090A - Semiconductor photodetector - Google Patents
Semiconductor photodetectorInfo
- Publication number
- JPH0575090A JPH0575090A JP3236593A JP23659391A JPH0575090A JP H0575090 A JPH0575090 A JP H0575090A JP 3236593 A JP3236593 A JP 3236593A JP 23659391 A JP23659391 A JP 23659391A JP H0575090 A JPH0575090 A JP H0575090A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- transfer
- electrodes
- voltage
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000001514 detection method Methods 0.000 description 10
- 238000005036 potential barrier Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 6
- 206010047571 Visual impairment Diseases 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体光検出装置にか
かり、特に、高感度，低雑音の半導体光検出装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photodetector, and more particularly to a semiconductor photodetector with high sensitivity and low noise.
【０００２】[0002]
【従来の技術】半導体光検出装置の一例として、図５に
示すように、光検出器にフォトダイオードを用い、この
フォトダイオードからの検出出力をＦＥＴソースフォロ
アで電流増幅して出力を得るものが知られている。この
半導体光検出装置では、フォトダイオードで光検出によ
って信号電荷が生じ、この信号電荷による電圧がＦＥＴ
のゲート用電極に印加されている。ＦＥＴのゲート用電
極の入力インピーダンスが非常に高いため、信号電荷に
よる電圧が保持され、ＦＥＴのソースに接続された負荷
抵抗ＲL にこの電圧が出力される。図５の回路の等価回
路が図６に示されている。光検出によってＦＥＴのゲー
ト用電極に生じる電圧変化ΔＶは、入射した光で生じた
信号電荷量ΔＱ及びゲート用電極に接続されている全容
量Ｃ（ＦＥＴ入力容量Ｃin及びフォトダイオードＰＤの
容量ＣPDの和）を用いて、 ΔＶ＝ΔＱ／Ｃ＝ΔＱ／（Ｃin＋ＣPD） とあらわされる。このΔＶが負荷抵抗ＲL にあらわれ
る。2. Description of the Related Art As an example of a semiconductor photodetector, as shown in FIG. 5, a photodiode is used as a photodetector, and a detection output from the photodiode is current-amplified by an FET source follower to obtain an output. Are known. In this semiconductor photodetector, signal charges are generated by photodetection by the photodiode, and the voltage due to the signal charges is the FET.
Is applied to the gate electrode. Since the input impedance of the gate electrode of the FET is very high, the voltage due to the signal charge is held and this voltage is output to the load resistance R L connected to the source of the FET. An equivalent circuit of the circuit of FIG. 5 is shown in FIG. The voltage change ΔV generated in the gate electrode of the FET by the light detection is the signal charge amount ΔQ generated by the incident light and the total capacitance C (the FET input capacitance C in and the capacitance C of the photodiode PD connected to the gate electrode). The sum of PD ) is used to represent ΔV = ΔQ / C = ΔQ / (C in + C PD ). This ΔV appears in the load resistance R L.
【０００３】[0003]
【発明が解決しようとする課題】微弱な光を検出するた
めには半導体光検出装置を高感度のものにする必要があ
る。その方法の一つとして、大面積のフォトダイオード
を光検出器に用いるということが考えられている。しか
し、大面積のフォトダイオードではその容量ＣPDが大き
くなり、前述の式に示したように、光検出によってＦＥ
Ｔのゲート用電極に生じる電圧変化ΔＶが小さくなる。
これは、等価的に感度が低下することを意味し、熱雑音
（ｋＴC 雑音）などのノイズの影響を受け、ノイズ成分
が信号に混入しやすくなる。また、フォトダイオードの
検出出力用の電極に信号電荷が到達するのに時間がかか
り、応答が鈍くなり、残像現象などが生じてしまう。こ
のように、半導体の光検出器では、小型軽量という利点
はあるのだが、微弱な光を検出するのにその性質上の限
界を有していた。In order to detect weak light, it is necessary to make the semiconductor photodetector highly sensitive. As one of the methods, it is considered to use a large-area photodiode for a photodetector. However, in a large-area photodiode, its capacitance C PD becomes large, and as shown in the above equation, FE is detected by photodetection.
The voltage change ΔV generated in the gate electrode of T becomes small.
This means that the sensitivity is equivalently reduced, and is affected by noise such as thermal noise (kT C noise), and noise components are easily mixed in the signal. Further, it takes time for the signal charge to reach the detection output electrode of the photodiode, the response becomes slow, and an afterimage phenomenon occurs. As described above, the semiconductor photodetector has an advantage of being small and lightweight, but has a limit in its property for detecting weak light.
【０００４】本発明は、前述の問題点を克服し、従来よ
りも高感度，低雑音の半導体光検出装置を提供すること
をその目的とする。An object of the present invention is to overcome the above-mentioned problems and to provide a semiconductor photodetector with higher sensitivity and lower noise than ever before.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体光検出装
置は、半導体基板と、この基板の受光領域上に互いに隣
接して配置された複数の電極と、基板上に形成され、複
数の電極のうち所定の電極近傍に蓄えられた電荷の転送
を制御するトランスファーゲート用電極と、電荷と反対
極性のバイアス電圧を複数の電極に印加し、トランスフ
ァーゲート用電極より最遠の複数の電極から順次バイア
ス電圧の印加を解除し若しくは電荷と同一極性の電圧を
印加し、トランスファーゲート用電極に電荷と反対極性
の電圧を印加する制御回路とを備えたことを特徴とす
る。A semiconductor photodetector according to the present invention includes a semiconductor substrate, a plurality of electrodes arranged adjacent to each other on a light receiving region of the substrate, and a plurality of electrodes formed on the substrate. Among them, a transfer gate electrode for controlling the transfer of the charge accumulated in the vicinity of a predetermined electrode and a bias voltage having a polarity opposite to the charge are applied to the plurality of electrodes, and the electrodes farthest from the transfer gate electrode are sequentially arranged from the plurality of electrodes. And a control circuit for releasing the application of the bias voltage or applying the voltage of the same polarity as the charge and applying the voltage of the opposite polarity to the charge to the transfer gate electrode.
【０００６】また、トランスファーゲート用電極を介し
て複数の電極近傍でかつ互いに隣り合った複数の移送用
電極と、この移送用電極近傍に蓄えられた電荷の転送を
制御する出力ゲート用電極とを基板上にさらに備え、制
御回路が、さらに、出力ゲート用電極から最遠の移送用
電極から順次バイアス電圧の印加を解除し若しくは電荷
と同一極性の電圧を印加し、出力ゲート用電極に電荷と
反対極性の電圧を印加することを特徴としてもよい。Further, a plurality of transfer electrodes adjacent to each other via the transfer gate electrode and adjacent to each other, and an output gate electrode for controlling transfer of charges accumulated in the vicinity of the transfer electrode are provided. The control circuit further includes a substrate, and the control circuit further releases the application of the bias voltage from the transfer electrode farthest from the output gate electrode or applies a voltage having the same polarity as the charge, and the charge is applied to the output gate electrode. It may be characterized in that voltages of opposite polarities are applied.
【０００７】そして、出力ゲート用電極近傍にフローテ
ィングディフュージョンアンプをさらに備えたことを特
徴としてもよい。Further, a floating diffusion amplifier may be further provided near the output gate electrode.
【０００８】[0008]
【作用】本発明の半導体光検出装置では、受光領域で入
射した光によって生じた電荷は、トランスファーゲート
用電極の側の電極から最遠の受光領域上の電極から順次
バイアス電圧の印加が解除され若しくは電荷と同一極性
の電圧が印加されることで、ポテンシャル障壁がトラン
スファーゲート用電極の側の電極近傍へと順次高くな
り、電荷がひきよせられる。トランスファーゲート用電
極に電荷と反対極性の電圧が印加されると、トランスフ
ァーゲート用電極近傍のポテンシャル障壁が低くなって
電荷が通過できるようになりこれが読み出される。In the semiconductor photodetector of the present invention, the charge generated by the light incident on the light receiving region is sequentially released from the electrode on the light receiving region farthest from the electrode on the transfer gate electrode side. Alternatively, by applying a voltage having the same polarity as the charge, the potential barrier is gradually increased to the vicinity of the electrode on the transfer gate electrode side, and the charge is pulled out. When a voltage having a polarity opposite to that of the charge is applied to the transfer gate electrode, the potential barrier near the transfer gate electrode is lowered to allow the charge to pass and is read out.
【０００９】移送用電極及び出力ゲート用電極が設けら
れている場合、この電荷が、トランスファーゲート用電
極に電荷と反対極性の電圧が印加されることによって移
送用電極に転送された後、出力ゲート用電極から最遠の
移送用電極から順次バイアス電圧の印加が解除され若し
くは電荷と同一極性の電圧が印加されると、ポテンシャ
ル障壁が出力ゲート用電極の側の電極近傍へと順次高く
なり、出力ゲート用電極の側の移送用電極近傍に集めら
れる。電荷が集められることで、この電荷による電位が
上昇し、これが出力ゲート用電極に電荷と反対極性の電
圧が印加されていると、出力ゲート用電極近傍のポテン
シャル障壁が低くなって電荷が通過できるようになりこ
れが出力される。When the transfer electrode and the output gate electrode are provided, the charges are transferred to the transfer electrode by applying a voltage having a polarity opposite to that of the charges to the transfer gate electrode, and then the output gate. When the bias voltage is sequentially released from the transfer electrode farthest from the working electrode or a voltage having the same polarity as the charge is applied, the potential barrier gradually increases to the vicinity of the electrode on the output gate electrode side, and the output Collected near the transfer electrode on the side of the gate electrode. By collecting the charges, the potential due to the charges rises, and when a voltage having the opposite polarity to the charges is applied to the output gate electrode, the potential barrier near the output gate electrode becomes low and the charges can pass through. And this is output.
【００１０】フローティングディフュージョンアンプが
設けられている場合、これらの出力はその高い入力イン
ピーダンスにより、電荷が保持されて減衰の非常に少な
い出力となる。When a floating diffusion amplifier is provided, these outputs have very low attenuation due to their high input impedance, which holds electric charges.
【００１１】[0011]
【実施例】本発明の実施例を図１乃至図４を用いて説明
する。この図１に示す半導体光検出装置は、簡単のため
に大面積のフォトダイオードの光検出領域を３×３で分
割した例である。Embodiments of the present invention will be described with reference to FIGS. The semiconductor photodetector shown in FIG. 1 is an example in which the photodetection region of a large-area photodiode is divided into 3 × 3 for simplicity.
【００１２】この半導体光検出装置は、ｐ型半導体の基
板１０２に、ＭＯＳ構造にて、電極１１〜３３が配置さ
れている。受光領域１０は、電極１１〜３３のいづれか
に正電圧を加えることで、ＭＯＳキャパシタ型の光電変
換が行われる光検出領域である。電極１１〜１３，２１
〜２３，３１〜３３は、それぞれ互いに接続されて、コ
ントロール電圧φ1V，φ2V，φ3Vが与えられ、受光領域
１０の表面のポテンシャルを制御し、その電極近傍の基
板表面に電荷を蓄積しもしくは転送，放出するものであ
る。In this semiconductor photodetector, electrodes 11 to 33 having a MOS structure are arranged on a p-type semiconductor substrate 102. The light receiving region 10 is a light detection region in which a MOS capacitor type photoelectric conversion is performed by applying a positive voltage to any of the electrodes 11 to 33. Electrodes 11-13, 21
～23,31～33 are each connected to one another, the control voltage φ 1V, φ 2V, φ 3V is given, controls the potential of the surface of the light receiving area 10, accumulates a charge on the substrate surface of the electrode near Alternatively, it is transferred or released.
【００１３】電極３１〜３３近傍の受光領域１０の外側
にはトランスファーゲート用電極４１〜４３が設けら
れ、コントロール電圧φTGにより正電圧が加えられてそ
の付近のポテンシャル障壁を低くすることで、電極３１
〜３３近傍に保持された電荷を移送用電極５１〜５３に
転送するものである。移送用電極５１〜５３も、電極１
１〜３３と同様、ＭＯＳ構造を有し、コントロール電圧
φ1H，φ2H，φ3Hにより、基板表面のポテンシャル障壁
を制御して、その電極近傍の基板表面に電荷を蓄積し、
もしくは放出するものである。出力ゲート用電極６１
は、正電圧が加えられることで、移送用電極５１近傍に
保持された電荷をｎ型領域７１に転送するものである。Electrodes 41 to 43 for transfer gates are provided outside the light receiving region 10 in the vicinity of the electrodes 31 to 33, and a positive voltage is applied by the control voltage φ TG to lower the potential barrier in the vicinity thereof. 31
The charges held in the vicinity of 33 to 33 are transferred to the transfer electrodes 51 to 53. The transfer electrodes 51 to 53 are also electrodes 1
Similar to Nos. 1 to 33, it has a MOS structure and controls the potential barrier on the substrate surface by the control voltages φ 1H , φ 2H , and φ 3H to accumulate charges on the substrate surface in the vicinity of the electrodes,
Or it is released. Output gate electrode 61
Is to transfer the charges held in the vicinity of the transfer electrode 51 to the n-type region 71 by applying a positive voltage.
【００１４】ｎ型領域７１及びＦＥＴ１０１でフローテ
ィングディフュージョンアンプ１７１が構成されてお
り、ｎ型領域７１に蓄積された電荷による電圧が負荷抵
抗ＲL に出力される。ｎ型領域７１，リセットゲ−ト電
極８１，リセットドレイン９１でリセットＦＥＴが構成
され、リセットドレイン９１の出力ＲD を介して基準電
圧ライン（グランド電圧ライン）若しくは負電圧に接続
されている。このリセットＦＥＴは、コントロール電圧
φRGによりリセットゲ−ト電極８１に正電圧が加えられ
ると、オンになり、ｎ型領域７１に蓄積された電荷を放
出して、ｎ型領域７１をグランド電位にする、というフ
ローティングディフュージョンアンプ１７１をリセット
するものである。A floating diffusion amplifier 171 is composed of the n-type region 71 and the FET 101, and a voltage due to the charges accumulated in the n-type region 71 is output to the load resistance R L. A reset FET is composed of the n-type region 71, the reset gate electrode 81, and the reset drain 91, and is connected to a reference voltage line (ground voltage line) or a negative voltage via the output R D of the reset drain 91. This reset FET is turned on when a positive voltage is applied to the reset gate electrode 81 by the control voltage φ RG , releases the electric charge accumulated in the n-type region 71, and brings the n-type region 71 to the ground potential. , To reset the floating diffusion amplifier 171.
【００１５】制御回路１００は、図２のタイミングチャ
ートに示すようなコントロール電圧φ1V，φ2V，φ3V，
φTG，φ1H，φ2H，φ3H，φRGを発生し、各電極へ出力
するものである。制御回路１００は、外部に設けられた
水晶発振子若しくはセラミック発振子Ｘ１による基準ク
ロックで制御され、カウンタ及びデコーダという簡単な
構成で製作されている。The control circuit 100 controls the control voltages φ 1V , φ 2V , φ 3V , as shown in the timing chart of FIG.
It generates φ TG , φ 1H , φ 2H , φ 3H , and φ RG and outputs them to each electrode. The control circuit 100 is controlled by a reference clock provided by an externally provided crystal oscillator or ceramic oscillator X1 and is manufactured with a simple configuration of a counter and a decoder.
【００１６】つぎに、この半導体光検出装置の動作につ
いて図１のＡ−Ａ’，Ｂ−Ｂ’断面の基板１０２のポテ
ンシャル図（図３，図４）を用いて説明する。Next, the operation of this semiconductor photodetector will be described with reference to the potential diagrams (FIGS. 3 and 4) of the substrate 102 taken along the lines AA 'and BB' in FIG.
【００１７】コントロール電圧φ1Vが「Ｈ」レベルとな
っている期間が電荷蓄積期間であり、この期間において
光電変換によって生じた電荷が受光領域１０に蓄積され
る（図２の時刻ｔ0 の状態、図３（ａ），図４（ａ）参
照）。電荷蓄積期間経過後、コントロール電圧φ1V，φ
2V，φ3Vが順次「Ｌ」レベルとなり、電極１１〜１３，
２１〜２３，３１〜３３近傍のポテンシャル障壁が順次
高くなり、光電変換によって生じた電荷がトランスファ
ーゲート用電極４１〜４３の方に押しやられ、コントロ
ール電圧φTG「Ｈ」レベルとなり、移送用電極５１〜５
３とつながって電荷が集められる（図２の時刻ｔ1 〜ｔ
3 の状態、図３（ｂ）〜（ｄ），図４（ａ），（ｂ）参
照）。続いて、コントロール電圧φ3Vが「Ｌ」レベルと
なり、受光領域１０で生じた全電荷が移送用電極５１〜
５３近傍に転送される（図２の時刻ｔ4 の状態、図３
（ｅ），図４（ｃ）参照）。トランスファーゲート用電
極４１〜４３が「Ｌ」レベルとなり、電極４１〜４３近
傍のポテンシャル障壁が高くなって、受光領域１０と移
送用電極５１〜５３近傍とがきりはなされる（図２の時
刻ｔ5 の状態、図３（ｆ），図４（ｄ）参照）。The period during which the control voltage φ 1V is at the “H” level is the charge accumulation period, and the charges generated by photoelectric conversion during this period are accumulated in the light receiving region 10 (state at time t 0 in FIG. 2). , FIG. 3 (a) and FIG. 4 (a)). After the charge accumulation period, control voltage φ 1V , φ
2V and φ3V become "L" level sequentially, and the electrodes 11-13,
The potential barriers in the vicinity of 21 to 23 and 31 to 33 gradually become higher, and the charges generated by photoelectric conversion are pushed toward the transfer gate electrodes 41 to 43 to reach the control voltage φ TG “H” level, and the transfer electrode 51. ~ 5
3 and charges are collected (time t 1 to t in FIG. 2).
3 state, see FIGS. 3 (b) to 3 (d) and FIGS. 4 (a) and 4 (b)). Subsequently, the control voltage φ 3V becomes the “L” level, and all the charges generated in the light receiving region 10 are transferred to the transfer electrodes 51 to 51.
It is transferred to the vicinity of 53 (state at time t 4 in FIG. 2, FIG.
(E), refer FIG.4 (c)). The transfer gate electrodes 41 to 43 are at the “L” level, the potential barrier in the vicinity of the electrodes 41 to 43 becomes high, and the light receiving region 10 and the vicinity of the transfer electrodes 51 to 53 are cut off (time t 5 in FIG. 2). (See FIG. 3 (f) and FIG. 4 (d)).
【００１８】受光領域１０では、コントロール電圧
φ1V，φ2V，φ3Vは「Ｈ」レベルとなって電荷蓄積期間
になり、この動作が繰り返される（図２の時刻ｔ6 以降
の状態、図３（ｇ），（ｈ），（ｉ）参照）。一方、移
送用電極５３，５１へのコントロール電圧φ1H，φ2H，
φ3Hが順に「Ｌ」レベルとなり（ＯＧにはＤＣ電圧が印
加されている。）、移送用電極５１の方に電荷が集めら
れ、ｎ型領域７１に電荷が転送される。また、コントロ
ール電圧φRGが「Ｈ」レベルとなり、ｎ型領域７１の電
荷が放出されて、フローティングディフュージョンアン
プ１７１が予めリセットされている（時刻ｔ6 〜ｔ8 の
状態、図４（ｅ）（ｆ）（ｇ）参照）。コントロール電
圧φ3Hが「Ｌ」レベルとなって、全電荷がｎ型領域７１
に転送され、ｎ型領域７１が切り離される。このｎ型領
域７１の電荷による電圧がフローティングディフュージ
ョンアンプ１７１で増幅され負荷抵抗ＲL に出力される
（時刻ｔ8 の状態、図４（ｇ）参照）。次にリセットゲ
−トが「Ｈ」レベルとなり、ＦＤがリセットされるまで
この状態が保持され、この動作がくりかえされる。In the light receiving region 10, the control voltages φ 1V , φ 2V , and φ 3V are set to the “H” level to enter the charge accumulation period, and this operation is repeated (state after time t 6 in FIG. 2, FIG. 3). (G), (h), (i)). On the other hand, control voltages φ 1H , φ 2H to the transfer electrodes 53, 51,
φ 3H sequentially goes to the “L” level (DC voltage is applied to OG), the charges are collected toward the transfer electrode 51, and the charges are transferred to the n-type region 71. Further, the control voltage φ RG becomes the “H” level, the charge of the n-type region 71 is discharged, and the floating diffusion amplifier 171 is reset in advance (state from time t 6 to t 8 , FIG. f) (g)). The control voltage φ 3H becomes the “L” level, and the total charge is the n-type region 71.
And the n-type region 71 is separated. The voltage due to the charge of the n-type region 71 is amplified by the floating diffusion amplifier 171 and output to the load resistance R L (state at time t 8 , see FIG. 4G). Next, the reset gate becomes "H" level, this state is maintained until the FD is reset, and this operation is repeated.
【００１９】このように、受光領域１０で光電変換によ
って生じた電荷がｎ型領域７１に転送されて、電荷の読
み残し，残像がなくなる。電荷の転送ロスを無視する
と、前述の容量と電荷量の関係からｎ型領域７１には、
およそ受光領域１０の電位の「（受光領域１０の容量）
／（ｎ型領域７１の容量）」倍の電位が生じる。即ち、
受光領域から基板上の所定領域に電荷を転送すること
で、等価的にそれらの容量比に応じた電圧増幅がなされ
る。その領域に保持された電荷がフローティングディフ
ュージョンアンプの高い入力インピーダンスにより保持
され、この電荷による電圧が出力される。これによっ
て、高感度，低雑音の光検出がなされている。In this way, the charges generated by photoelectric conversion in the light receiving region 10 are transferred to the n-type region 71, and the charges are left unread and the afterimage disappears. Neglecting charge transfer loss, in the n-type region 71, due to the relationship between the capacitance and the charge amount,
About the potential of the light receiving area 10 "(capacity of the light receiving area 10)
/ (Capacity of the n-type region 71) times as much potential is generated. That is,
By transferring charges from the light receiving region to a predetermined region on the substrate, voltage amplification corresponding to their capacitance ratio is equivalently performed. The charges held in that region are held by the high input impedance of the floating diffusion amplifier, and the voltage due to this charges is output. As a result, high-sensitivity and low-noise optical detection is performed.
【００２０】本発明は、前述の実施例に限らず様々な変
形が可能である。The present invention is not limited to the above-mentioned embodiment, but various modifications can be made.
【００２１】電極数，電極配列，電極形状や各電極にか
けるパルス波形などについては、例えば、前述の第１実
施例において電極１１〜３３をトランスファーゲート用
電極４１〜４３から遠ざかるにつれて大きくなるように
構成しても良い。また、図１の電極１１〜３３を削除
し、転送用電極に受光領域を設けても良い。この場合
は、電圧増幅率は減少するが制御が若干簡単になる。基
板についてもその表面に低不純物のｎ層が設けられたｐ
ｎ接合を有するものを用いることができる。また、制御
回路を基板外に設けても良い。フローティングディフュ
ージョンアンプにかえてチャージアンプにしても良い。
さらに、受光領域を小さくして多数マトリクス状に配置
し、それぞれの受光領域にトランスファーゲート用電極
若しくは出力ゲート用電極を設けることによっていわゆ
る固体撮像素子を構成すると残像の少なく感度の良い固
体撮像素子になる。このように、上記の色々な組み合わ
せで様々なバリエーションが可能である。With respect to the number of electrodes, the electrode arrangement, the electrode shape, the pulse waveform applied to each electrode, and the like, for example, in the above-described first embodiment, the electrodes 11 to 33 become larger as they move away from the transfer gate electrodes 41 to 43. It may be configured. Further, the electrodes 11 to 33 in FIG. 1 may be deleted and a light receiving region may be provided in the transfer electrode. In this case, the voltage amplification factor decreases, but the control becomes slightly easier. As for the substrate, p with a low impurity n layer provided on its surface
A material having an n-junction can be used. Further, the control circuit may be provided outside the substrate. A charge amplifier may be used instead of the floating diffusion amplifier.
Further, if the so-called solid-state image sensor is configured by arranging a plurality of light-receiving areas in a matrix and providing a transfer gate electrode or an output gate electrode in each light-receiving area, a solid-state image sensor with little afterimage and high sensitivity can be obtained. Become. In this way, various variations are possible with the various combinations described above.
【００２２】[0022]
【発明の効果】以上の通り本発明によれば、トランスフ
ァーゲート用電極の側の電極から最遠の電極から順次バ
イアス電圧の印加が解除され若しくは電荷と同一極性の
電圧が印加されることで、光検出で生じる電荷を効率的
に集めることができ、読み残し，残像がなくなり、ま
た、検出出力が等価的に電圧増幅され、低雑音化され検
出感度を向上させることができる。移送用電極から順次
バイアス電圧の印加が解除され若しくは電荷と同一極性
の電圧が印加されることで、検出出力がさらに電圧増幅
され、低雑音化され検出感度が向上させることができ
る。フローティングディフュージョンアンプの増幅によ
り、減衰の非常に少ない出力となり、さらに良好な検出
出力を得ることができる。As described above, according to the present invention, the application of the bias voltage is sequentially released from the electrode farthest from the electrode on the transfer gate electrode side, or the voltage having the same polarity as the charge is applied, It is possible to efficiently collect the electric charges generated by the photodetection, to eliminate the unread portion and the afterimage, and to equivalently amplify the voltage of the detection output, reduce the noise, and improve the detection sensitivity. The application of the bias voltage is sequentially released from the transfer electrode or the voltage having the same polarity as the charge is applied, whereby the detection output is further voltage-amplified, the noise is reduced, and the detection sensitivity can be improved. Due to the amplification of the floating diffusion amplifier, an output with very little attenuation is obtained, and an even better detection output can be obtained.
【図１】第１実施例の構成図。FIG. 1 is a configuration diagram of a first embodiment.
【図２】制御回路からの制御パルスのタイミングチャー
ト。FIG. 2 is a timing chart of control pulses from a control circuit.
【図３】図２の制御パルスによる第１実施例のポテンシ
ャル図。FIG. 3 is a potential diagram of the first embodiment according to the control pulse of FIG.
【図４】図２の制御パルスによる第１実施例のポテンシ
ャル図。FIG. 4 is a potential diagram of the first embodiment according to the control pulse of FIG.
【図５】従来例の半導体光検出装置の回路図FIG. 5 is a circuit diagram of a conventional semiconductor photodetector device.
【図６】図５の等価回路を示す回路図。6 is a circuit diagram showing an equivalent circuit of FIG.
１０…受光領域 １１〜１３…電極 ２１〜２３…電極 ３１〜３３…電極 ４１〜４３…トランスファーゲート用電極 ６１…出力ゲート用電極 １００…制御回路 ５１〜５３…電極 １７１…フローティングディフュージョンアンプ 10 ... Light receiving area 11-13 ... Electrode 21-23 ... Electrode 31-33 ... Electrode 41-43 ... Transfer gate electrode 61 ... Output gate electrode 100 ... Control circuit 51-53 ... Electrode 171 ... Floating diffusion amplifier
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｎ 5/335 Ｆ 8838−5Ｃ 8422−4Ｍ Ｈ０１Ｌ 31/10 Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H04N 5/335 F 8838-5C 8422-4M H01L 31/10 A
Claims (3)
の電極と、 前記基板上に形成され、前記複数の電極のうち所定の電
極近傍に蓄えられた電荷の転送を制御するトランスファ
ーゲート用電極と、 前記電荷と反対極性のバイアス電圧を前記複数の電極に
印加し、前記トランスファーゲート用電極より最遠の前
記複数の電極から順次前記バイアス電圧の印加を解除し
若しくは前記電荷と同一極性の電圧を印加し、前記トラ
ンスファーゲート用電極に前記電荷と反対極性の電圧を
印加する制御回路とを備えたことを特徴とする半導体光
検出装置。1. A semiconductor substrate, a plurality of electrodes arranged adjacent to each other on a light receiving region of the substrate, and charges stored on the substrate and stored in the vicinity of a predetermined electrode of the plurality of electrodes. A transfer gate electrode for controlling the transfer of the transfer gate, and a bias voltage having a polarity opposite to that of the charge is applied to the plurality of electrodes, and the bias voltage is released from the plurality of electrodes farthest from the transfer gate electrode. Or a control circuit for applying a voltage having the same polarity as the charge and applying a voltage having the opposite polarity to the charge to the transfer gate electrode.
て前記複数の電極近傍でかつ互いに隣り合った複数の移
送用電極と、この移送用電極近傍に蓄えられた電荷の転
送を制御する出力ゲート用電極とを前記基板上にさらに
備え、 前記制御回路が、さらに、前記出力ゲート用電極から最
遠の前記移送用電極から順次前記バイアス電圧の印加を
解除し若しくは前記電荷と同一極性の電圧を印加し、前
記出力ゲート用電極に前記電荷と反対極性の電圧を印加
することを特徴とする請求項１記載の半導体光検出装
置。2. A plurality of transfer electrodes adjacent to each other through the transfer gate electrode and adjacent to each other, and an output gate electrode for controlling transfer of charges accumulated in the vicinity of the transfer electrode. Is further provided on the substrate, and the control circuit further sequentially releases the application of the bias voltage from the transfer electrode farthest from the output gate electrode or applies a voltage having the same polarity as the charge. 2. The semiconductor photodetector according to claim 1, wherein a voltage having a polarity opposite to that of the charge is applied to the output gate electrode.
は前記出力ゲート用電極近傍にフローティングディフュ
ージョンアンプをさらに備えたことを特徴とする請求項
１又は２記載の半導体光検出装置。3. The semiconductor photodetector according to claim 1, further comprising a floating diffusion amplifier near the transfer gate electrode or the output gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23659391A JP3167150B2 (en) | 1991-09-17 | 1991-09-17 | Semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23659391A JP3167150B2 (en) | 1991-09-17 | 1991-09-17 | Semiconductor photodetector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0575090A true JPH0575090A (en) | 1993-03-26 |
| JP3167150B2 JP3167150B2 (en) | 2001-05-21 |
Family
ID=17002946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23659391A Expired - Fee Related JP3167150B2 (en) | 1991-09-17 | 1991-09-17 | Semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3167150B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005036648A1 (en) * | 2003-10-07 | 2005-04-21 | Hamamatsu Photonics K.K. | Energy line detecting element |
| US7589775B2 (en) | 2003-04-23 | 2009-09-15 | Hamamatsu Photonics K.K. | Solid-state imaging device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101337866B (en) * | 2008-08-12 | 2010-12-29 | 苏州大学 | Method for preparing 1,2-dione by catalytic oxidation of alkyne |
| CN101768037B (en) * | 2010-01-13 | 2013-04-17 | 苏州大学 | Method for generating 1,2-diketone by oxidizing alkyne with ruthenium compound as catalyst |
-
1991
- 1991-09-17 JP JP23659391A patent/JP3167150B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7589775B2 (en) | 2003-04-23 | 2009-09-15 | Hamamatsu Photonics K.K. | Solid-state imaging device |
| WO2005036648A1 (en) * | 2003-10-07 | 2005-04-21 | Hamamatsu Photonics K.K. | Energy line detecting element |
| US7514687B2 (en) | 2003-10-07 | 2009-04-07 | Hamamatsu Photonics K.K. | Energy ray detecting element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3167150B2 (en) | 2001-05-21 |
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