JPH09198863A - Memory control apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control apparatus by which data in one block portion is transferred continuously without being interrupted halfway, which reduces noise and which prevents power consumption from being concentrated. SOLUTION: An access-suspension-period measuring part 1 receives a transfer request signal, and it identifies an access suspension period in which the transfer request signal is not sent out. A refresh number-of-times and cycle decision part 2 computes the number of times of refresh operations to be executed during one access cycle. In addition, during the access suspension period which is discriminated by the accesss-suspension-period measuring part 1, a refresh cycle in which refresh operations are performed the computed number of times is decided. A memory control part 3 performs refresh operations by the required number of times at the refresh cycle decided by the refresh number-of-times and cycle decision part 2 in such a way that the refresh operations are dispersed in the access suspension period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a memory device composed of a DRAM or the like, and more particularly to a memory control device having an improved refresh system for the memory device.

[0002]

2. Description of the Related Art Conventionally known memory control devices include:
As described in JP-A-6-111568, data for one line is continuously transferred without interruption in the middle, and the number of refresh requests generated during the transfer is counted. There is a system in which after the data transfer for one line is completed, the number of refreshes that cannot be performed is continuously performed. As a result, the image data for one line can be continuously processed, and the control circuit and the like can be simplified.

However, in this conventional device, switching noise is increased and power consumption is concentrated because refreshing is performed continuously for a number of times that could not be performed after the transfer of data for one line is completed. There is a problem that occurs. Further, in a device using a plurality of DRAMs, the refresh timing cannot be staggered, and due to momentary increase in power consumption, noise may be generated, which may cause malfunctions in other circuits due to fluctuations in the power supply ground. There were some drawbacks such as

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and one block of data is interrupted on the way by measuring the access suspension period and obtaining the refresh count and the cycle. Continuous transfer without refreshing and refreshing the number of cycles and the period according to the access suspension period to eliminate the concentration of power consumption, and in a device using a plurality of DRAMs, it is easy to shift the refresh timing arbitrarily. It is an object of the present invention to provide a memory control device capable of achieving the above.

[0005]

According to a first aspect of the present invention, there is provided an access pause period measuring means for predicting an access pause period in a memory control device of a dynamic memory capable of continuously accessing data at every predetermined cycle. Refresh frequency / cycle determining means for determining a necessary number and interval of refresh operations performed during the access suspend period based on the predicted access suspend period and the predetermined cycle, and a dynamic memory of the dynamic memory for the required number of times at the determined interval. It is characterized by having a memory control means for refreshing.

According to a second aspect of the present invention, in the memory control device according to the first aspect, there is further provided an access cycle measuring means for measuring a cycle of continuously accessing data, and the refresh frequency / cycle determining means. Is characterized in that the required number of times and the interval of the refresh are determined by using the cycle measured by the access cycle measuring means.

According to a third aspect of the present invention, in the memory control device according to the first or second aspect, a plurality of sets of the memory control means corresponding to the dynamic memory are provided, and the refresh frequency / cycle is set. It is characterized by further comprising refresh number / cycle changing means for changing the refresh timing so that the refreshes of the respective dynamic memories do not overlap with each other based on the required number of refreshes and the interval determined by the determining means.

[0008]

1 is a block diagram showing a first embodiment of a memory control device of the present invention. In the figure, 1
Is an access suspension period measuring unit, 2 is a refresh frequency / cycle determining unit, 3 is a memory control unit, and 4 is a dynamic memory. The access suspension period measuring unit 1 receives the transfer request signal and determines the access suspension period in which the transfer request signal is not transmitted. Refresh frequency / cycle determination unit 2
Receives the access cycle and calculates the number of refreshes to be performed during one access cycle. further,
During the access suspension period determined by the access suspension period measuring unit 1, the refresh cycle for performing the calculated number of refreshes is determined. The memory control unit 3
In the refresh cycle determined by the refresh frequency / cycle determining unit 2, a required number of refreshes are performed during the access suspension period. At this time, the refresh is not performed while the access is being performed. Therefore, continuous data transfer is possible.

FIG. 2 is a block diagram showing a second embodiment of the memory control device of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. Reference numeral 5 is an access cycle measuring unit. The access cycle measuring unit 5 receives the transfer request signal, measures the cycle of access for transfer, and passes it to the refresh frequency / cycle determining unit 2. In the refresh frequency / cycle determination unit 2, the access cycle measurement unit 5
Based on the access cycle measured in step 1, the number of times refresh should be performed is calculated, and the refresh cycle is determined during the access suspension period. According to this embodiment, it is not necessary to separately provide an access cycle.

FIG. 3 is an explanatory diagram showing an example of the refresh cycle determined in the first and second embodiments of the memory control device of the present invention. In FIG. 3, as for the transfer request signal, as shown in FIG. 3A, the H level is a period during which the memory is accessed to request the transfer, and the L level is an access suspension period. In the conventional memory control device,
As shown in FIG. 3B, when the transfer request signal is at the L level and the access suspension period is entered, the refresh is immediately performed the number of times to be executed by then. Here, refresh is performed after the CAS signal is set to the L level and then R
This is executed by setting the AS signal to L level. In FIG. 3, refreshing is performed four times.

According to the present invention, as shown in FIG. 3C, for example, when four refreshes must be performed during data transfer, a cycle for refreshing four times during the access suspension period is set. Determine and refresh based on the cycle. Therefore, as shown in FIG. 3 (C), refresh is dispersed and performed during the access suspension period. This suppresses the generation of switching noise during the access suspension period, and
Power consumption for refreshing can be dispersed. Of course, as described above, even when a memory device that refreshes with a refresh signal is used instead of the RAS signal and the CAS signal, the refresh can be similarly dispersed during the access suspension period.

FIG. 4 is a block diagram showing a specific example of the second embodiment of the present invention, and FIG. 5 is an explanatory diagram of an input reference signal of image data. In the figure, 11 is a controller, 12 is a refresh counter, 13 is a transfer cycle measurement counter, 14 is an LPW latch, 15 is a CYC latch,
16 is a frequency / cycle determination circuit, 17 is a cycle counter, 18
Is a number counter, 19 is a memory control circuit, and 20 is an image memory.

In this specific example, a case where an image read by an image reading device such as a scanner is transferred to and stored in the image memory 20 will be described as an example. Here, as an input reference signal when storing the read image data in the image memory 20, as shown in FIG. 5, a page sync (hereinafter referred to as PSYNC) and a C indicating an image effective area in the paper feed direction.
A line sync (hereinafter referred to as LSYNC) indicating an image effective area in the reading direction of the CD image sensor is used. This P
An area in which both SYNC and LSYNC are effective becomes an effective area for image data and is stored in the image memory 20.

Further, in this specific example, it is assumed that the periodic refresh operation is performed during the period when PSYNC is invalid, and when PSYNC is valid, the distributed refresh operation within the access suspension period as shown in FIG. 3C. Shall be switched to.

The controller 11 receives PSYNC and LSYNC from the outside such as an image reading device, and also receives the refresh end signal REF_END during the access suspension period from the number counter 18.
It also outputs to the refresh counter 12 a SYNC_REF signal indicating whether to perform a periodic refresh operation or a distributed refresh operation within the access suspension period based on the received PSYNC. Furthermore, LSY
When the NC becomes valid, the transfer cycle counter latch clear signal CYC_LTCL is sent to the transfer cycle measurement counter 13 and the CYC latch 15. Further, when the LSYNC becomes invalid, the LSYNC invalid address latch signal LPW_LT is set to the LPW latch 14 and the frequency counter 1.
8 is output. In addition, PSYNC is enabled and LS
When YNC becomes invalid, the refresh enable signal REF_EN indicating that the access suspension period has started is output to the cycle counter 17 and the number counter 18.

The refresh counter 12 counts the system clock and refresh clock REF_C.
K1 is generated and supplied to the memory control circuit 19. Also,
When the SYNC_REF signal is given from the controller 11, the refresh counter 12 is reset and stopped.

The transfer cycle counter 13 counts the system clock, and the transfer cycle counter latch clear signal CYC_LT output from the controller 11 is output.
Cleared by CL. Transfer cycle measurement counter 13
The count value of is supplied to the LPW latch 14 and the CYC latch 15.

The count value of the transfer cycle measuring counter 13 is supplied to the LPW latch 14, and the controller 11 sends the LSYNC invalid address latch signal LPW_L.
When T is input, the count value is fetched. This allows
The LPW latch 14 holds the count value during the valid period of LSYNC.

The count value of the transfer cycle measuring counter 13 is also supplied to the CYC latch 15, and the transfer cycle counter latch clear signal CYC_from the controller 11 is supplied.
When LTCL is input, the count value is fetched. As a result, the CYC latch 15 holds the count value for one transfer period.

The number / cycle determining circuit 16 determines the count value of the access valid period from the LPW latch 14 and CY.
The count value of one cycle is received from the C latch 15, and the number of times refreshing is not performed is further received from the number counter 18, to determine the number of refreshes to be performed and the cycle to be refreshed within the access suspension period. The number of refreshes is output to the counter 17 and the number of times to the counter 18.

The cycle counter 17 receives the refresh enable signal REF_EN from the controller 11,
Load the cycle calculated by the frequency / cycle determination circuit 16,
Immediately start addition or subtraction by the system clock. Then, the count enable signal is sent to the number counter 18 every refresh cycle.

The number-of-times counter 18 loads the number of times of refresh calculated by the number-of-times / cycle determining circuit 16 by the LSYNC invalid address latch signal LPW_LT.
Refresh enable signal RE from controller 11
When F_EN is received, the refresh request signal RE is input each time the count enable is input from the cycle counter 17.
While sending F_REQ to the memory control circuit 19,
Adds or subtracts the value of the counter. When the refresh request signal REF_REQ for the number of refresh times calculated by the number / cycle determination circuit 16 is output, the refresh end signal REF_END indicating that the refresh is completed is returned to the controller 11.

The memory control circuit 19 uses the refresh clock REF_C generated by the refresh counter 12.
The image memory 20 is refreshed according to K1 and the refresh request signal REF_REQ output from the number counter 18.

The image memory 20 is composed of DRAM and is refreshed by the memory control circuit 19. As a specific refresh cycle, a 512 cycle / 8 msec DRAM can be used. In this case, when performing refreshing at a fixed period, 15.
Refresh is performed at intervals of once every 625 μsec. Further, when performing the distributed refresh operation within the access suspension period, it is sufficient to perform refreshing a total of 512 times or more within 8 msec.

FIG. 6 is a block diagram showing an example of the frequency / cycle determination circuit 16 in a specific example of the second embodiment of the present invention. In the figure, 21 is a subtractor, 22 is a decoder,
Reference numeral 23 is an adder, and 24 is a division table. As described above, the number / cycle determination circuit 16 receives the count value of the period being accessed from the LPW latch 14, and the CYC
The count value of one cycle is received from the latch 15.

The subtractor 21 subtracts the count value of the access valid period from the count value of one cycle to obtain the access suspension period. On the other hand, the decoder 22 obtains the number of refreshes performed in one cycle based on the count value of one cycle. The number of refreshes is obtained from (access cycle / constant cycle of refresh) +1 times. The adder 23 includes a refresh counter calculated by the decoder 22 and a counter 1
8 is added to the number of refreshes not yet performed, and the number of refreshes to be performed in the next access suspension period is calculated. The number of refreshes calculated is
The number of times counter 18 is set. Further, the division table 24 divides the access suspension period obtained by the subtracter 21 by the number of refreshes to be performed obtained by the adder 23 to obtain a refresh cycle. The obtained refresh cycle is set in the cycle counter 17.

By providing these calculation results to the cycle counter 17 and the number counter 18 and operating during the access suspension period, refreshing can be executed with a fixed period during the access suspension period.

Next, an example of the operation in one specific example of the second embodiment of the present invention will be described. FIG. 7 is a timing chart showing an example of the operation in a specific example of the second exemplary embodiment of the present invention. An example of the operation of the configuration shown in FIGS. 4 and 6 will be described below with reference to FIG.

First, in the case of refreshing the image memory 20 when PSYNC is invalid, the refresh clock REF_CK1 generated by the refresh counter 12 is sent to the memory control circuit to perform refreshing at a constant cycle. This operation is performed in the section of FIG. For example, in the case of a DRAM whose image memory 20 has a refresh cycle of 512 cycles / 8 msec,
Refresh is performed once every 15.625 μsec.

When PSYNC becomes valid, the controller 11 sends the SYNC_REF signal to the refresh counter 1
2, the refresh counter 12 is returned to the initial value and stopped, and the distributed refresh operation is switched within the access suspension period.

When LSYNC becomes valid, the controller 11 clears the transfer cycle counter latch latch CYC_LTCL.
Is enabled and the value of the transfer cycle measurement counter 13 is loaded into the CYC latch 15, and at the same time the transfer cycle measurement counter 1
3 is reset to 0 and the next transfer cycle is counted. Next, when LSYNC is disabled, controller 1
1 outputs the LSYNC invalid address latch signal LPW_LT and fetches the value of the transfer cycle measurement counter 13 into the LPW latch 14. The measurement of the access cycle and the access suspension period is achieved by continuously performing the above operation.

In the frequency / cycle determining circuit 16, a value required for controlling refresh is obtained from the values of the LPW latch 14 and the CYC latch 15. During the access suspension period,
It is obtained by the subtracter 21 from the output of the CYC latch 15 and the output of the LPW latch 14. In addition, the refresh frequency is
In the decoder 22 and the adder 23, for example, (C
YC latch / 15.625 μsec) + 1 + number of unexecuted times. Further, the refresh cycle is obtained from (access suspension period / refresh count) in the division table 24. The number-of-times counter 18 loads the number of times of refreshing according to the LSYNC invalid address latch signal LPW_LT. The cycle counter and the frequency counter are refresh enable signals REF from the controller 11.
Since _EN operates only during the access suspension period, LS
The operation is started immediately after the data is taken in by the input of the YNC invalid address latch signal LPW_LT.

First, when the LSYNC invalid address latch signal LPW_LT is input to the number counter 18, the first refresh request REF_REQ is output and the value of the number counter 18 is down-counted (-1). After that, the cycle counter 17 counts up and outputs a count enable to the number counter 18 each time the value of the cycle determined by the cycle / cycle determining circuit 16 is reached. Upon receiving this count enable, the number counter 18 outputs the refresh request REF_REQ and down-counts (-1) the value of the number counter 18. This operation is continued until the number counter 18 reaches 0. When the frequency counter 18 reaches 0, the refresh end REF_END is returned to the controller 11,
Refreshing during the access suspension period ends. This refresh operation is performed in the section shown in FIG. Each refresh is performed in a distributed manner, for example, as shown in FIG.

At this time, if the access suspension period ends before the count counter 18 reaches 0 due to a change in the access cycle or the access suspension period, the count counter 1
The value of 8 is returned to the number / cycle determination circuit 16 as the number of times refresh has not been performed, and is added to the next number of refreshes. As a result, the number of refreshes and the refresh cycle are changed, and processing is automatically performed so that insufficient refresh does not occur.

The above operation is repeatedly executed while PSYNC is valid. After continuing such operation, PS
When the YNC is invalidated, the LSYNC is invalidated after the PSYNC is invalidated, and refresh is performed as many times as necessary in the refresh cycle of the distributed refresh. After that, the number counter 18 outputs the refresh end REF_END to the controller 11 to end the distributed refresh operation. After that,
The operation of the refresh counter 12 is restarted by returning to the refresh of a fixed cycle. In FIG. 7, after performing the last distributed refresh operation in a section, refreshing is performed in a constant cycle in the subsequent section.

This final distributed refresh operation is
Even if the access suspension period is shortened due to a change in the access cycle, the refresh operation is continued until the number counter 18 reaches 0 so that the refresh shortage does not occur.

By performing such an operation, it is possible to easily perform optimum distributed processing of refresh during the access suspension period.

FIG. 8 is a block diagram showing a third embodiment of the memory control device of the present invention. In the figure, the same parts as those in FIG. 6 is a refresh frequency / cycle changing unit, 7 is a memory control unit, and 8 is a dynamic memory. In the third embodiment,
An example having a memory control unit corresponding to a plurality of dynamic memories is shown. The memory control unit 7 and the dynamic memory 8 are the same as the memory control unit 3 and the dynamic memory 9. The set of the memory control unit and the dynamic memory will be called a refresh group. Although the third embodiment has a configuration having a plurality of dynamic memories and a memory control unit in the above-described second embodiment, in the first embodiment,
A configuration having a plurality of dynamic memories and memory control units may be used.

The refresh frequency / cycle changing unit 6 is arranged so that the refresh times in the dynamic memory 4 and the dynamic memory 8 are distributed as much as possible based on the refresh frequency and the refresh cycle determined by the refresh frequency / cycle determining unit 2. Change the refresh timing of. In each of the memory control units 3 and 7, the dynamic memories 4 and 8 are refreshed at the refresh timing changed by the refresh frequency / cycle changing unit 6.

FIG. 9 is an explanatory diagram showing an example of the refresh cycle determined in the third embodiment of the memory control device of the present invention. In FIG. 9, as in FIG. 3, the transfer request signal is shown in FIG. The L level is the access suspension period.

In this embodiment, as shown in FIG. 9B, for example, when four refresh operations must be performed in each refresh group during data transfer, a total of eight refresh operations are performed during the access suspension period. The timing for performing the refresh is determined, and the refresh is performed based on the timing. The refresh timing determined at this time is such that the refresh is alternately performed between the refresh groups as shown in FIG. 9C, or one refresh is performed first as shown in FIG. 9B. , Decided to do the other later. The timing of each refresh is determined to be distributed and performed during the access suspension period. As a result, similarly to the above-described first and second embodiments, the generation of switching noise during the access suspension period is suppressed, and the refreshing between refresh groups does not overlap, so that the power consumption for refreshing is dispersed. be able to. Of course, as mentioned above, RAS
Even when a memory device that refreshes by a refresh signal is used regardless of a signal or a CAS signal, refresh can be similarly dispersed and performed during an access suspension period.

FIG. 10 is a block diagram showing a specific example of the third embodiment of the present invention, and FIG. 11 is a diagram showing the number / cycle determining circuit 16 of the specific example of the third embodiment of the present invention. It is a block diagram which shows an example. 4 and 6 in the figure
The same reference numerals are given to the same portions as, and the description thereof will be omitted. 3
1 is a selector, 32 is a memory control circuit, 33 is an image memory, and 41 is a multiplier. In the configuration shown in FIG. 10, there are two refresh groups, a refresh group including the memory control circuit 19 and the image memory 20, and a refresh group including the memory control circuit 32 and the image memory 33. Therefore, in this configuration, the SEL signal for setting the number of refresh groups and the mode in which the refresh of the image memory is switched once each as shown in FIG. 9C, or in the group unit as shown in FIG. 9B. It has a MODE signal for selecting whether to switch. A plurality of DRAMs can be refreshed by using these control signals.

The number / cycle determination circuit 16 has a new SE
The L signal is input, the total number of refreshes is calculated by multiplying the number of refreshes calculated from the count value of one cycle sent from the CYC latch 15 by the number of refresh groups given by the SEL signal, and set in the number counter 18. To do. Further, the refresh cycle is calculated from the total number of times of refreshing and the data pause period, and set in the cycle counter 17.

Specifically, as shown in FIG. 11, the number of refreshes to be performed in one cycle by the decoder 22 is calculated,
The multiplier 41 multiplies the number of refresh groups.
Further, the adder 23 adds the number of times refreshing has not been performed that remains in the number counter 18 to obtain the total number of refreshes. The multiplier 41, for example, when the number of refresh groups is 2, 4, 8, ...
You may comprise a shifter.

The selector 31 receives the refresh request REF_REQ from the frequency counter 18 and the count value. Further, it receives a SEL signal indicating the number of refresh groups and a MODE signal instructing mode selection. Then, based on these count value, SEL signal, and MODE signal, FIG.
As shown in (C), the refresh request REF_REQ is sent to each refresh group.

For example, when refreshing two refresh groups in the mode shown in FIG. 9C as shown in FIG. 10, this condition is set by the SEL signal and the MODE signal, and the selector 31 sets the number of times. Counter 1
Each time the refresh request REF_REQ is received from 8, the refresh group is switched and the refresh request REF_REQ is transmitted. In addition, FIG.
When refreshing in the mode shown in (B),
The refresh request REF_REQ may be continuously transmitted to one side according to the count value, and when the count value becomes half, the refresh group may be switched and the subsequent refresh request REF_REQ may be transmitted.

In this way, the value of the frequency counter and S
By switching the output destination of the refresh request according to the EL signal and the MODE signal, even in a device using a plurality of DRAMs, it is possible to easily perform the optimal distributed refresh processing during the access suspension period. Also,
Since refreshes are dispersed in each refresh group and the entire device, noise can be reduced and power consumption can be dispersed.

In the configuration shown in FIG. 10, the refresh clock REF_CK1 from the refresh counter 12 is supplied to each refresh group in common at the time of refreshing in a constant cycle. Is shortened and the selectors are sequentially switched and supplied to each refresh group, so that the refresh can be dispersed even when refreshing at a constant cycle.

[0049]

As is apparent from the above description, according to the present invention, one block of data is continuously transferred,
By performing the refresh to be performed during the data transfer in the access suspension period in a distributed manner, switching noise generated by the refresh performed in the access suspension period can be reduced and the power consumption can be dispersed.

Further, even in a device using a plurality of DRAMs, it is possible to avoid the overlap of refresh periods with other DRAMs, to prevent an instantaneous increase in power consumption, to generate noise, to fluctuate the power supply ground, etc. There is an effect that it can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory control device of the present invention.

FIG. 2 is a block diagram showing a second embodiment of a memory control device of the present invention.

FIG. 3 is an explanatory diagram showing an example of a refresh cycle determined in the first and second embodiments of the memory control device of the present invention.

FIG. 4 is a block diagram showing a specific example according to the second embodiment of the present invention, and FIG. 5 is an explanatory diagram of an input reference signal of image data.

FIG. 5 is an explanatory diagram of an input reference signal of image data.

FIG. 6 is a block diagram showing an example of a frequency / cycle determination circuit 16 in a specific example of the second embodiment of the present invention.

FIG. 7 is a timing chart showing an example of operation in a specific example of the second exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing a third embodiment of the memory control device of the present invention.

FIG. 9 is an explanatory diagram showing an example of a refresh cycle determined in the third embodiment of the memory control device of the present invention.

FIG. 10 is a block diagram showing a specific example according to the third embodiment of the present invention, and FIG. 11 shows an example of the number / cycle determination circuit 16 according to a specific example of the third embodiment of the present invention. It is a block diagram.

FIG. 11 is a block diagram showing an example of a frequency / cycle determination circuit 16 in a specific example of the third exemplary embodiment of the present invention.

[Explanation of symbols]

1 ... Access suspension period measurement unit, 2 ... Refresh frequency
Cycle determining unit, 3 ... Memory control unit, 4 ... Dynamic memory, 5 ... Access cycle measuring unit, 6 ... Refresh frequency
Cycle change section, 7 ... Memory control section, 8 ... Dynamic memory, 11 ... Controller, 12 ... Refresh counter, 13 ... Transfer cycle measurement counter, 14 ... LPW latch, 15 ... CYC latch, 16 ... Number / cycle determination circuit,
17 ... Cycle counter, 18 ... Number counter, 19 ... Memory control circuit, 20 ... Image memory, 21 ... Subtractor, 22 ...
Decoder, 23 ... Adder, 24 ... Division table, 31 ...
Selector, 32 ... memory control circuit, 33 ... image memory,
41 ... Multiplier.

Claims (3)

[Claims] 1. A memory control device of a dynamic memory capable of continuously accessing data in every predetermined cycle, wherein an access stop period measuring means for predicting an access stop period, the predicted access stop period and the predetermined cycle are provided. On the basis of the above, there is provided a refresh frequency / cycle determining means for determining a necessary number and an interval of refresh performed during the access suspension period, and a memory control means for refreshing the dynamic memory by the required number of times at the determined interval. Memory controller. 2. An access cycle measuring means for measuring a cycle of continuous data access is further provided, and the refresh frequency / cycle determining means uses the cycle measured by the access cycle measuring means. The memory control device according to claim 1, wherein the required number of times and the interval are determined. 3. A plurality of sets of the memory control means corresponding to the dynamic memories are provided, and the dynamic memories of the respective dynamic memories are based on the required number of refreshes and intervals determined by the refresh count / cycle determining means. 3. The memory control device according to claim 1, further comprising refresh frequency / cycle changing means for changing refresh timing so that refresh does not overlap.