JPH0390943A - Method and device for controlling memory of microcomputer - Google Patents

Abstract

PURPOSE:To attain an access to the entire area of a RAM with no waste by eliminating the overlapping between the RAM and ROM areas. CONSTITUTION:When a designated address exceeds the maximum address of a ROM 3, an address obtained by applying a subtraction shift to the address given from a subtractor by an extent equal to the address of the ROM 3 is outputted via a selector. Then a RAM 2 receives an access based on the outputted address. If the designated address is less than the minimum address of the ROM 3, the designated address is outputted as it is via the selector. Then the RAM 2 receives an access based on the designated address. When the ROM area receives an access, a ROM enable signal is outputted and the ROM 3 receives an access based on the designated address received from a microprocessor 1. Thus the entire area of the RAM 2 can receive an access with no waste.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a read-only memory, a random access memory, and a microprocessor for accessing each of these memories, and provides a read-only memory, a random access memory, and a microprocessor for accessing each of these memories. The present invention relates to a memory control method and a memory control device for a microcomputer that includes a dedicated memory area.

[Prior Art] In recent years, the capacity of random access memory (hereinafter referred to as RAM) in microcomputers has become considerably larger, and the memory space that can be specified for one memory IC has become wider. For this reason, there arises the inconvenience that a RAM exists in an area where a read-only memory (hereinafter referred to as ROM) is desired to be placed.

For this reason, in the past, the ROM area was separated so that ROM and RAM were not accessed at the same time, and the entire memory space was made into a RAM area (Japanese Patent Laid-Open No. 58-58
665 (see Japanese Patent Application Laid-open No. 58-203560) and one in which RAM and ROM are accessed by switching between them using a mode signal (see Japanese Patent Laid-Open No. 58-203560).

[Problems to be Solved by the Invention] However, in this conventional device, when the ROM is enabled, the RO in the RAM area shown by diagonal lines in FIG.
There is a problem in that the portion that overlaps with the M area cannot be accessed, and therefore RAM having the same capacity as the ROM capacity is wasted.

Therefore, the present invention provides a memory control method and a memory control device for a microcomputer that can eliminate the overlap between the RAM area and the ROM nR area and access all of the RAM area without waste in a system where a ROM area exists within the RAM area. This is what we are trying to provide.

[Means for Solving the Problems] The present invention provides a read-only memory, a random access memory, and a microprocessor that accesses each memory, and a read-only memory area is interposed within the address of the random access memory area. When the microprocessor accesses a memory area larger than the maximum address of the read-only memory in a microcomputer, the address specified by the microprocessor is subtracted and shifted by the capacity of the read-only memory, and random access is performed. When accessing a memory area below the minimum address of read-only memory, random access memory is accessed without converting the specified address by the microprocessor, and when the microprocessor accesses a memory area within the read-only memory area, This is a memory control method in which an enable signal is output to a read-only memory and the read-only memory is accessed without converting a specified address by a microprocessor.

The present invention also provides a subtracter that subtracts an address corresponding to the capacity of the read-only memory from an address specified by the microprocessor, and a first comparison device that compares and determines whether the address specified by the microprocessor is equal to or greater than the maximum address of the read-only memory. a second comparator that compares and determines whether the address specified by the microprocessor is less than the minimum address of the read-only memory; a selector that outputs the address designated by the microprocessor as is when the first comparator compares and determines that it is less than the maximum address; and a second comparator that compares and determines that the first comparator is less than the maximum address. A signal output means is provided for outputting an enable signal for the read-only memory when the signal output means compares and determines that the address is greater than or equal to the minimum address, and when the enable signal is not output from the signal output means, the random access memory is accessed based on the address output from the selector. The memory control device accesses the read-only memory based on an address designated by the microprocessor when an enable signal is output from the signal output means.

[Operation] In the present invention having such a configuration, the address corresponding to the capacity of the read-only memory is subtracted from the address designated by the microprocessor by the subtracter.

On the other hand, a first comparator compares and determines whether the specified address is greater than or equal to the maximum address of the read-only memory, and a second comparator compares and determines whether the specified address is less than the minimum address of the read-only memory. be done.

If the specified address is greater than or equal to the maximum address of the read-only memory, the address from the subtracter is sent via the selector,
That is, an address obtained by subtracting and shifting the designated address by the address of the read-only memory is output, and the random access memory is accessed based on that address. If the designated address is less than the minimum address of the read-only memory, the designated address is output as is through the selector, and the random access memory is accessed based on the designated address. In this way, random access memory is accessed at consecutive addresses across all areas.

Also, when accessing the ROM area, the specified address is within the range of less than the maximum address of the read-only memory and greater than the minimum address, so in this case, the read-only memory enable signal is output, and the read-only memory is accessed from the specified address from the microprocessor. will be accessed by.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microcomputer, in which 1 is a microprocessor that constitutes the main body of the control section, 2
is RAM (random access memory), 3 is RO
M (read-only memory), 4 is I10 controller,
Reference numeral 5 denotes a memory control circuit constituting a main part.

The microprocessor 1, ROM 3, and I10 controller 4 are connected by an address path line 6, a data path line 7, and a control path line 8.

Further, the microprocessor 1 and the RAM 2 are connected by the data path line 7 and the control path line 8.

Further, the microprocessor 1 and the memory control circuit 5 are connected to the address path line 6 and the data path line 7.
connected by.

Then, the memory control circuit 5 performs R for the RAM 2.
It is connected via an AM address path line 9.

Further, a ROM enable signal E is sent from the memory control circuit 5.
N is supplied to the ROM 3.

The memory control circuit 5 is constructed as shown in FIG. That is, RO for the data path line 7
An M area start address register 21 and a ROM area end address register 22 are connected. A write control signal IOW is also input to each of the registers 21 and 22. Then, in the ROM area start address register 21, the start address data ADDH, which is the maximum address data of the ROM area, is stored by the microprocessor 1 via the data path line 7 by the manual input of the write control signal 10W. End address data ADDL, which is the minimum address data of the ROM area, is stored in the end address register 22 by the microprocessor 1 via the data path line 7 by the manual input of the write control signal 10W.

The first address data ADDH stored in the first 82 ROM area first address register 21 is supplied to a first subtracter 23 and a first comparator 24, respectively. Further, the end address data ADDL stored in the ROM area end address register 22 is supplied to the first subtracter 23 and the second comparator 25, respectively.

The first subtracter 23 subtracts the end address data ADDL from the start address data ADDH to obtain an address amount corresponding to the capacity of the ROM 3, and then subtracts the end address data ADDL from the start address data ADDH to obtain an address amount corresponding to the capacity of the ROM 3.
is supplied to the subtracter 26.

The designated address LA from the microprocessor 1 transferred via the address path line 6 is input to the second subtracter 26, the first and second comparators 24 and 25, and the selector 27, respectively.

The second subtracter 26 subtracts the address amount from the first subtracter 23 from the specified address LA from the microprocessor 1, subtracts and shifts the specified address by the capacity of the ROM 3, and transfers the shifted address to the selector. 27.

The first comparator 24 compares and determines whether the specified address LA from the microprocessor 1 is greater than or equal to the start address ADDH, and when ADDH≦LA, it outputs a high level signal, AD
When DH>LA, a low level signal is supplied to the selector 27 and also supplied to the two-manual AND gate circuit 29 via the inversion circuit 28.

When the selector 27 receives a high level signal from the first comparator 24, the address data from the second subtracter 26 is sent to the R address via the RAM address pass line 9.
When a low level signal is input from the first comparator 24, the specified address data from the address pass line 6 is directly passed through the RAM address pass line 9 to the RAM address pass line 9. RAM2
The selection operation is performed so that the signal is supplied to the terminal.

The second comparator 25 compares and determines whether or not the designated address LA from the microprocessor 1 is less than the end address ADDL, and when ADDL5LA, a high level signal, AD
When DL>LA, a low level signal is supplied to the AND gate circuit 29.

The AND gate circuit 29 supplies a ROM enable signal EN to the ROM 3 when both of the two input signals are at a high level.

In this embodiment with such a configuration, for example, as shown in FIG. 3(a), the addresses in the RAM area are 0 to F.
In FFFFF, if the address ADDL-ADDH of the ROM area exists in the RAM area, then the specified address LA from the microprocessor 1 is LA≧ADDH.
When , the selector 2 is selected by the output of the first comparator 24.
7 selects the address data from the second subtractor 26. This address data indicates that the specified address LA is rLA-(
The address is converted to ADDH-ADDL)J.

Thus, RAM2 is accessed by address rLA-(ADDH-ADDL)J.

Also, the specified address LA from microprocessor 1 is L.
When A<ADDH, the selector 27 selects designated address data from the address pass line 6 based on the output of the first comparator 24.

In this case, if LA<ADDL, the RAM 2 will be directly accessed by the designated address LA.

Therefore, RAM2 is 0 to rF as shown in FIG. 3(b).
Accesses are made with consecutive addresses up to FFFFF-(ADDH-ADDL)J.

Further, when the specified address LA is ADDH>LA≧ADDL, both the input signals to the AND gate circuit 29 are at high level, so the ROM enable signal EN is outputted from the AND gate circuit 29 and supplied to the ROM 3. Therefore, in this case, the specified address LA from the microprocessor 1 is sent to R via the address path line 6.
It will be directly supplied to OM3 and ROM3 will be accessed.

In this way, the RAM area and ROM area are addressed and accessed so that they do not overlap, so the RAM area
There is no useless area that is not accessed in the area.

Further, even if the address of the ROM area is arbitrarily changed, this can be easily handled by changing the start address and end address stored in each register 21, 22 accordingly. Furthermore, even if the capacity of the ROM is to be increased, this can be easily handled by setting the start address and end address accordingly.

In the above embodiment, the ROM area start address register 21, the ROM area end address register 22, and the first subtracter 23 are omitted, and the first and second comparators 24.2 are omitted.
5 and the fixed data A preset in the second subtractor 26
DDH, ADDL.

(ADDH-ADDL) may be manually operated directly.

[Effects of the Invention] As detailed above, according to the present invention, in a device in which a ROM area exists within a RAM area, the RAM area and RO
It is possible to provide a memory control method and a memory control device for a microcomputer that eliminates overlapping of M areas and allows access to all RAM areas without waste.

[Brief explanation of drawings]

1 to 3 show embodiments of the present invention.
The figure is a block diagram showing the configuration of the microcomputer, FIG. 2 is a block diagram showing the specific configuration of the memory control circuit,
Figure 3 is a memory map showing the relationship between the RAM nA area, ROM area and addresses, and Figure 4 is a conventional RAM map.
This is a memory map showing the relationship between areas and ROM eM areas. 1... Microprocessor, 2... RAM (Random Access Memory), 3
... ROM (read-only memory), 5... memory control circuit, 24... first comparator, 25... second comparator, 26... second subtractor, 27. ...Selector, 28...Inversion circuit, 29...AND gate circuit. Outsourcing agent

Claims (2)

[Claims] (1) In a microcomputer that is provided with a read-only memory, a random access memory, and a microprocessor that accesses each of these memories, and in which the read-only memory area is interposed within the address of the random access memory area, the microprocessor When accessing a memory area larger than the maximum address of the read-only memory, the address designated by the microprocessor is subtracted and shifted by the capacity of the read-only memory to access the random access memory, and the microprocessor accesses the random access memory. When accessing a memory area less than the minimum address of the memory, the random address is used without converting the specified address by the microprocessor.
When the access memory is accessed and the microprocessor accesses a memory area within the area of the read-only memory, an enable signal is output to the read-only memory so that the microprocessor reads the specified address without converting it. A memory control method for a microcomputer characterized by accessing a dedicated memory. (2) In a microcomputer that is provided with a read-only memory, a random access memory, and a microprocessor that accesses each of these memories, and in which the read-only memory area is interposed within the address of the random access memory area, the microprocessor a subtracter that subtracts an address corresponding to the capacity of the read-only memory from a designated address; a first comparator that compares and determines whether the address designated by the microprocessor is equal to or greater than the maximum address of the read-only memory; a second comparator that compares and determines whether the address designated by the processor is less than the minimum address of the read-only memory; and when the first comparator compares and determines whether or not the address specified by the processor is equal to or greater than the maximum address, outputs the address from the subtracter. and a selector that outputs the address designated by the microprocessor as is when the first comparator compares and determines that the address is less than the maximum address; signal output means for outputting an enable signal for the read-only memory when the comparator compares and determines the minimum address or more; Random access
A memory control device for a microcomputer, wherein the read-only memory is accessed based on an address designated by the microprocessor when an enable signal is output from the signal output means.