JPH08147214A - Memory device - Google Patents

Abstract

PURPOSE: To provide a memory device capable of always high speedily completing access without depending on an address to start burst access. CONSTITUTION: This memory device is provided with a memory controller 11 for outputting a signal '*CE-EVEN' for instructing an address counter 12EVEN to count-up an address stored inside asynchronously with a CPU cycle starting the burst access to the memory device when the start address of that CPU cycle is an odd number and a LOAD signal generating circuit 14 for generating a '*LOAD' signal asynchronous with the CPU cycle so as to enable the count-up of the address counter 12EVEN. Thus, the second data can be outputted to a memory bank 13EVEN in the third CPU cycle after access is started and even at the time of odd number address start, the data can be outputted from the second CPU cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device,
In particular, the present invention relates to a burst-accessible memory device having a plurality of address-interleaved memory banks.

[0002]

2. Description of the Related Art RISC (Reduced Instruction Set Com)
Some puter) type CPUs support a memory access mode called burst access. The burst access mode is an access mode provided to access data at consecutive addresses at high speed. In this access mode, as shown in FIGS. 8 and 9, the memory device 32 to be accessed from the CPU 31 is used. , A control signal indicating that burst access is to be performed and only the first address (start address) of the data to be accessed are supplied, and the CPU 31 then outputs the data (output to the data bus by the memory device 32). Data 0 and data 1) are acquired in synchronization with the clock (CLK) to access data at consecutive addresses.

Thus, during burst access, C
Since only the start address is output from the PU, the CPU that performs burst access is used in combination with a memory device that has a function of sequentially changing the address of data to be output based on the start address supplied from the CPU. Will be.

As a memory device (memory chip) that can be used in combination with a CPU that performs burst access,
It is known that the memory chip itself has a function capable of supporting burst access, and the normal memory chip has some circuits added thereto so as to support burst access.

Of these, the former type of memory chip (memory device) is rarely manufactured, and when a system capable of burst access is constructed using such a memory chip, the memory capacity of the system is manufactured. It is limited by the capacity of the existing memory chip, and there is a problem that the system cannot be freely designed. Further, since such a memory chip is also expensive, there is a problem that the system becomes expensive.

On the other hand, since the latter memory device can be constructed by using a memory chip that is widely and generally used, the memory capacity can be set arbitrarily and the system can be constructed at low cost. It will also be possible. When such a memory device is configured by using a memory having a relatively slow access time, a circuit is formed by using a plurality of memory banks so that each memory bank outputs data cyclically. Banks are being controlled.

An outline of a conventional memory device will be described below by taking the case of using two memory banks as an example.

FIG. 10 shows the structure of a conventional memory device having two memory banks. * BURST, * ROMO in the figure
E, * ROMCS, and CLK are control signals supplied from a CPU (not shown) that supports burst access, and * RADY is a control signal supplied to the CPU. First, the outline of each circuit constituting the memory device will be described with reference to this drawing.

The address counters 22 _EVEN and 22 _ODD are
When the enable level signal “* LOAD” is input from the memory controller 21, the circuit is configured to take in the address on the address bus and output the address to the memory banks 23 _EVEN and 23 _ODD. Yes, enable level signal “* CE-EVEN”,
When "* CE-ODD" is input, it also counts up the address stored internally.

The memory banks 23 _EVEN and 23 _ODD are memory banks in which data of even addresses and odd addresses are stored, respectively, and the address of the data to be output from each memory bank 23 is an address counter 22 _EVEN and 22 _EVEN .
Each memory bank 23 is designated by _ODD , and each memory bank 23 receives the enable level signal “* OE-
When “EVEN” or “* OE-ODD” is input, the data of the corresponding address is output to the data bus. In the memory device described here, the memory bank 23 has an access time of 1 CPU. A cycle type is used.

The memory controller 21 controls the control signals (* BURST, * ROMOE, * ROMCS) input from the CPU and the clock.
Signals (* LOAD, * CE-EVEN, * OE-EVEN, * CE-ODD, * OE- for controlling the address counter 22 and memory bank 23 based on (CLK) and the least significant bit A0 of the address bus. OD
D) is created, and as shown in FIG. 11, "IDLE", "SIM-EVEN", and
"SIM-ODD", "preBUR-ODD", "BUR-EVEN", "BUR-
Six states (states) such as "ODD" are converted to the signal "* BUR".
It is configured to make a transition in accordance with the level of “ST” or “* ROMCS”, and to output a control signal (FIG. 12) of a level defined for each state in each transitioned state.

First, the operation during simple access (access for outputting data for one address) will be briefly described with reference to these figures.

Of the states taken by the memory controller 21, the "SIM-EVEN" and "SIM-ODD" states are prepared for responding to the simple access, and as shown in FIG. The transition from the “IDLE” state to the “SIM-EVEN” state is “! ROMCS & BURST &!
A0 "(Signal" * ROMCS "=" L "and Signal" * BURST "=
The transition to the "SIM-ODD" state is executed under the condition of "H" and the least significant bit A0 = "0" of the address, and "! ROMCS & BURST &A0" (signal "* ROMCS" = "L" and signal " * BURST ”=“ H ”and the least significant bit of the address
It is executed under the condition of A0 = "1").

That is, the transition to the "SIM-EVEN" and "SIM-ODD" states is performed at the time of memory access instructed by the signal "* BURST" that it is not burst access. At this time, if the address supplied from the CPU is an even address (A0 = "0"), "SIM-
EVEN "transition to the state is carried out. In this state, as is shown in FIG. 12, the enable level of the signal" because * OE-EVEN "is input to the memory banks 23 _EVEN, memory bank 23 _EVEN is Address counter 22
Data corresponding to the address supplied from _EVEN will be output to the data bus, and the data will be C
It will be stored in the PU.

As described above, in order to output the data of the address whose supply is started in the "IDLE" state in the next CPU cycle, the memory bank 23 having an access time of about 1 CPU cycle is used. When a memory bank with a slower access time is used, control is performed in a procedure different from this.

Next, the operation during burst access will be described.

Among the transition states of the memory controller 21, "BUR-EVEN", "preBUR-ODD", "BUR-ODD"
The "state" is a state provided to deal with a burst access request. Among these states, "BUR-EVEN" and "BUR-ODD" are burst access with even address start or odd address start. Also used in, the "preBUR-ODD" state is used only at odd address start.

That is, in the burst access of the even address start, both the signal "* ROMCS" and the signal "* BURST" become "L", and the least significant bit A0 of the address becomes "0" (! ROMCS &! BURST &! A0). ), As shown in FIG. 11, the transition from the “IDLE” state to the “BUR-EVEN” state is performed, and then the end of burst access is instructed by the CPU (signal “* ROMCS” = “H”). Unless "), the transition between" BUR-ODD "and" BUR-EVEN "states is repeated every CPU cycle, and" preBUR-O "
There is no transition to the DD ”state.

On the other hand, in the burst access of odd address start, both the signal "* ROMCS" and the signal "* BURST" are "L", and the least significant bit A0 of the address is "1" (! ROM).
CS &! BURST & A0), transition from "IDLE" state to "preBUR-ODD" state first, and then transition between "BUR-EVEN" and "BUR-ODD" states every CPU cycle Is being repeated.

In this way, at the start of odd addresses,
The reason why the transition to the special state (“preBUR-ODD”) is performed will be described with reference to FIGS. 13 and 14. Note that FIG. 13 is a timing chart of burst access started at even addresses in the conventional memory device, and FIG. 14 is a timing chart of burst access started at odd addresses.

As shown in FIG. 13, in the burst access of the even address start, the transition from the "IDLE" state to the "BUR-EVEN" state is first performed, and in the "BUR-EVEN" state, The enable level signals “* CE-EVEN” and “* OE-EVEN” will be output. Therefore, the memory bank 23 _EVEN receiving the enable level signal “* OE-EVEN” transfers the data of the address supplied from the “IDLE” state onto the data bus, as in the “SIM-EVEN” state. Will be output.

In the "BUR-EVEN" state, "SIM-
Unlike the "EVEN" state, the enable level signal "* CE-EVEN" is also output, so the address counter 22 _{EV EN} starts counting up the address held internally, and this "BUR-EVEN" At the end of the "state, counting up of the address in the address counter 22 _EVEN is completed, and the supply of a new address (ADD EVEN: address 2) to the memory bank 23 _EVEN is started.

Thus, the data bank 2 _EVEN is ready to output the data 2 in the fourth CPU cycle, and the memory bank 23 _ODD is ready to output the data 1 in the second CPU cycle. Since it has been completed, as shown in FIG. 13, in the burst access of the even address start, the “BUR-EVEN” and “BUR-ODD” states are alternately repeated after the “IDLE” state. From the second CPU cycle, data can be sequentially output for each CPU cycle.

However, when the odd address starts, 2
The data that needs to be output second is memory bank 2
The address stored in 3 _EVEN and for designating the data is an address different from the start address supplied from the CPU. Therefore, when starting an odd address, it is necessary to instruct the address counter 23 _EVEN to count up the address in advance.

The state provided for this purpose is
It is in "preBUR-ODD" state, and in the conventional memory device, during burst access of odd address start,
As shown in FIG. 14, by making a transition from the “IDLE” state to the “preBUR-ODD” state (see FIG. 12) in which only the signal “* CE-EVEN” is enabled, 2nd data required in memory bank 23 _EVEN from the next CPU cycle of "preBUR-ODD"
The address 2 for specifying the address is supplied. And after "preBUR-ODD" state, "BUR-ODD",
By alternately changing the "BUR-EVEN" state, data is sequentially output for each CPU cycle after the third CPU cycle.

[0026]

As described above,
In the conventional memory device, the time required to transfer the same number of data is increased by one CPU cycle in the burst access of odd address start, as compared with the burst access of even address start.

Therefore, in the conventional memory device, for example, when programming is performed by using a compiler, a large number of odd address start burst accesses are executed, burst access is used. Therefore, the effect of improving the access speed cannot be sufficiently obtained.

Therefore, an object of the present invention is to provide a memory device which can always complete access at high speed regardless of the address at which burst access is started.

[0029]

According to the first aspect of the present invention,
(A) An even address memory and an odd address memory having an access time of about 1 CPU cycle, and (b)
An even-numbered and odd-numbered address counter connected to each of the even-numbered address memory and the odd-numbered address memory for outputting an address designating data to be read from each memory, and (c) CP
When the address to start burst access supplied from U is supplied to the address counters for even addresses and odd addresses, and the address specifies the data stored in the memory for odd addresses, A first instruction means for instructing the address counter for even addresses to count up the address, and (d) C
Depending on the address supplied from the PU, either one of the even address memory and the odd address memory is defined as the memory to be read first, and the even address memory and the even address memory are synchronized with the CPU cycle of the CPU. Specifying means for specifying the memory for odd addresses as a memory for reading data alternately,
(E) In the CPU cycle in which the memory specified by the specifying means becomes ready to output data, the memory is instructed to output data and the address counter corresponding to the memory is instructed to count up the address. And second instructing means.

That is, according to the first aspect of the present invention, the contents of the two memories are read alternately according to the CPU cycle and the address corresponding to the burst access request is addressed to the memory device corresponding to the burst access. When the data stored in the memory is specified, the even number address counter that specifies the even address memory address is instructed to count up the address without depending on the CPU cycle. A first indicating means for performing is added. As a result, in the CPU cycle for outputting the first data requested to be accessed from the memory for odd addresses, the memory for even addresses can be prepared with the data to be output next.

According to a second aspect of the present invention, (a) a predetermined number of memories which are address interleaved and have an access time of about 1 CPU cycle; and (b) each memory which is connected to each of the predetermined number of memories. (D) a predetermined number of address counters for outputting an address designating data to be read, (d) a supply means for supplying an address for starting burst access supplied from the CPU to the predetermined number of address counters, and (e) burst. (F) a discriminating means for discriminating a memory which does not need to output the data of the address supplied to the corresponding address counter among the predetermined number of memories based on the address to be accessed.
First discriminating means for instructing the address counter corresponding to each of the memories discriminated that it is not necessary to output the data by the discriminating means, and (g) the address supplied from the CPU Accordingly, one of the predetermined number of memories is set as the memory to be read first, and the CPU of the CPU
In synchronization with the cycle, a specific means for cyclically identifying a predetermined number of memories as a memory for reading data,
(H) In a CPU cycle in which the memory specified by the specifying means is ready to output data, the memory is instructed to output data and the address counter corresponding to the memory is instructed to count up the address. And second instructing means.

That is, according to the second aspect of the present invention, the contents of a predetermined number of memories are cyclically read in accordance with the CPU cycle, and the memory device corresponding to the burst access request is supplied to the memory device corresponding to the burst access start address. Of the predetermined number of memories, a determination unit that determines a memory that does not need to output the data of the address supplied to the corresponding address counter, and a memory that the determination unit determines that the data does not need to be output. The first instruction means for instructing the count up of the address is added to the address counter corresponding to each of the above. This allows
While the data of the address to start the burst access is being output from one of the memories, the data to be output to another memory can be prepared.

[0033]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a schematic structure of a memory device according to an embodiment of the present invention. As shown in the figure, the memory device of the embodiment includes a memory controller 11, two address counters 12 _EVEN and 12 _ODD , two memory banks 13 _EVEN and 13 _ODD, and a LOAD signal generation circuit 14. There is.

The address counters 12 _EVEN and 12 _ODD are
Enable level signal “* L” from LOAD signal generation circuit 14
When "OAD" is input, the address on the address bus is taken in and the address is changed to "ADD EVEN",
"ADD ODD" as memory banks 13 _EVEN , 13 _ODD
It is a counter that outputs to, and when the enable level signal “* CE-EVEN” or “* CE-ODD” is input, it also counts up the address stored internally.

The memory banks 13 _EVEN and 13 _ODD are memory banks each having an access time of about 1 CPU cycle, and even-numbered address data is stored in the memory bank 1.
3 _{EV EN} has data of odd address in memory bank 13
Stored in _ODD . Memory bank 13 _EVEN , 13
_When the enable level signals “* OE-EVEN” and “* OE-ODD” are input from the memory controller 11, the _{ODDs receive} the data at the addresses specified by the address counters 12 _EVEN and 12 _ODD , respectively. Output on the data bus.

The memory controller 11 controls the control signals (* BURST, * ROMOE, * ROMC) input from a CPU (not shown).
S), clock (CLK), and signal (* CE-EVEN, * OE-EVEN, *) for controlling the address counter 12 and memory bank 13 based on the contents of the least significant bit A0 of the address bus.
CE-ODD, * OE-ODD) is a circuit to create, basically,
The state is changed in synchronization with the clock and a control signal of a level defined for each state is output. The LOAD signal generation circuit 14 is a circuit that generates a * LOAD signal based on control signals (* ROMOE, * ROMCS) and a clock (CLK) input from the CPU. Hereinafter, the operation of the memory controller and the LOAD signal generation circuit according to the embodiment will be described in detail with reference to the drawings.

FIG. 2 schematically shows how the state of the memory controller of the embodiment transits according to each signal from the CPU. As shown in the figure, the memory controller of the embodiment has “IDLE”, “SIM-EVEN”,
It is configured to respond to a memory access request from the CPU by transiting five states of "BUR-EVEN", "SIM-ODD", and "BUR-ODD" every CPU cycle.

When an access request is made from the CPU,
The memory controller is "! ROMCS & BURST &! A0", that is, the signal "* ROMCS" is "L" and the signal "* BURST" is "H".
When the least significant bit A0 of the address is "0", the "IDLE" state is transited to the "SIM-EVEN" state. Also, the signal "* ROMCS" is "L", and the signal "* BUR" is
When ST "is" H "and the least significant bit A0 is" 1 ", the state transits from the" IDLE "state to the" SIM-ODD "state.

"! ROMCS &! BURST &! A0", that is, the signal "* ROMCS" is "L" and the signal "* BURST" is "L".
When the least significant bit A0 of the address is “0”, the burst access is an even address start, and therefore the state transitions from the “IDLE” state to the “BUR-EVEN” state. Also, the signal "* ROMCS" is "L", and the signal "* BUR" is
When ST "is" L "and the least significant bit A0 is" 1 ", the burst access is an odd address start, so the transition from the" IDLE "state to the" BUR-ODD "state is performed.

Thereafter, when the signal "* ROMCS" from the CPU maintains "L", "BUR-EVEN", "BUR-
When the signal "* ROMCS" changes to "H", the transition from "BUR-EVEN" and "BUR-ODD" to "IDLE" is performed. SIM-EVE
The transition from "N", "SIM-ODD" to "IDLE" is also signal "* RO".
It is performed when MCS "becomes" H ".

FIG. 3 shows the level of each control signal output from the memory controller and the LOAD signal generating circuit in each of these states. As shown, in the memory device of the embodiment, the signal "* CE-EVEN" is controlled in synchronization with the CPU cycle in the states other than the "IDLE" state, but in the "IDLE" state, It is controlled asynchronously according to the least significant bit A0 of the address. Also,
The signal "* LOAD" is also controlled asynchronously, such as "! LOAD =! ROMCS & ROMOE &CLK".

By the memory controller and the LOAD signal generating circuit which output each control signal at such timing, the memory device of the embodiment operates as follows in response to a burst access request.

First, the operation at the time of starting an even address will be described with reference to the timing chart shown in FIG.

As shown in FIG. 4, in the first CPU cycle ("IDLE" state), C is placed on the address bus.
The start address supplied from PU is the enable level signal “* LOAD” output from the LOAD signal generation circuit.
The received address counters 12 _EVEN and 12 _ODD are loaded. And address counter 1
The 2 _{EV EN} and 12 _ODD supply the loaded start address (excluding the least significant bit) to each memory bank as "ADD EVEN" (address 0) and "ADD ODD" (address 1) as they are. Since the access time of each memory bank is about 1 CPU cycle as already described, the data output preparation is completed in the first CPU cycle where “ADD EVEN” and “ADD ODD” are supplied. Instead, the data output is ready for the next CPU cycle.

In this "IDLE" state, as shown in FIG. 3, the asynchronously controlled signal "* CE-EVEN".
_Will be supplied to the address counter 12 _EVEN. However, in this case, since the start address is an even number,
Apparently, the "H" level signal "* CE-EVEN" is supplied to the address counter 12 _EVEN in synchronization with the CPU cycle.

In the CPU cycle next to the "IDLE" state, the signal "* ROMCS" is "L" and the signal "* BURST" is "L".
Since the least significant bit A0 of the address is “0” (that is, even-numbered address start burst access), the memory controller 21 takes the “BUR-EVEN” state and sends the address counter 12 _EVEN with the address. "L" level signal "* C" that instructs to count up
"E-EVEN" (see Fig. 3) is output, and memory bank 1
A signal "* OE-EVEN" (not shown) of "L" level for instructing output of data to the data bus is output to 3 _EVEN .

Therefore, at the end of this "BUR-EVEN" state, the address in the address counter 12 _EVEN is incremented, and the signal "* RADY" is set to "L" in this CPU cycle. Therefore, the data of the address 0 supplied from the memory bank 13 _EVEN onto the data bus is stored in the CPU.

As shown in FIG. 3, the third CPU
If burst mode was still active at the beginning of the cycle, the memory controller will use the “BUR-ODD
It shifts to the “state” and the enable level signal “* OE-O
By outputting "DD" (not shown), the memory bank 13 _ODD is instructed to output data, and the enable level signal "* CE-ODD" is output to the address counter 12 _ODD . On the other hand, it instructs the counter to increment the address stored internally.

In the memory device of the embodiment, such data output (repetition of two states of "BUR-EVEN" and "BUR-ODD") continues as long as the signal "* BURST" is "L". Then, when the signal “* BURST” or “* ROMCS” is disabled, the data output from the memory is stopped.

Next, the operation at the time of starting the odd address will be described with reference to FIG.

As shown in FIG. 5, in the first CPU cycle ("IDLE" state), C is placed on the address bus.
The start address supplied from PU is the enable level signal “* LOAD” output from the LOAD signal generation circuit.
The received address counters 12 _EVEN and 12 _ODD are loaded to the address counters 12 _EVEN and 12 _ODD , and the loaded start addresses (excluding the least significant bit) are directly read as “ADD EVEN” (address 0) and “ADD ODD "(Address 1)
Is supplied to each memory bank.

At this time, since the least significant bit AO of the address is "1", the memory controller outputs the signal "* CE-EVEN" which changes asynchronously as shown in the figure. The address counter 12 _{EVEN which} has received “* CE-EVEN” starts counting up the addresses stored therein. As a result, the address in the address counter 12 _EVEN is counted up at the end of the "IDLE" state. It is to be noted that the LOAD signal generation circuit 14 is caused to generate the "* LOAD" signal asynchronous with the CPU cycle by the address counter 12
_This is because it is possible to count up _EVEN .

The signal "* ROMCS" is "L", the signal "* BURST" is "L", and the least significant bit A0 of the address is
Is "1", the memory device transits to the "BUR-ODD" state in the next CPU cycle, and the memory controller instructs the address counter 12 _ODD to count up the address "L". Level signal “* C
E-ODD "and" L "that instructs the memory bank 13 _ODD to output data to the data bus
The level signal "* OE-ODD" (not shown) is output.

Also in the third CPU cycle, if the burst mode is continued, the memory controller shifts to the "BUR-EVEN" state and outputs the enable level signal "* CE-EVEN". The address counter 12 _ODD is instructed to count up the address stored therein, and the enable level signal "* OE-EVEN" is output (not shown).
Thus, the memory bank 13 _EVEN is instructed to output data. As described above, at the time of odd number address start, the count-up of the address counter is started in the “IDLE” state, and the data 2 is ready to be output in this third CPU cycle. It is possible to issue a data output instruction in the "EVEN" state.

After that, as long as the signal "* BURST" is "L", the "BUR-ODD" and "BUR-EVEN" states are repeated, and the data from the specified address is sequentially supplied to the data bus. It will be.

As described above, in the memory device of the embodiment, since the asynchronous control is added to a part of the control of the memory bank, the address counter can start counting up in the first CPU cycle. There is.
Therefore, even in the burst access starting with an odd address, the second data required can be prepared in the third CPU cycle, and, in the end, even in the burst access starting with an odd address or an even address,
Data can be continuously supplied to the CPU from the second CPU cycle.

Further, in the CPU cycle except when the access is started, it is only necessary to perform the control in synchronism with the CPU cycle, so that it is possible to easily and easily develop the optimum memory device for the system.

Although the memory device of the embodiment specifies the memory bank to be used from the two memory banks by A0, the bit used to specify the memory bank is determined according to the system configuration and the usage of the memory. Of course may be changed to another bit.

Further, although the memory device of the embodiment is a device constituted by two memory banks, the number of memory banks to which the present invention can be applied is not particularly limited, and CP
If the memory controller is configured so that the count-up is instructed in the first CPU cycle for the memory bank that does not require the output of the start address data supplied from U, the number of memory banks can be increased. Even if there is a burst access that starts at any address, C is always used from the second CPU cycle.
A memory device capable of sequentially outputting data for each PU cycle can be configured.

For example, as shown schematically in FIG. 6, when a memory device is constructed using four memory banks, the data to be output next to memory bank 0 is stored in memory bank 1 and in memory bank 1. When address interleaving is performed such that the data to be output after 1 is to the memory bank 2, for example, during burst access starting from the memory bank 1, only the address counter 0 is addressed in the “IDLE” state. 7 is issued, and at the time of burst access starting from the memory bank 3, an address count-up instruction is issued to the address counters 0 to 2, as shown as an example in FIG. First data (data 3) at 2 CPU cycle
Then, the data can be sequentially output every CPU cycle.

[0062]

As described above in detail, according to the memory device of the present invention, burst access, which has been conventionally slow depending on the start address, can be performed.
It can always be completed at high speed regardless of the start address.

This effect is particularly remarkable when the number of data to be accessed in one burst access is small, and the memory device of the two-bank configuration as in the invention of claim 1 and the conventional memory of the two-bank configuration are provided. When comparing the devices,
For example, if four data are accessed in one burst access and odd and even address starts are performed on average, the time required for one burst access is reduced by about 10%.

Further, when the memory device is configured by using more memories as in the second aspect of the invention, the burst access speed is higher than that of the conventional memory device. Therefore, a remarkable effect can be obtained.

For this reason, when the memory device of the present invention is used in a device such as a fax machine or a copying machine, which frequently accesses a small amount of data in burst, as compared with a device using a conventional memory device. It is possible to obtain a device that operates at a particularly high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention.

FIG. 2 is a state transition diagram of a memory controller provided in the memory device according to the embodiment.

FIG. 3 is an explanatory diagram showing a control signal level output in each state by a memory controller and a LOAD signal generation circuit provided in the memory device of the embodiment.

FIG. 4 is a timing chart when burst access starting with an even address is performed on the memory device of the embodiment.

FIG. 5 is a timing chart when burst access starting at an odd address is performed on the memory device of the embodiment.

FIG. 6 is a block diagram showing another example of a memory device to which the present invention can be applied.

7 is a timing chart showing an example of a burst access procedure in the memory device having the configuration shown in FIG. 6 to which the present invention is applied.

FIG. 8 is a schematic configuration diagram of a system using a CPU capable of burst access.

FIG. 9 is a timing chart for explaining burst access.

FIG. 10 is a block diagram showing a schematic configuration of a conventional memory device.

FIG. 11 is a state transition diagram of a memory controller provided in a conventional memory device.

FIG. 12 is an explanatory diagram showing a control signal level output in each state by a memory controller provided in a conventional memory device.

FIG. 13 is a timing chart when a burst access starting with an even address is performed on a conventional memory device.

FIG. 14 is a timing chart when performing a burst access starting with an odd address in a conventional memory device.

[Explanation of symbols]

11, 21 ... Memory controller, 12, 22 ... Address counter, 13, 23 ... Memory bank, 14 ... LOAD signal generation circuit, 31 ... CPU, 32 ... Memory device

Claims (2)

[Claims] 1. An even-numbered address memory and an odd-numbered address memory having an access time of about 1 CPU cycle, and an address for specifying data to be read from each memory connected to each of the even-numbered address memory and the odd-numbered address memory. An even-numbered and odd-numbered address counter for outputting, and an address for starting burst access, which is supplied from the CPU, are supplied to the even-numbered address and odd-numbered address counter, and the address is for an odd-numbered address. When the data stored in the memory is designated, a first instruction means for instructing the address counter for even addresses to count up the address, and the even address depending on the address supplied from the CPU For memory and odd One of the memories for several addresses is defined as a memory to be read first, and the memory for even addresses and the memory for odd addresses are alternately read out in synchronization with the CPU cycle of the CPU. In the CPU cycle in which the memory specified by the specifying means and the memory specified by the specifying means are ready to output data, the memory is instructed to output the data, and the address counter corresponding to the memory is addressed. And a second instructing means for instructing the count-up of the memory device. 2. A predetermined number of memories which are address-interleaved and have an access time of about 1 CPU cycle, and a predetermined memory which is connected to each of the predetermined memories and which outputs an address designating data to be read from each memory. Number of address counters, supply means for supplying an address to start burst access, which is supplied from the CPU, to the predetermined number of address counters, and based on the addresses to start burst access, Of these, a determination unit that determines the memory that does not need to output the data of the address supplied to the corresponding address counter, and an address that corresponds to each of the memories that are determined not to output the data by this determination unit. First instruction to instruct counter to count up address And one of the predetermined number of memories is defined as a memory to be read first according to the number of stages and the address supplied from the CPU, and the predetermined number of memories is synchronized with the CPU cycle of the CPU. Cyclically specifying the memory as the memory for reading the data, and in the CPU cycle in which the memory specified by the specifying means is ready to output the data, the memory is instructed to output the data. A second instruction means for instructing the address counter corresponding to the memory to count up the address.